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Thu, 28 Dec 2023 04:05:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IElX7lCg1r81+3uWkpG6uxjTf4djKKphGFbDX2bDHAZSeqvkQoq6AHrhkw/4e5YYTTV685L8g== X-Received: by 2002:a05:600c:4e11:b0:40d:6c73:b8c with SMTP id b17-20020a05600c4e1100b0040d6c730b8cmr180687wmq.367.1703765124030; Thu, 28 Dec 2023 04:05:24 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org Subject: [PATCH v2] tcg/i386: convert add/sub of 128 to sub/add of -128 Date: Thu, 28 Dec 2023 13:05:14 +0100 Message-ID: <20231228120514.70205-1-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.755, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1703765185327100007 Content-Type: text/plain; charset="utf-8" Extend the existing conditional that generates INC/DEC, to also swap an ADD for a SUB and vice versa when the immediate is 128. This facilitates using OPC_ARITH_EvIb instead of OPC_ARITH_EvIz. Best reviewed with "git diff -b". Signed-off-by: Paolo Bonzini --- tcg/i386/tcg-target.c.inc | 40 +++++++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 16 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index a83f8aab304..1791b959738 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1316,23 +1316,31 @@ static void tgen_arithi(TCGContext *s, int c, int r= 0, c &=3D 7; } =20 - /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce - partial flags update stalls on Pentium4 and are not recommended - by current Intel optimization manuals. */ - if (!cf && (c =3D=3D ARITH_ADD || c =3D=3D ARITH_SUB) && (val =3D=3D 1= || val =3D=3D -1)) { - int is_inc =3D (c =3D=3D ARITH_ADD) ^ (val < 0); - if (TCG_TARGET_REG_BITS =3D=3D 64) { - /* The single-byte increment encodings are re-tasked as the - REX prefixes. Use the MODRM encoding. */ - tcg_out_modrm(s, OPC_GRP5 + rexw, - (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0); - } else { - tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0); + if (!cf && (c =3D=3D ARITH_ADD || c =3D=3D ARITH_SUB)) { + /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce + partial flags update stalls on Pentium4 and are not recommended + by current Intel optimization manuals. */ + if (val =3D=3D 1 || val =3D=3D -1) { + int is_inc =3D (c =3D=3D ARITH_ADD) ^ (val < 0); + if (TCG_TARGET_REG_BITS =3D=3D 64) { + /* The single-byte increment encodings are re-tasked as the + REX prefixes. Use the MODRM encoding. */ + tcg_out_modrm(s, OPC_GRP5 + rexw, + (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0); + } else { + tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0); + } + return; } - return; - } - - if (c =3D=3D ARITH_AND) { + if (val =3D=3D 128) { + /* + * Facilitate using an 8-bit immediate. Carry is inverted + * by this transformation, so do it only if cf =3D=3D 0. + */ + c ^=3D ARITH_ADD ^ ARITH_SUB; + val =3D -128; + } + } else if (c =3D=3D ARITH_AND) { if (TCG_TARGET_REG_BITS =3D=3D 64) { if (val =3D=3D 0xffffffffu) { tcg_out_ext32u(s, r0, r0); --=20 2.43.0