From nobody Wed Nov 27 00:30:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703753738545907.2716325712308; Thu, 28 Dec 2023 00:55:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rImAy-0007xY-Ec; Thu, 28 Dec 2023 03:55:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rImAw-0007wt-Bv for qemu-devel@nongnu.org; Thu, 28 Dec 2023 03:55:34 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rImAu-0007sc-99 for qemu-devel@nongnu.org; Thu, 28 Dec 2023 03:55:34 -0500 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxF_CiN41lIAIAAA--.83S3; Thu, 28 Dec 2023 16:53:54 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxD+WYN41lQvENAA--.48131S10; Thu, 28 Dec 2023 16:53:53 +0800 (CST) From: Tianrui Zhao To: qemu-devel@nongnu.org Cc: gaosong@loongson.cn, maobibo@loongson.cn, zhaotianrui@loongson.cn, mst@redhat.com, cohuck@redhat.com, pbonzini@redhat.com, marcandre.lureau@redhat.com, berrange@redhat.com, thuth@redhat.com, philmd@linaro.org, richard.henderson@linaro.org, peter.maydell@linaro.org, yangxiaojuan@loongson.cn, xianglai li Subject: [PATCH v3 8/9] target/loongarch: Implement set vcpu intr for kvm Date: Thu, 28 Dec 2023 16:40:50 +0800 Message-Id: <20231228084051.3235354-9-zhaotianrui@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20231228084051.3235354-1-zhaotianrui@loongson.cn> References: <20231228084051.3235354-1-zhaotianrui@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8AxD+WYN41lQvENAA--.48131S10 X-CM-SenderInfo: p2kd03xldq233l6o00pqjv00gofq/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=zhaotianrui@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1703753739221100001 Content-Type: text/plain; charset="utf-8" Implement loongarch kvm set vcpu interrupt interface, when a irq is set in vcpu, we use the KVM_INTERRUPT ioctl to set intr into kvm. Signed-off-by: Tianrui Zhao Signed-off-by: xianglai li Reviewed-by: Song Gao --- target/loongarch/cpu.c | 32 +++++++++++++++++++++++--------- target/loongarch/kvm.c | 15 +++++++++++++++ target/loongarch/kvm_loongarch.h | 16 ++++++++++++++++ target/loongarch/trace-events | 1 + 4 files changed, 55 insertions(+), 9 deletions(-) create mode 100644 target/loongarch/kvm_loongarch.h diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 83899c673f..caf82f9133 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -11,7 +11,6 @@ #include "qapi/error.h" #include "qemu/module.h" #include "sysemu/qtest.h" -#include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "cpu.h" #include "internals.h" @@ -20,8 +19,16 @@ #ifndef CONFIG_USER_ONLY #include "sysemu/reset.h" #endif -#include "tcg/tcg.h" #include "vec.h" +#include "sysemu/kvm.h" +#include "kvm_loongarch.h" +#ifdef CONFIG_KVM +#include +#endif +#ifdef CONFIG_TCG +#include "exec/cpu_ldst.h" +#include "tcg/tcg.h" +#endif =20 const char * const regnames[32] =3D { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", @@ -110,12 +117,15 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int= level) return; } =20 - env->CSR_ESTAT =3D deposit64(env->CSR_ESTAT, irq, 1, level !=3D 0); - - if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); + if (kvm_enabled()) { + kvm_loongarch_set_interrupt(cpu, irq, level); } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + env->CSR_ESTAT =3D deposit64(env->CSR_ESTAT, irq, 1, level !=3D 0); + if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } } } =20 @@ -140,7 +150,9 @@ static inline bool cpu_loongarch_hw_interrupts_pending(= CPULoongArchState *env) =20 return (pending & status) !=3D 0; } +#endif =20 +#ifdef CONFIG_TCG static void loongarch_cpu_do_interrupt(CPUState *cs) { LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); @@ -320,9 +332,7 @@ static bool loongarch_cpu_exec_interrupt(CPUState *cs, = int interrupt_request) } return false; } -#endif =20 -#ifdef CONFIG_TCG static void loongarch_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -560,7 +570,9 @@ static void loongarch_cpu_reset_hold(Object *obj) } #endif =20 +#ifdef CONFIG_TCG restore_fp_status(env); +#endif cs->exception_index =3D -1; } =20 @@ -802,7 +814,9 @@ static struct TCGCPUOps loongarch_tcg_ops =3D { #include "hw/core/sysemu-cpu-ops.h" =20 static const struct SysemuCPUOps loongarch_sysemu_ops =3D { +#ifdef CONFIG_TCG .get_phys_page_debug =3D loongarch_cpu_get_phys_page_debug, +#endif }; =20 static int64_t loongarch_cpu_get_arch_id(CPUState *cs) diff --git a/target/loongarch/kvm.c b/target/loongarch/kvm.c index d2dab3fef4..bd33ec2114 100644 --- a/target/loongarch/kvm.c +++ b/target/loongarch/kvm.c @@ -748,6 +748,21 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run = *run) return ret; } =20 +int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level) +{ + struct kvm_interrupt intr; + CPUState *cs =3D CPU(cpu); + + if (level) { + intr.irq =3D irq; + } else { + intr.irq =3D -irq; + } + + trace_kvm_set_intr(irq, level); + return kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &intr); +} + void kvm_arch_accel_class_init(ObjectClass *oc) { } diff --git a/target/loongarch/kvm_loongarch.h b/target/loongarch/kvm_loonga= rch.h new file mode 100644 index 0000000000..d945b6bb82 --- /dev/null +++ b/target/loongarch/kvm_loongarch.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU LoongArch kvm interface + * + * Copyright (c) 2023 Loongson Technology Corporation Limited + */ + +#include "cpu.h" + +#ifndef QEMU_KVM_LOONGARCH_H +#define QEMU_KVM_LOONGARCH_H + +int kvm_loongarch_set_interrupt(LoongArchCPU *cpu, int irq, int level); +void kvm_arch_reset_vcpu(CPULoongArchState *env); + +#endif diff --git a/target/loongarch/trace-events b/target/loongarch/trace-events index 021839880e..dea11edc0f 100644 --- a/target/loongarch/trace-events +++ b/target/loongarch/trace-events @@ -12,3 +12,4 @@ kvm_failed_put_counter(const char *msg) "Failed to put co= unter into KVM: %s" kvm_failed_get_cpucfg(const char *msg) "Failed to get cpucfg from KVM: %s" kvm_failed_put_cpucfg(const char *msg) "Failed to put cpucfg into KVM: %s" kvm_arch_handle_exit(int num) "kvm arch handle exit, the reason number: %d" +kvm_set_intr(int irq, int level) "kvm set interrupt, irq num: %d, level: %= d" --=20 2.39.1