From nobody Wed Nov 27 00:26:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703665410951604.2593526561803; Wed, 27 Dec 2023 00:23:30 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rIPAe-0006OQ-DF; Wed, 27 Dec 2023 03:21:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rIPAZ-0006MU-Hc for qemu-devel@nongnu.org; Wed, 27 Dec 2023 03:21:39 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rIPAX-0002Lc-Ef for qemu-devel@nongnu.org; Wed, 27 Dec 2023 03:21:39 -0500 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxGOiD3otlUvcEAA--.1001S3; Wed, 27 Dec 2023 16:21:23 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bxib153otly4QMAA--.16227S16; Wed, 27 Dec 2023 16:21:23 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, peter.maydell@linaro.org, philmd@linaro.org, maobibo@loongson.cn Subject: [PATCH v3 14/17] hw/loongarch: fdt adds pcie irq_map node Date: Wed, 27 Dec 2023 16:08:18 +0800 Message-Id: <20231227080821.3216113-15-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20231227080821.3216113-1-gaosong@loongson.cn> References: <20231227080821.3216113-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8Bxib153otly4QMAA--.16227S16 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1703665411901100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Song Gao --- hw/loongarch/virt.c | 73 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 69 insertions(+), 4 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 3b300187b2..f12791036c 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -316,7 +316,62 @@ static void fdt_add_fw_cfg_node(const LoongArchMachine= State *lams) g_free(nodename); } =20 -static void fdt_add_pcie_node(const LoongArchMachineState *lams) +static void fdt_add_pcie_irq_map_node(const LoongArchMachineState *lams, + char *nodename, + uint32_t *pch_pic_phandle) +{ + int pin, dev; + uint32_t irq_map_stride =3D 0; + uint32_t full_irq_map[GPEX_NUM_IRQS *GPEX_NUM_IRQS * 10] =3D {}; + uint32_t *irq_map =3D full_irq_map; + const MachineState *ms =3D MACHINE(lams); + + /* This code creates a standard swizzle of interrupts such that + * each device's first interrupt is based on it's PCI_SLOT number. + * (See pci_swizzle_map_irq_fn()) + * + * We only need one entry per interrupt in the table (not one per + * possible slot) seeing the interrupt-map-mask will allow the table + * to wrap to any number of devices. + */ + + for (dev =3D 0; dev < GPEX_NUM_IRQS; dev++) { + int devfn =3D dev * 0x8; + + for (pin =3D 0; pin < GPEX_NUM_IRQS; pin++) { + int irq_nr =3D 16 + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); + int i =3D 0; + + /* Fill PCI address cells */ + irq_map[i] =3D cpu_to_be32(devfn << 8); + i +=3D 3; + + /* Fill PCI Interrupt cells */ + irq_map[i] =3D cpu_to_be32(pin + 1); + i +=3D 1; + + /* Fill interrupt controller phandle and cells */ + irq_map[i++] =3D cpu_to_be32(*pch_pic_phandle); + irq_map[i++] =3D cpu_to_be32(irq_nr); + + if (!irq_map_stride) { + irq_map_stride =3D i; + } + irq_map +=3D irq_map_stride; + } + } + + + qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map, + GPEX_NUM_IRQS * GPEX_NUM_IRQS * + irq_map_stride * sizeof(uint32_t)); + qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", + 0x1800, 0, 0, 0x7); +} + +static void fdt_add_pcie_node(const LoongArchMachineState *lams, + uint32_t *pch_pic_phandle, + uint32_t *pch_msi_phandle) { char *nodename; hwaddr base_mmio =3D VIRT_PCI_MEM_BASE; @@ -347,6 +402,11 @@ static void fdt_add_pcie_node(const LoongArchMachineSt= ate *lams) 2, base_pio, 2, size_pio, 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 2, base_mmio, 2, size_mmio); + qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", + 0, *pch_msi_phandle, 0, 0x10000); + + fdt_add_pcie_irq_map_node(lams, nodename, pch_pic_phandle); + g_free(nodename); } =20 @@ -505,7 +565,10 @@ static DeviceState *create_platform_bus(DeviceState *p= ch_pic) return dev; } =20 -static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineS= tate *lams) +static void loongarch_devices_init(DeviceState *pch_pic, + LoongArchMachineState *lams, + uint32_t *pch_pic_phandle, + uint32_t *pch_msi_phandle) { MachineClass *mc =3D MACHINE_GET_CLASS(lams); DeviceState *gpex_dev; @@ -551,6 +614,9 @@ static void loongarch_devices_init(DeviceState *pch_pic= , LoongArchMachineState * gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); } =20 + /* Add pcie node */ + fdt_add_pcie_node(lams, pch_pic_phandle, pch_msi_phandle); + serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, qdev_get_gpio_in(pch_pic, VIRT_UART_IRQ - VIRT_GSI_BASE), @@ -702,7 +768,7 @@ static void loongarch_irq_init(LoongArchMachineState *l= ams) /* Add PCH MSI node */ fdt_add_pch_msi_node(lams, &eiointc_phandle, &pch_msi_phandle); =20 - loongarch_devices_init(pch_pic, lams); + loongarch_devices_init(pch_pic, lams, &pch_pic_phandle, &pch_msi_phand= le); } =20 static void loongarch_firmware_init(LoongArchMachineState *lams) @@ -863,7 +929,6 @@ static void loongarch_init(MachineState *machine) lams->powerdown_notifier.notify =3D virt_powerdown_req; qemu_register_powerdown_notifier(&lams->powerdown_notifier); =20 - fdt_add_pcie_node(lams); /* * Since lowmem region starts from 0 and Linux kernel legacy start add= ress * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer --=20 2.25.1