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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=luxu.kernel@bytedance.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 26 Dec 2023 00:29:12 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @bytedance.com) X-ZM-MESSAGEID: 1703568621567100001 Content-Type: text/plain; charset="utf-8" The mcycle/minstret counter's stop flag is mistakenly updated on a copy on stack. Thus the counter increments even when the CY/IR bit in the mcountinhibit register is set. This commit corrects its behavior. Fixes: 3780e33732f88 (target/riscv: Support mcycle/minstret write operation) Signed-off-by: Xu Lu Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/csr.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fde7ce1a5336..c50a33397c51 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -907,11 +907,11 @@ static int write_mhpmcounterh(CPURISCVState *env, int= csrno, target_ulong val) static RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong = *val, bool upper_half, uint32_t ctr_idx) { - PMUCTRState counter =3D env->pmu_ctrs[ctr_idx]; - target_ulong ctr_prev =3D upper_half ? counter.mhpmcounterh_prev : - counter.mhpmcounter_prev; - target_ulong ctr_val =3D upper_half ? counter.mhpmcounterh_val : - counter.mhpmcounter_val; + PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; + target_ulong ctr_prev =3D upper_half ? counter->mhpmcounterh_prev : + counter->mhpmcounter_prev; + target_ulong ctr_val =3D upper_half ? counter->mhpmcounterh_val : + counter->mhpmcounter_val; =20 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { /* @@ -919,12 +919,12 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVStat= e *env, target_ulong *val, * stop the icount counting. Just return the counter value written= by * the supervisor to indicate that counter was not incremented. */ - if (!counter.started) { + if (!counter->started) { *val =3D ctr_val; return RISCV_EXCP_NONE; } else { /* Mark that the counter has been stopped */ - counter.started =3D false; + counter->started =3D false; } } =20 --=20 2.20.1