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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=baturo.alexey@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1703393428282100007 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/translate.c | 23 +++++++++++++++++++++-- target/riscv/vector_helper.c | 10 ++++++++++ 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1eb501e0d3..c0c5030e05 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -575,11 +575,20 @@ static void gen_jal(DisasContext *ctx, int rd, target= _ulong imm) /* Compute a canonical address from a register plus offset. */ static TCGv get_address(DisasContext *ctx, int rs1, int imm) { + int pmlen =3D riscv_pm_get_pmlen(ctx->pm_pmm); TCGv addr =3D tcg_temp_new(); TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_addi_tl(addr, src1, imm); - if (get_address_xl(ctx) =3D=3D MXL_RV32) { + if (ctx->pm_pmm) { + tcg_gen_shli_tl(addr, addr, pmlen); + /* sign extend address by first non-masked bit otherwise zero exte= nd */ + if (ctx->pm_signext) { + tcg_gen_sari_tl(addr, addr, pmlen); + } else { + tcg_gen_shri_tl(addr, addr, pmlen); + } + } else if (get_address_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } =20 @@ -589,11 +598,21 @@ static TCGv get_address(DisasContext *ctx, int rs1, i= nt imm) /* Compute a canonical address from a register plus reg offset. */ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) { + int pmlen =3D riscv_pm_get_pmlen(ctx->pm_pmm); TCGv addr =3D tcg_temp_new(); TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_add_tl(addr, src1, offs); - if (get_xl(ctx) =3D=3D MXL_RV32) { + /* sign extend address by first non-masked bit */ + if (ctx->pm_pmm) { + tcg_gen_shli_tl(addr, addr, pmlen); + /* sign extend address by first non-masked bit otherwise zero exte= nd */ + if (ctx->pm_signext) { + tcg_gen_sari_tl(addr, addr, pmlen); + } else { + tcg_gen_shri_tl(addr, addr, pmlen); + } + } else if (get_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } return addr; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8e7a8e80a0..faa8f5820d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -94,6 +94,16 @@ static inline uint32_t vext_max_elems(uint32_t desc, uin= t32_t log2_esz) =20 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) { + RISCVPmPmm pmm =3D riscv_pm_get_pmm(env); + int pmlen =3D riscv_pm_get_pmlen(pmm); + bool signext =3D !riscv_cpu_bare_mode(env); + addr =3D addr << pmlen; + /* sign/zero extend masked address by N-1 bit */ + if (signext) { + addr =3D (target_long)addr >> pmlen; + } else { + addr =3D addr >> pmlen; + } return addr; } =20 --=20 2.34.1