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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=baturo.alexey@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1703393413954100001 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 15 +++++++++------ target/riscv/cpu_helper.c | 3 +++ target/riscv/translate.c | 5 +++++ 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c607a94bba..038b86db4b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -538,14 +538,17 @@ FIELD(TB_FLAGS, VILL, 14, 1) FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 16, 2) -FIELD(TB_FLAGS, VTA, 18, 1) -FIELD(TB_FLAGS, VMA, 19, 1) +/* If pointer masking should be applied and address sign extended */ +FIELD(TB_FLAGS, PM_PMM, 18, 2) +FIELD(TB_FLAGS, PM_SIGNEXTEND, 20, 1) +FIELD(TB_FLAGS, VTA, 21, 1) +FIELD(TB_FLAGS, VMA, 22, 1) /* Native debug itrigger */ -FIELD(TB_FLAGS, ITRIGGER, 20, 1) +FIELD(TB_FLAGS, ITRIGGER, 23, 1) /* Virtual mode enabled */ -FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) -FIELD(TB_FLAGS, PRIV, 22, 2) -FIELD(TB_FLAGS, AXL, 24, 2) +FIELD(TB_FLAGS, VIRT_ENABLED, 24, 1) +FIELD(TB_FLAGS, PRIV, 25, 2) +FIELD(TB_FLAGS, AXL, 27, 2) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 47f325294e..7c33369cf1 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -68,6 +68,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, RISCVCPU *cpu =3D env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags =3D 0; + bool pm_signext =3D !riscv_cpu_bare_mode(env); =20 *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; *cs_base =3D 0; @@ -135,6 +136,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 *pflags =3D flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 6b4b9a671c..1eb501e0d3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -103,6 +103,9 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; + /* pointer masking extension */ + uint8_t pm_pmm; + bool pm_signext; /* Use icount trigger for native debug */ bool itrigger; /* FRM is known to contain a valid value. */ @@ -1176,6 +1179,8 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; + ctx->pm_pmm =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM); + ctx->pm_signext =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND); ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; --=20 2.34.1