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Fri, 22 Dec 2023 10:16:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IHFfxgj3JMehyksYOgvesLE//e9HgnPQAlTaj6fyZMKDdE7pCp9FQq4CvetvulhoKRn0DJ87A== X-Received: by 2002:a50:aa94:0:b0:554:347a:4f58 with SMTP id q20-20020a50aa94000000b00554347a4f58mr924104edc.66.1703268985351; Fri, 22 Dec 2023 10:16:25 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 10/22] target/i386: add X86_SPECIALs for MOVSX and MOVZX Date: Fri, 22 Dec 2023 19:15:51 +0100 Message-ID: <20231222181603.174137-11-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222181603.174137-1-pbonzini@redhat.com> References: <20231222181603.174137-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1703269118536100004 Content-Type: text/plain; charset="utf-8" Usually the registers are just moved into s->T0 without much care for their operand size. However, in some cases we can get more efficient code if the operand fetching logic syncs with the emission function on what is nicer. All the current uses are mostly demonstrative and only reduce the code in the emission functions, because the instructions do not support memory operands. However the logic is generic and applies to several more instructions such as MOVSXD (aka movslq), one-byte shift instructions, multiplications, XLAT, and indirect calls/jumps. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/decode-new.c.inc | 18 ++++++++++---- target/i386/tcg/decode-new.h | 4 +++ target/i386/tcg/emit.c.inc | 42 +++++++++++++++++--------------- 3 files changed, 40 insertions(+), 24 deletions(-) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index 00fdb243857..d7a86d96c0c 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -156,6 +156,8 @@ #define op0_Rd .special =3D X86_SPECIAL_Op0_Rd, #define op2_Ry .special =3D X86_SPECIAL_Op2_Ry, #define avx_movx .special =3D X86_SPECIAL_AVXExtMov, +#define sextT0 .special =3D X86_SPECIAL_SExtT0, +#define zextT0 .special =3D X86_SPECIAL_ZExtT0, =20 #define vex1 .vex_class =3D 1, #define vex1_rep3 .vex_class =3D 1, .vex_special =3D X86_VEX_REPScalar, @@ -571,8 +573,8 @@ static const X86OpEntry opcodes_0F38_F0toFF[16][5] =3D { [5] =3D { X86_OP_ENTRY3(BZHI, G,y, E,y, B,y, vex13 cpuid(BMI1)), {}, - X86_OP_ENTRY3(PEXT, G,y, B,y, E,y, vex13 cpuid(BMI2)), - X86_OP_ENTRY3(PDEP, G,y, B,y, E,y, vex13 cpuid(BMI2)), + X86_OP_ENTRY3(PEXT, G,y, B,y, E,y, vex13 zextT0 cpuid(BMI2)), + X86_OP_ENTRY3(PDEP, G,y, B,y, E,y, vex13 zextT0 cpuid(BMI2)), {}, }, [6] =3D { @@ -583,10 +585,10 @@ static const X86OpEntry opcodes_0F38_F0toFF[16][5] = =3D { {}, }, [7] =3D { - X86_OP_ENTRY3(BEXTR, G,y, E,y, B,y, vex13 cpuid(BMI1)), + X86_OP_ENTRY3(BEXTR, G,y, E,y, B,y, vex13 zextT0 cpuid(BMI1)), X86_OP_ENTRY3(SHLX, G,y, E,y, B,y, vex13 cpuid(BMI1)), - X86_OP_ENTRY3(SARX, G,y, E,y, B,y, vex13 cpuid(BMI1)), - X86_OP_ENTRY3(SHRX, G,y, E,y, B,y, vex13 cpuid(BMI1)), + X86_OP_ENTRY3(SARX, G,y, E,y, B,y, vex13 sextT0 cpuid(BMI1)), + X86_OP_ENTRY3(SHRX, G,y, E,y, B,y, vex13 zextT0 cpuid(BMI1)), {}, }, }; @@ -1905,6 +1907,12 @@ static void disas_insn_new(DisasContext *s, CPUState= *cpu, int b) } break; =20 + case X86_SPECIAL_SExtT0: + case X86_SPECIAL_ZExtT0: + /* Handled in gen_load. */ + assert(decode.op[1].unit =3D=3D X86_OP_INT); + break; + default: break; } diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h index b253f7457ae..70b6717227f 100644 --- a/target/i386/tcg/decode-new.h +++ b/target/i386/tcg/decode-new.h @@ -191,6 +191,10 @@ typedef enum X86InsnSpecial { * become P/P/Q/N, and size "x" becomes "q". */ X86_SPECIAL_MMX, + + /* When loaded into s->T0, register operand 1 is zero/sign extended. = */ + X86_SPECIAL_SExtT0, + X86_SPECIAL_ZExtT0, } X86InsnSpecial; =20 /* diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index f5e44117eab..4c2006fdd09 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -232,9 +232,30 @@ static void gen_load(DisasContext *s, X86DecodedInsn *= decode, int opn, TCGv v) break; case X86_OP_INT: if (op->has_ea) { - gen_op_ld_v(s, op->ot, v, s->A0); + if (v =3D=3D s->T0 && decode->e.special =3D=3D X86_SPECIAL_SEx= tT0) { + gen_op_ld_v(s, op->ot | MO_SIGN, v, s->A0); + } else { + gen_op_ld_v(s, op->ot, v, s->A0); + } + + } else if (op->ot =3D=3D MO_8 && byte_reg_is_xH(s, op->n)) { + if (v =3D=3D s->T0 && decode->e.special =3D=3D X86_SPECIAL_SEx= tT0) { + tcg_gen_sextract_tl(v, cpu_regs[op->n - 4], 8, 8); + } else { + tcg_gen_extract_tl(v, cpu_regs[op->n - 4], 8, 8); + } + + } else if (op->ot < MO_TL && v =3D=3D s->T0 && + (decode->e.special =3D=3D X86_SPECIAL_SExtT0 || + decode->e.special =3D=3D X86_SPECIAL_ZExtT0)) { + if (decode->e.special =3D=3D X86_SPECIAL_SExtT0) { + tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot | MO_SIGN); + } else { + tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot); + } + } else { - gen_op_mov_v_reg(s, op->ot, v, op->n); + tcg_gen_mov_tl(v, cpu_regs[op->n]); } break; case X86_OP_IMM: @@ -1084,9 +1105,6 @@ static void gen_BEXTR(DisasContext *s, CPUX86State *e= nv, X86DecodedInsn *decode) * Shifts larger than operand size get zeros. */ tcg_gen_ext8u_tl(s->A0, s->T1); - if (TARGET_LONG_BITS =3D=3D 64 && ot =3D=3D MO_32) { - tcg_gen_ext32u_tl(s->T0, s->T0); - } tcg_gen_shr_tl(s->T0, s->T0, s->A0); =20 tcg_gen_movcond_tl(TCG_COND_LEU, s->T0, s->A0, bound, s->T0, zero); @@ -1428,19 +1446,11 @@ static void gen_PCMPISTRM(DisasContext *s, CPUX86St= ate *env, X86DecodedInsn *dec =20 static void gen_PDEP(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) { - MemOp ot =3D decode->op[1].ot; - if (ot < MO_64) { - tcg_gen_ext32u_tl(s->T0, s->T0); - } gen_helper_pdep(s->T0, s->T0, s->T1); } =20 static void gen_PEXT(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) { - MemOp ot =3D decode->op[1].ot; - if (ot < MO_64) { - tcg_gen_ext32u_tl(s->T0, s->T0); - } gen_helper_pext(s->T0, s->T0, s->T1); } =20 @@ -1796,9 +1806,6 @@ static void gen_SARX(DisasContext *s, CPUX86State *en= v, X86DecodedInsn *decode) =20 mask =3D ot =3D=3D MO_64 ? 63 : 31; tcg_gen_andi_tl(s->T1, s->T1, mask); - if (ot !=3D MO_64) { - tcg_gen_ext32s_tl(s->T0, s->T0); - } tcg_gen_sar_tl(s->T0, s->T0, s->T1); } =20 @@ -1873,9 +1880,6 @@ static void gen_SHRX(DisasContext *s, CPUX86State *en= v, X86DecodedInsn *decode) =20 mask =3D ot =3D=3D MO_64 ? 63 : 31; tcg_gen_andi_tl(s->T1, s->T1, mask); - if (ot !=3D MO_64) { - tcg_gen_ext32u_tl(s->T0, s->T0); - } tcg_gen_shr_tl(s->T0, s->T0, s->T1); } =20 --=20 2.43.0