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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1703269017855100011 Content-Type: text/plain; charset="utf-8" X86_SPECIAL_ZExtOp0 and X86_SPECIAL_ZExtOp2 are poorly named; they are a ha= ck that is needed by scalar insertion and extraction instructions, and not rea= lly related to zero extension: for PEXTR the zero extension is done by the gene= ration functions, for PINSR the high bits are not used at all and in fact are *not* filled with zeroes when loaded into s->T1. Rename the values to match the effect described in the manual, and explain better in the comments. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/decode-new.c.inc | 16 ++++++++-------- target/i386/tcg/decode-new.h | 17 +++++++++++++---- 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index 5eb2e9d0224..00fdb243857 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -153,8 +153,8 @@ #define xchg .special =3D X86_SPECIAL_Locked, #define lock .special =3D X86_SPECIAL_HasLock, #define mmx .special =3D X86_SPECIAL_MMX, -#define zext0 .special =3D X86_SPECIAL_ZExtOp0, -#define zext2 .special =3D X86_SPECIAL_ZExtOp2, +#define op0_Rd .special =3D X86_SPECIAL_Op0_Rd, +#define op2_Ry .special =3D X86_SPECIAL_Op2_Ry, #define avx_movx .special =3D X86_SPECIAL_AVXExtMov, =20 #define vex1 .vex_class =3D 1, @@ -632,13 +632,13 @@ static const X86OpEntry opcodes_0F3A[256] =3D { [0x05] =3D X86_OP_ENTRY3(VPERMILPD_i, V,x, W,x, I,b, vex6 chk(W0) c= puid(AVX) p_66), [0x06] =3D X86_OP_ENTRY4(VPERM2x128, V,qq, H,qq, W,qq, vex6 chk(W0) c= puid(AVX) p_66), =20 - [0x14] =3D X86_OP_ENTRY3(PEXTRB, E,b, V,dq, I,b, vex5 cpuid(SSE4= 1) zext0 p_66), - [0x15] =3D X86_OP_ENTRY3(PEXTRW, E,w, V,dq, I,b, vex5 cpuid(SSE4= 1) zext0 p_66), + [0x14] =3D X86_OP_ENTRY3(PEXTRB, E,b, V,dq, I,b, vex5 cpuid(SSE4= 1) op0_Rd p_66), + [0x15] =3D X86_OP_ENTRY3(PEXTRW, E,w, V,dq, I,b, vex5 cpuid(SSE4= 1) op0_Rd p_66), [0x16] =3D X86_OP_ENTRY3(PEXTR, E,y, V,dq, I,b, vex5 cpuid(SSE4= 1) p_66), [0x17] =3D X86_OP_ENTRY3(VEXTRACTPS, E,d, V,dq, I,b, vex5 cpuid(SSE4= 1) p_66), [0x1d] =3D X86_OP_ENTRY3(VCVTPS2PH, W,xh, V,x, I,b, vex11 chk(W0) c= puid(F16C) p_66), =20 - [0x20] =3D X86_OP_ENTRY4(PINSRB, V,dq, H,dq, E,b, vex5 cpuid(SSE4= 1) zext2 p_66), + [0x20] =3D X86_OP_ENTRY4(PINSRB, V,dq, H,dq, E,b, vex5 cpuid(SSE4= 1) op2_Ry p_66), [0x21] =3D X86_OP_GROUP0(VINSERTPS), [0x22] =3D X86_OP_ENTRY4(PINSR, V,dq, H,dq, E,y, vex5 cpuid(SSE4= 1) p_66), =20 @@ -1883,17 +1883,17 @@ static void disas_insn_new(DisasContext *s, CPUStat= e *cpu, int b) case X86_SPECIAL_HasLock: break; =20 - case X86_SPECIAL_ZExtOp0: + case X86_SPECIAL_Op0_Rd: assert(decode.op[0].unit =3D=3D X86_OP_INT); if (!decode.op[0].has_ea) { decode.op[0].ot =3D MO_32; } break; =20 - case X86_SPECIAL_ZExtOp2: + case X86_SPECIAL_Op2_Ry: assert(decode.op[2].unit =3D=3D X86_OP_INT); if (!decode.op[2].has_ea) { - decode.op[2].ot =3D MO_32; + decode.op[2].ot =3D s->dflag =3D=3D MO_16 ? MO_32 : s->dflag; } break; =20 diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h index 611bfddd957..b253f7457ae 100644 --- a/target/i386/tcg/decode-new.h +++ b/target/i386/tcg/decode-new.h @@ -165,11 +165,20 @@ typedef enum X86InsnSpecial { X86_SPECIAL_Locked, =20 /* - * Register operand 0/2 is zero extended to 32 bits. Rd/Mb or Rd/Mw - * in the manual. + * Rd/Mb or Rd/Mw in the manual: register operand 0 is treated as 32 b= its + * (and writeback zero-extends it to 64 bits if applicable). PREFIX_D= ATA + * does not trigger 16-bit writeback and, as a side effect, high-byte + * registers are never used. */ - X86_SPECIAL_ZExtOp0, - X86_SPECIAL_ZExtOp2, + X86_SPECIAL_Op0_Rd, + + /* + * Ry/Mb in the manual (PINSRB). However, the high bits are never use= d by + * the instruction in either the register or memory cases; the *real* = effect + * of this modifier is that high-byte registers are never used, even w= ithout + * a REX prefix. Therefore, PINSRW does not need it despite having Ry= /Mw. + */ + X86_SPECIAL_Op2_Ry, =20 /* * Register operand 2 is extended to full width, while a memory operand --=20 2.43.0