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Fri, 22 Dec 2023 10:00:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IFnPlrzjC4T9n9wHkzQPrqjb6Ma1wDQvcDH9VNQ+2R7Te3W+yTxgANKJtn3FFKTk00M7Bc6RQ== X-Received: by 2002:a05:600c:3513:b0:40c:36ff:7507 with SMTP id h19-20020a05600c351300b0040c36ff7507mr956748wmq.70.1703268005417; Fri, 22 Dec 2023 10:00:05 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, mcb30@ipxe.org, qemu-stable@nongnu.org Subject: [PATCH 4/5] target/i386: remove unnecessary/wrong application of the A20 mask Date: Fri, 22 Dec 2023 18:59:50 +0100 Message-ID: <20231222175951.172669-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222175951.172669-1-pbonzini@redhat.com> References: <20231222175951.172669-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1703268033625100011 Content-Type: text/plain; charset="utf-8" If ptw_translate() does a MMU_PHYS_IDX access, the A20 mask is already applied in get_physical_address(), which is called via probe_access_full() and x86_cpu_tlb_fill(). If ptw_translate() on the other hand does a MMU_NESTED_IDX access, the A20 mask must not be applied to the address that is looked up in the nested page tables; it must be applied only *while* looking up NPT entries. Therefore, we can remove A20 masking from the computation of the page table entry's address, and let get_physical_address() or mmu_translate() apply it when they know they are returning a host-physical address. Cc: qemu-stable@nongnu.org Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 2= 022-10-18) Signed-off-by: Paolo Bonzini --- target/i386/tcg/sysemu/excp_helper.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index eee1af52710..ede8ba6b80e 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -164,8 +164,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 5 */ - pte_addr =3D ((in->cr3 & ~0xfff) + - (((addr >> 48) & 0x1ff) << 3)) & a20_mask; + pte_addr =3D (in->cr3 & ~0xfff) + (((addr >> 48) & 0x1ff) = << 3); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -189,8 +188,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 4 */ - pte_addr =3D ((pte & PG_ADDRESS_MASK) + - (((addr >> 39) & 0x1ff) << 3)) & a20_mask; + pte_addr =3D (pte & PG_ADDRESS_MASK) + (((addr >> 39) & 0x1ff)= << 3); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -210,8 +208,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 3 */ - pte_addr =3D ((pte & PG_ADDRESS_MASK) + - (((addr >> 30) & 0x1ff) << 3)) & a20_mask; + pte_addr =3D (pte & PG_ADDRESS_MASK) + (((addr >> 30) & 0x1ff)= << 3); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -238,7 +235,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 3 */ - pte_addr =3D ((in->cr3 & 0xffffffe0ULL) + ((addr >> 27) & 0x18= )) & a20_mask; + pte_addr =3D (in->cr3 & 0xffffffe0ULL) + ((addr >> 27) & 0x18); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -260,8 +257,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 2 */ - pte_addr =3D ((pte & PG_ADDRESS_MASK) + - (((addr >> 21) & 0x1ff) << 3)) & a20_mask; + pte_addr =3D (pte & PG_ADDRESS_MASK) + (((addr >> 21) & 0x1ff) << = 3); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -287,8 +283,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 1 */ - pte_addr =3D ((pte & PG_ADDRESS_MASK) + - (((addr >> 12) & 0x1ff) << 3)) & a20_mask; + pte_addr =3D (pte & PG_ADDRESS_MASK) + (((addr >> 12) & 0x1ff) << = 3); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -306,7 +301,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 2 */ - pte_addr =3D ((in->cr3 & 0xfffff000ULL) + ((addr >> 20) & 0xffc)) = & a20_mask; + pte_addr =3D (in->cr3 & 0xfffff000ULL) + ((addr >> 20) & 0xffc); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -335,7 +330,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 1 */ - pte_addr =3D ((pte & ~0xfffu) + ((addr >> 10) & 0xffc)) & a20_mask; + pte_addr =3D (pte & ~0xfffu) + ((addr >> 10) & 0xffc); if (!ptw_translate(&pte_trans, pte_addr)) { return false; } --=20 2.43.0