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Fri, 22 Dec 2023 09:59:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IEa+WJTwPc1wookDV/f51BPJO8buAEkuXjpn8OKNSme6mKxszogysJGN/Fi1zkh+DHrRnUYoA== X-Received: by 2002:a05:600c:4595:b0:40d:1778:cdae with SMTP id r21-20020a05600c459500b0040d1778cdaemr1001770wmo.25.1703267997751; Fri, 22 Dec 2023 09:59:57 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, mcb30@ipxe.org, qemu-stable@nongnu.org Subject: [PATCH 1/5] target/i386: mask high bits of CR3 in 32-bit mode Date: Fri, 22 Dec 2023 18:59:47 +0100 Message-ID: <20231222175951.172669-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222175951.172669-1-pbonzini@redhat.com> References: <20231222175951.172669-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1703268035529100019 Content-Type: text/plain; charset="utf-8" CR3 bits 63:32 are ignored in 32-bit mode (either legacy 2-level paging or PAE paging). Do this in mmu_translate() to remove the last where get_physical_address() meaningfully drops the high bits of the address. Cc: qemu-stable@nongnu.org Suggested-by: Richard Henderson Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 2= 022-10-18) Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/sysemu/excp_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 5b86f439add..11126c860d4 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -238,7 +238,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 3 */ - pte_addr =3D ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20= _mask; + pte_addr =3D ((in->cr3 & 0xffffffe0ULL) + ((addr >> 27) & 0x18= )) & a20_mask; if (!ptw_translate(&pte_trans, pte_addr)) { return false; } @@ -306,7 +306,7 @@ static bool mmu_translate(CPUX86State *env, const Trans= lateParams *in, /* * Page table level 2 */ - pte_addr =3D ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_m= ask; + pte_addr =3D ((in->cr3 & 0xfffff000ULL) + ((addr >> 20) & 0xffc)) = & a20_mask; if (!ptw_translate(&pte_trans, pte_addr)) { return false; } --=20 2.43.0