From nobody Wed Nov 27 00:27:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1703247941; cv=none; d=zohomail.com; s=zohoarc; b=lnWx3zbn+PxPzIJbz0JJh0NoFFMLByQ+6pn6AzeLmsHeNDcZ5nUVGAHfrAXxTKCDM4hfk9H44O10uuiX90nb31BY5Pm8/xWH0xOy0c/oXAoyYHkM4wpKuUw4CLQt0kI/XLzjykQVwkLYh2wynXtlO7QwAcspk81F2YCdr/ygDSE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703247941; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ohkcTHo+nO+qUyiKr9PwLX4xkcWJcEp6mLlOiRy/wj8=; b=XD/tDZEYdIqfJcqOwWxJmaCo81OKEiCnNxsV8HucR6qeoc95pGTynnpZpJVBZK3l4Ko1vC8+01dCeqYMo7/1zpenUAIZBPvouHIvfRpGsGScj2RK9wq8KJh0j0EHTDW1/R43/Eeejpv4EeEcbDWPDgprRZxLDRTB6Cpw3ATgkM0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703247941872892.7406815258975; Fri, 22 Dec 2023 04:25:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rGeYh-0001mo-IY; Fri, 22 Dec 2023 07:23:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rGeYg-0001iZ-6H for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:23:18 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rGeYU-0006Av-Km for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:23:16 -0500 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6d93d15db24so1687443b3a.0 for ; Fri, 22 Dec 2023 04:23:06 -0800 (PST) Received: from grind.dc1.ventanamicro.com (201-69-66-51.dial-up.telesp.net.br. [201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:23:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247785; x=1703852585; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ohkcTHo+nO+qUyiKr9PwLX4xkcWJcEp6mLlOiRy/wj8=; b=bBTW/DFnh/Ck9FdlveukDF4NRCIMMeNTMghXHA4DmWvWirfD39wCH931f0cy+62kak WifeOX93griBol4KoVhww4kx5h840lBbsus9grE1CSt9+7yhaQKe8zx0YUsCnnetzVmq c0wq+/7hyiGca8fyBh3qaw+4ytqDBjLOdF0KNK7Mgfcqu2UVWZJuKAZRZS1Cy6mGBxHM u1ggAioEpbUYNzFGWPqaXM5o9Rrhpnf7Y+p20annvPUY7CRZfYylWdAPHQX6a8rVQATJ qKunxG+EhVtAWim45Ndyf9L7PwSLMmjBLMrkMpXzQQEGpZ8CibbjLxLQYouI66ll9tz+ NrEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247785; x=1703852585; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ohkcTHo+nO+qUyiKr9PwLX4xkcWJcEp6mLlOiRy/wj8=; b=J5DC/rTns1IPALPZpYQrnl4a8DCYoGT2Wn/q9NG4PJdayXfQUk8t1LrGIr0jtVY6Sp k2TnL4o5SAN2LK20+pXGLgM4iACQEfX+8yFNjb9+PFjHDMP+o20x/HfPNijyGmWUHs7z PnbeP/a5ShSXLAh/vfEGOyESP6vB4/SMSTGclzsZjmEBuy4YA0+JZziWfXBfor5md3AS mcTT789KI6p60gyf84hCt08znfKp4AETvBIABQHLuCRtsweNjjYx5cn4SHegcU259o9b st5unM1Qn/ez3X+4xk15/XwH0biM8OH/dOCck0Djf2TLHurZnDHcccplhy7oa9uryZNM OepQ== X-Gm-Message-State: AOJu0YyJ8Tk+lXQs6zYHx8E1dLdBFkN2ecrAdv0vfHM3tvnLlAm3jClP dDjt/tNOGZy9RRIYNqoKgBLeG0t+qbzV8pweDgjBDjI15zF4WQ== X-Google-Smtp-Source: AGHT+IFhEaB7dA+SXEVIqb0pLI/6H6vpDW2g0cMBqmA1rPdbcGO4ZlNo/sbXKzI/nvDaDag6WAIE4A== X-Received: by 2002:aa7:8611:0:b0:6d9:83a8:658a with SMTP id p17-20020aa78611000000b006d983a8658amr1191057pfn.43.1703247784921; Fri, 22 Dec 2023 04:23:04 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 08/16] target/riscv: move 'vlen' to riscv_cpu_properties[] Date: Fri, 22 Dec 2023 09:22:27 -0300 Message-ID: <20231222122235.545235-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247942431100001 Content-Type: text/plain; charset="utf-8" Turning 'vlen' into a class property will allow its default value to be overwritten by cpu_init() later on, solving the issue we have now where CPU specific settings are getting overwritten by the default. For 'vlen', 'elen' and the blocksize options we need a way of tracking if the user set a value for them. This is benign for TCG since the cost of always validating these values are small, but for KVM we need syscalls to read the host values to make the validations. Knowing whether the user didn't touch the values makes a difference. We'll track user setting for these properties using a hash, like we do in the TCG driver. Common validation bits are moved from riscv_cpu_validate_v() to prop_vlen_set() to be shared with KVM. And, as done with every option we migrated to riscv_cpu_properties[], vendor CPUs can't have their 'vlen' value changed. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 63 +++++++++++++++++++++++++++++++++++++- target/riscv/tcg/tcg-cpu.c | 5 --- 2 files changed, 62 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d6625399a7..c2ff50bcab 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -29,6 +29,7 @@ #include "qapi/visitor.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" +#include "hw/core/qdev-prop-internal.h" #include "migration/vmstate.h" #include "fpu/softfloat-helpers.h" #include "sysemu/kvm.h" @@ -53,6 +54,15 @@ const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF,= RVD, RVV, #define BYTE(x) (x) #endif =20 +/* Hash that stores general user set numeric options */ +static GHashTable *general_user_opts; + +static void cpu_option_add_user_setting(const char *optname, uint32_t valu= e) +{ + g_hash_table_insert(general_user_opts, (gpointer)optname, + GUINT_TO_POINTER(value)); +} + #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 @@ -1244,6 +1254,8 @@ static void riscv_cpu_init(Object *obj) IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); #endif /* CONFIG_USER_ONLY */ =20 + general_user_opts =3D g_hash_table_new(g_str_hash, g_str_equal); + /* * The timer and performance counters extensions were supported * in QEMU before they were added as discrete extensions in the @@ -1664,8 +1676,54 @@ static const PropertyInfo prop_vext_spec =3D { .set =3D prop_vext_spec_set, }; =20 +static void prop_vlen_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + if (!is_power_of_2(value)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + + /* Always allow setting a default value */ + if (cpu->cfg.vlen =3D=3D 0) { + cpu->cfg.vlen =3D value; + return; + } + + if (value !=3D cpu->cfg.vlen && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.vlen); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.vlen =3D value; +} + +static void prop_vlen_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.vlen; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_vlen =3D { + .name =3D "vlen", + .get =3D prop_vlen_get, + .set =3D prop_vlen_set, + .set_default_value =3D qdev_propinfo_set_default_value_uint, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), @@ -1687,6 +1745,9 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "priv_spec", .info =3D &prop_priv_spec}, {.name =3D "vext_spec", .info =3D &prop_vext_spec}, =20 + {.name =3D "vlen", .info =3D &prop_vlen, + .set_default =3D true, .defval.u =3D 128}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 6501c29d8e..8ec858e096 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -178,11 +178,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu,= Error **errp) static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { - if (!is_power_of_2(cfg->vlen)) { - error_setg(errp, "Vector extension VLEN must be power of 2"); - return; - } - if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { error_setg(errp, "Vector extension implementation only supports VLEN " --=20 2.43.0