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[201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:22:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247773; x=1703852573; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o5PCLfKnIm15G3iihfvhUkVoKe5lIweTL/Udt+M00pE=; b=CdMi2gCP821/AQ5tQickF1CJyDjXdG+taGzRZ+vA1AM0rnDcjBZTMY9NzWzJakEMmu z1EcEIrWdB3LXUbysBenAXkiKRnqNXBrqt6JGeFKxmgRDgKtuBc6QNrFejpFE9M/Pt88 EkQFzD4dDXcSJoiws1HikMU3+nOFqFaq1yctC+pD8yYd3h0tyi+4EkAM1WgXfJgeCGet B1kIPcLC6Dtcoqb1Aa6TpCvY7TooMMb5oTydp3ygazxXaqBPVxQMLk5eP+wy7nMFTTNo 9tv1XXfVIO396KBEbZQoJ74oSeNtWWICzBGaN99R355s8hK7szaWHGBbfUlRftzJIGNU 80sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247773; x=1703852573; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o5PCLfKnIm15G3iihfvhUkVoKe5lIweTL/Udt+M00pE=; b=BTtkiNCeS/ymK2qh2i+pFZUE1PXo2SvGyupDg0FtyPlNk0QWNx1yjj06INgu2Oxe8A w9QB5y0TTOU3ePfImW0t5IbD6HURIpuddDrvF8YeehcbbAdkkcRTHhyivAt6czkh9o/w YQLXK5qhNS+OHAXwnR//3s8LFm/wd0KZ6vHSZSEmxBGpIxAtKxUJwHes4Lgxucb8oAOJ feabXFJtCWQ9mmADATl/kXYct3/envGSas044lXQLnAJ2tOhaVgv/38nVjaS+yd77Z6P YIrh4sFQ59BXD5Gqwd2n2OWYdG2iUsw+j0lG3RwlPI286QEQxT9JrN5fcqZWJ4coVsPS /qOg== X-Gm-Message-State: AOJu0YxKKF4bZVNaVcauumSg/dDdUhXnTKLpHNYyNw3AezAJwr7BgabF 4X6l+v84099J60NvMFTPwCO6PTT0wTr7F17YazsbKY3IZt+muw== X-Google-Smtp-Source: AGHT+IHVH0H/8qqXx6ZSWiuMdWtRpmM7EJx1MlDvGjt4FXbRkT9CRglAwvefH9YVlulTNbnPCMYQgw== X-Received: by 2002:a05:6a20:7491:b0:18f:e56b:9848 with SMTP id p17-20020a056a20749100b0018fe56b9848mr1442446pzd.13.1703247772827; Fri, 22 Dec 2023 04:22:52 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 04/16] target/riscv: move 'mmu' to riscv_cpu_properties[] Date: Fri, 22 Dec 2023 09:22:23 -0300 Message-ID: <20231222122235.545235-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247914425100002 Content-Type: text/plain; charset="utf-8" Commit 7f0bdfb5bfc ("target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()") already did some of the work by making some cpu_init() functions to explictly enable their own 'mmu' default. The generic CPUs didn't get update by that commit, so they are still relying on the defaults set by the 'mmu' option. But having 'mmu' and 'pmp' being default=3Dtrue will force CPUs that doesn't implement these options to set them to 'false' in their cpu_init(), which isn't ideal. We'll move 'mmu' to riscv_cpu_properties[] without any defaults, i.e. the default will be 'false'. Compensate it by manually setting 'mmu =3D true' to the generic CPUs that requires it. Implement a setter for it to forbid the 'mmu' setting to be changed for vendor CPUs. This will allow the option to exist for all CPUs and, at the same time, protect vendor CPUs from undesired changes: $ ./build/qemu-system-riscv64 -M virt -cpu sifive-e51,mmu=3Dtrue qemu-system-riscv64: can't apply global sifive-e51-riscv-cpu.mmu=3Dtrue: CPU 'sifive-e51' does not allow changing the value of 'mmu' Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 67 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 63 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fb3d23b047..080713b9b5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -410,6 +410,8 @@ static void riscv_max_cpu_init(Object *obj) CPURISCVState *env =3D &cpu->env; RISCVMXL mlx =3D MXL_RV64; =20 + cpu->cfg.mmu =3D true; + #ifdef TARGET_RISCV32 mlx =3D MXL_RV32; #endif @@ -424,7 +426,11 @@ static void riscv_max_cpu_init(Object *obj) #if defined(TARGET_RISCV64) static void rv64_base_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + + cpu->cfg.mmu =3D true; + /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV64, 0); /* Set latest version of privileged specification */ @@ -542,13 +548,18 @@ static void rv64_veyron_v1_cpu_init(Object *obj) =20 static void rv128_base_cpu_init(Object *obj) { + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + if (qemu_tcg_mttcg_enabled()) { /* Missing 128-bit aligned atomics */ error_report("128-bit RISC-V currently does not work with Multi " "Threaded TCG. Please use: -accel tcg,thread=3Dsingle= "); exit(EXIT_FAILURE); } - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + + cpu->cfg.mmu =3D true; + /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV128, 0); /* Set latest version of privileged specification */ @@ -560,7 +571,11 @@ static void rv128_base_cpu_init(Object *obj) #else static void rv32_base_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + + cpu->cfg.mmu =3D true; + /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV32, 0); /* Set latest version of privileged specification */ @@ -1431,6 +1446,19 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_ex= ts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static bool riscv_cpu_is_vendor(Object *obj) +{ + return !riscv_cpu_is_generic(obj); +} + +static void cpu_set_prop_err(RISCVCPU *cpu, const char *propname, + Error **errp) +{ + g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); + error_setg(errp, "CPU '%s' does not allow changing the value of '%s'", + cpuname, propname); +} + static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -1468,8 +1496,37 @@ static const PropertyInfo prop_pmu_num =3D { .set =3D prop_pmu_num_set, }; =20 +static void prop_mmu_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value; + + visit_type_bool(v, name, &value, errp); + + if (cpu->cfg.mmu !=3D value && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, "mmu", errp); + return; + } + + cpu->cfg.mmu =3D value; +} + +static void prop_mmu_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.mmu; + + visit_type_bool(v, name, &value, errp); +} + +static const PropertyInfo prop_mmu =3D { + .name =3D "mmu", + .get =3D prop_mmu_get, + .set =3D prop_mmu_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), =20 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), @@ -1491,6 +1548,8 @@ static Property riscv_cpu_properties[] =3D { MAKE_64BIT_MASK(3, 16)), {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ =20 + {.name =3D "mmu", .info =3D &prop_mmu}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif --=20 2.43.0