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[201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:22:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247770; x=1703852570; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Oagcc2Zv4k0si9dN/lqEsLqexrn9/qqPDiS/g5OohqM=; b=Pj9AhRxY43NMKAwMnp0mppNeOvbNuc+vvntrrVk7Khxs1udLlFYOmymoX0wGqEj80T bPPc6n1NLvF4DBSit8r3pNoPjMvZAJVK+9g+GIT0h1GmHpJq/KaHACAmDbAI+u4KqQM1 Yo25FOQlUWeZyQFxxT+Wp7sc1q+JXs28KAC613f2RGc0tOZv7XZ3le5UKdnTU1GNdK5P OsE0KzWJo1+vOoKZ4pL/rSEq17Hdb5KTtKxo3yPFRERQxJ1kJQFV4Hl4QIPTSJUAgwCN 9KIkmyHAayEUBN/FcRaTDsvEPkpC+ScMc0S2HDXxny3On0T/ACL2b9JTxEvfv/rwwxBd HmaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247770; x=1703852570; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Oagcc2Zv4k0si9dN/lqEsLqexrn9/qqPDiS/g5OohqM=; b=M72vU0UUrvgkBsAFUv8DbPTOJf4eOyV7PDjXWZ7InRYdrA/Cl+q/9TlBzm9g6dmyPR m65RZxGuh2vBHr3+OZPMKh8bHQvwTPVG25AN8QKehuRG2kT3mCakkQj98z8sTaFTEY9P 0jeA7QxkidwxpEunPkSd0Y6ndSm8oqOG5im5uIV+h9THgJFOyQ/Dx7LTo96nQKSEsm0y RezP1medUBgIXb4tHaAGNZiS2FcET7Uupldpg28e4JEZRJY9LKDCm10qHdVu+AsQyt39 HcSc6II0nog4YDVrk0abI/isFXog/V54BoEFyJSFCJrLlaW/vxnijF75Ie0HVJg1tsXp /c1w== X-Gm-Message-State: AOJu0Yz3B5x4N0TYsxwZrFpJ6lPBL2ZUwE03BxaGpf+W0e9QptWj2IDd 8ITwjOd3vc6fOXSDNDh6Y4w79pYBXnencj6u/s6d9BEwAw0U0Q== X-Google-Smtp-Source: AGHT+IGGxm2zC4frts7y71/3cieGAzfB5JBJqX9EODDYa40UrW3bqCKYvm+O8BYa+KmDGdlewxyhJQ== X-Received: by 2002:a05:6602:50:b0:7b7:abba:a0d0 with SMTP id z16-20020a056602005000b007b7abbaa0d0mr1204134ioz.43.1703247769819; Fri, 22 Dec 2023 04:22:49 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 03/16] target/riscv: make riscv_cpu_is_generic() public Date: Fri, 22 Dec 2023 09:22:22 -0300 Message-ID: <20231222122235.545235-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d31; envelope-from=dbarboza@ventanamicro.com; helo=mail-io1-xd31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247922426100001 Content-Type: text/plain; charset="utf-8" We'll use this function in target/riscv/cpu.c to implement setters that won't allow vendor CPU options to be changed. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 5 +++++ target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 5 ----- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 34f7616258..fb3d23b047 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -183,6 +183,11 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ex= t_offset, bool en) *ext_enabled =3D en; } =20 +bool riscv_cpu_is_generic(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; +} + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361be6..cfe965e512 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -757,6 +757,7 @@ enum riscv_pmu_event_idx { void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); +bool riscv_cpu_is_generic(Object *cpu_obj); =20 typedef struct RISCVCPUMultiExtConfig { const char *name; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8a35683a34..a09300e908 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -658,11 +658,6 @@ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) =3D=3D NU= LL; } =20 -static bool riscv_cpu_is_generic(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; -} - /* * We'll get here via the following path: * --=20 2.43.0