From nobody Wed Nov 27 00:38:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1703247898; cv=none; d=zohomail.com; s=zohoarc; b=LyhBKzF6z4BtF9NS9ShD7EHp1D+Ppd1AjQW74IIabSmXm3HAjFbCI8MZ5353bEFdXKRqXUeE6y62KapfGf6+YLFWqBHcFfFBfpzcCIrVPddeufNR3u7zrv1qs80Tx5aLdXh0vYjEWf/TqMR5TSf1hIkwV5PLLIj71PAodBVFbTo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703247898; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YBdFO1/O1xsYMUcgtmKgi1/AljKQg+BgIlpJLJG998U=; b=XrIpawptkletT5VzoZx6jTau9EQbUnFMB3uXqd0oeZNM7EzwNG5vwpJYrAkZuL9gyukVWDKR58W1SYdgi2EM1v4i0kZSXKo7xwljoGR5QlVjWX6ZveS4Y0ThEE0YAMUMvQr2pwRJ3/PwnhL1tHcRLbLGSP+6HIGWT+GJmgRIZCQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703247898572596.2858909288689; Fri, 22 Dec 2023 04:24:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rGeYg-0001ks-Gl; Fri, 22 Dec 2023 07:23:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rGeYe-0001i7-KQ for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:23:16 -0500 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rGeYa-0006CO-Mw for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:23:16 -0500 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6d939e2f594so1673226b3a.3 for ; Fri, 22 Dec 2023 04:23:12 -0800 (PST) Received: from grind.dc1.ventanamicro.com (201-69-66-51.dial-up.telesp.net.br. [201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:23:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247791; x=1703852591; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YBdFO1/O1xsYMUcgtmKgi1/AljKQg+BgIlpJLJG998U=; b=G4YnKrdI6qR/YIz8PQfgC6zhBr1kDuKKYCaY2qQSrQbmMwDj/aMAKb+tuPthtyEcM1 OjZ5ghn2y6jxf9IxR9+Al3tvJNGx/+MGlCSzderpG3ZfvJspi+9qiwlL0zL7tS/mp89y pc7TPnJeb96/1Q22autalWM2BebEWFhGlqctK4tupws4gvw1nbyph27HrX0FeYEr0fWS jqibTxzsfrc5M2eWGwGmL7fXPEP8GVeGI82en7oi7KCF9Oeb4SqJlUAkxG7qnRcP8JYF guHoF5whP7uWUdHDXnsYpwKV9yp6Mn6pw2S2mmuBH+4M5OxZbBvyLYRmfqD8ASBrLqtX 1nGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247791; x=1703852591; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YBdFO1/O1xsYMUcgtmKgi1/AljKQg+BgIlpJLJG998U=; b=fh3RDRwoQWoAWzR1StySGOziC9Uk+LJIqrz1hMgD66Ol1pMdHtCpLdakl+V7tKAhuS 4ow3hrxZmGfijgr+rE/lZG3lSNoqgxfFCy5+uDl/tGB8p0YnbPRF7DvuUmgwGbp1SVUT b+8e3O5MAfbz2IHvx1HptvnGTNwCap9PgusRByaPmkEQ73Cy2h3oF+tXuo7/2NBEA0My MuStW/fL1DwYtWzRZzExfkkiTbQ0jGIOU0BeON3lZxWLeRufrtLV/gZnz1WwIMz2x5vY yiqsXx9yLlZUnvQ/z5xyEbpzWfjM2ZP5K9WdR22flGwkYyrN0PvcPiy2X0z2AZt8S/44 9G8g== X-Gm-Message-State: AOJu0YyhGULVabie+QVYVjf28gWeU1ra8RZUYnV7KKslIX9xgxGmoU29 IVvAvoCLuDbfCWo50QUqfsIaGz1i6YIfNUUM9uVtUZnfyRhLQg== X-Google-Smtp-Source: AGHT+IFfh54e4U+6AzhBnWFB4AlLrA1/nhXCG+B4zu8MtwRla4vWW9c+q4hZj0wbk9NnfF9t3nYffA== X-Received: by 2002:a05:6a20:7da4:b0:194:dd52:bdc7 with SMTP id v36-20020a056a207da400b00194dd52bdc7mr1482747pzj.56.1703247790897; Fri, 22 Dec 2023 04:23:10 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 10/16] target/riscv: create finalize_features() for KVM Date: Fri, 22 Dec 2023 09:22:29 -0300 Message-ID: <20231222122235.545235-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247900327100011 Content-Type: text/plain; charset="utf-8" To turn cbom_blocksize and cboz_blocksize into class properties we need KVM specific changes. KVM is creating its own version of these options with a customized setter() that prevents users from picking an invalid value during init() time. This comes at the cost of duplicating each option that KVM supports. This will keep happening for each new shared option KVM implements in the future. We can avoid that by using the same property TCG uses and adding specific KVM handling during finalize() time, like TCG already does with riscv_tcg_cpu_finalize_features(). To do that, the common CPU property offers a way of knowing if an option was user set or not, sparing us from doing unneeded syscalls. riscv_kvm_cpu_finalize_features() is then created using the same KVMScratch CPU we already use during init() time, since finalize() time is still too early to use the official KVM CPU for it. cbom_blocksize and cboz_blocksize are then handled during finalize() in the same way they're handled by their KVM specific setter. With this change we can proceed with the blocksize changes in the common code without breaking the KVM driver. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 16 +++++++--- target/riscv/cpu.h | 1 + target/riscv/kvm/kvm-cpu.c | 59 ++++++++++++++++++++++++++++++++++++ target/riscv/kvm/kvm_riscv.h | 1 + 4 files changed, 72 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8be619b6f1..f49d31d753 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -63,6 +63,11 @@ static void cpu_option_add_user_setting(const char *optn= ame, uint32_t value) GUINT_TO_POINTER(value)); } =20 +bool riscv_cpu_option_set(const char *optname) +{ + return g_hash_table_contains(general_user_opts, optname); +} + #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 @@ -1056,17 +1061,18 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Err= or **errp) { Error *local_err =3D NULL; =20 - /* - * KVM accel does not have a specialized finalize() - * callback because its extensions are validated - * in the get()/set() callbacks of each property. - */ if (tcg_enabled()) { riscv_tcg_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } + } else if (kvm_enabled()) { + riscv_kvm_cpu_finalize_features(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 53101b82c5..988471c7ba 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -495,6 +495,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); +bool riscv_cpu_option_set(const char *optname); =20 #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 62a1e51f0a..70fb075846 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1490,6 +1490,65 @@ static void kvm_cpu_instance_init(CPUState *cs) } } =20 +void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + KVMScratchCPU kvmcpu; + struct kvm_one_reg reg; + uint64_t val; + int ret; + + /* short-circuit without spinning the scratch CPU */ + if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz) { + return; + } + + if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { + error_setg(errp, "Unable to create scratch KVM cpu"); + return; + } + + if (cpu->cfg.ext_zicbom && + riscv_cpu_option_set(kvm_cbom_blocksize.name)) { + + reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + kvm_cbom_blocksize.kvm_reg_id); + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_setg(errp, "Unable to read cbom_blocksize, error %d", er= rno); + return; + } + + if (cpu->cfg.cbom_blocksize !=3D val) { + error_setg(errp, "Unable to set cbom_blocksize to a different " + "value than the host (%lu)", val); + return; + } + } + + if (cpu->cfg.ext_zicboz && + riscv_cpu_option_set(kvm_cboz_blocksize.name)) { + + reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + kvm_cboz_blocksize.kvm_reg_id); + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_setg(errp, "Unable to read cbom_blocksize, error %d", er= rno); + return; + } + + if (cpu->cfg.cboz_blocksize !=3D val) { + error_setg(errp, "Unable to set cboz_blocksize to a different " + "value than the host (%lu)", val); + return; + } + } + + kvm_riscv_destroy_scratch_vcpu(&kvmcpu); +} + static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h index 8329cfab82..4bd98fddc7 100644 --- a/target/riscv/kvm/kvm_riscv.h +++ b/target/riscv/kvm/kvm_riscv.h @@ -27,5 +27,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t= group_shift, uint64_t guest_num); void riscv_kvm_aplic_request(void *opaque, int irq, int level); int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state); +void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp); =20 #endif --=20 2.43.0