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[201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:22:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247763; x=1703852563; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bNKontpfLUZyadIzXzNBnB69eWAYBQx8Z06ZfrYR8/0=; b=bHR973U682ixIDlPQ+i/QFa6uoEZHk26LTME1cebpk9GHdutDjWSSPjXXx5XUyEemD KsSNGfYmvr803AsYrx++JYaCDwUMwMoe1bVV+Ptu14RxdyilZEbKoHN40VMuJoGLyy9z 8/FwArjJKjClG1up3P/cTB0FaEi6J5bOyh2KnvMbgB/ripnIYHmHf6tWifxmVuV7DlNP yiw5SP4Rvg6gL1mMrrlWT6WPSBcQ/7sfrG6wT0VZEE3noslEADJWEu5dK17RBmdxlxc3 f9lylD6qiqbzyksitBkA6lkWKCuedYxMK2I6y6sNzRwJbesGN6XmS3P7+OOsrPtugw3T pXHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247763; x=1703852563; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bNKontpfLUZyadIzXzNBnB69eWAYBQx8Z06ZfrYR8/0=; b=IumUwFrbwb6cPvsQ2GNAfT/jBM0oQjwHOgWphLJlSsKk2LMnRzSJbsrFSAOd54kSEJ k1QJVmyPmKnxkt0sh5yFD3hX1HPweEI5PFPlOd92vEieCV170WeNxx9lHJ6SQmyNY8Vi r/V3MmeyZqkiR+FSmQcZNyqB9sT6iFyZs4xK1py+jW7V8s4gVssP6yQdmy6HKToKdDQD hFW4hGAnulfYCJaleCJ8ju2doUor6Cbz/f7Mu6zHxVV4F0mr3XTKnAoWI7JgKo29h9Rs mZb+uHg2C4fkIUgvVWPNet0NW7AARzJomXC3GUzdhlb3rtwo4dVaNgySRzjS2mIZFNG3 sMjA== X-Gm-Message-State: AOJu0YyqB/MYrf8G3uj21Z3YNXY7wHETCxZHnmI66ITzVjJjycubBcQX l4lG10nnE5TJdDAa0n55nKfsAZTGToX/LicrnLGriev/w6m8Ww== X-Google-Smtp-Source: AGHT+IGVsM/Li3YD6MuFO/G8cE7Px9qU45nHLuk38M8cY1Zc+0fHGtcYFu6e3WJKguSMrsMhEDoWSA== X-Received: by 2002:a05:6a20:78a1:b0:194:b3af:8674 with SMTP id d33-20020a056a2078a100b00194b3af8674mr1122908pzg.10.1703247763704; Fri, 22 Dec 2023 04:22:43 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 01/16] target/riscv/cpu_cfg.h: remove user_spec and bext_spec Date: Fri, 22 Dec 2023 09:22:20 -0300 Message-ID: <20231222122235.545235-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247800104100003 Content-Type: text/plain; charset="utf-8" They aren't being used. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu_cfg.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index f4605fb190..c67a8731d3 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -136,8 +136,6 @@ struct RISCVCPUConfig { =20 uint32_t pmu_mask; char *priv_spec; - char *user_spec; - char *bext_spec; char *vext_spec; uint16_t vlen; uint16_t elen; --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1703247933; cv=none; d=zohomail.com; s=zohoarc; b=MRRWdjPhk618VazC9vDzN/OJPnCn0tsR0UMi4MYYzI2tky49Zo1ZQWcBn0gx3IcsqdoyDtqJF1csRVe5KvxpATVhp95FiacUTi7q7WmIWgn0AG105Sf3YDzZBzIvePNUUWO/tUrxxuzllRyUian6APyCw6uvaLbIaGkCDBTvGiA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703247933; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WHLPmiheEOnodk4jIREyWq0iPo/tsfjG5BHc9yunH9g=; b=F/qljIYRTaz4c/qXh0L8ALeMtuc2np/CR8hN86LtxK6EIlbllK+ZqJ3RFXF4UjoQLAzYvXGItKS4mCVFqnfBInp0eFAKFt1VzzXzxPl/jydNhV7UeT/P5FMSw2CrpXXv4M7Cl7r3H53czpY/iU76nSEwUHFPcgDa/wyZmtKXGVo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703247933131213.46201794763567; Fri, 22 Dec 2023 04:25:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rGeYG-0001We-35; Fri, 22 Dec 2023 07:22:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rGeYE-0001Vh-6q for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:22:50 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rGeYC-0005nB-EB for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:22:49 -0500 Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-5cd68a0de49so1308340a12.2 for ; Fri, 22 Dec 2023 04:22:48 -0800 (PST) Received: from grind.dc1.ventanamicro.com (201-69-66-51.dial-up.telesp.net.br. [201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:22:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247767; x=1703852567; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WHLPmiheEOnodk4jIREyWq0iPo/tsfjG5BHc9yunH9g=; b=Hx5PtxsxUduIwSvTHPZZC1+WKziOVjbg8YxLL8CeOzV6Ni8FG+GakKpPKvt6dvsGF7 snYSQo/IMz9k7M1iBep+Bw15VeyiC05935a6gSYF4rhTHM1gMVPrJMnEak7QHbGR7T1w wvUvCTpoCmMPclTxyHHxQjTYN0B1daK36JvvFeFZcoj7UF4b6zo4WLLpotdXMlveihUR U8/qmqM5XkJhymKn37gctFfMLA6AeG8sB5c09EiiygfEsRSibdZ4VMLyQo6d+TkZdAg0 UAubV89OnXnNcfOeSK5dJuGGed1aEPfNKofRsgIVeTwXfJlJWS07R0H16zRjm9S4ZP2E aAzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247767; x=1703852567; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WHLPmiheEOnodk4jIREyWq0iPo/tsfjG5BHc9yunH9g=; b=YlgON8tnrKInG+43F7PyW0i+5mIxqg2iOaasQbYlu1RzFUObDXyxvrN+h9RZDPXdOd KSFktxsFzgUJzjtJ7TkR7yhq0hnlSCA0b5rs4Cok3k/NbQXPsreNBsN0N4NfLaaIt4ay F+rFhFoMlzM/sx2LeHzBC5zyJpZpLhgOVMBBtlcxCjZXrKq16lIwxlBfLQAUpyh4JpkY /ZwfW7N4M6cJf1gUkjnqBBpEnm8jeJ/bIwbEz/u8dSUD5RpyRJ3J2SkVc7VQi9Aah51G W/YiVEqSD5kPz87Kr8W60EedVrpc7B8mBgAv8hO93dIPc20h3AnuSGg4jwIukeJGtPhA zGbg== X-Gm-Message-State: AOJu0Yx4exiWOdgfq3WlzNB+gDynytkLYnb1Lv4GeWbNkCzStx/DxuhX GGiotsa9+MlKEsH0NIwYIoMSATbGfFmhyl8kv3o/bKDUYLfx4g== X-Google-Smtp-Source: AGHT+IH/2maknFZ9G6JVhIXRR0d0X5WENMCJMhAuteI0XYsk+pGRXCGfkfXcLZ/8Y2XLnBrw1GETbA== X-Received: by 2002:a05:6a20:430e:b0:191:60f5:2a9 with SMTP id h14-20020a056a20430e00b0019160f502a9mr1363508pzk.80.1703247766821; Fri, 22 Dec 2023 04:22:46 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 02/16] target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[] Date: Fri, 22 Dec 2023 09:22:21 -0300 Message-ID: <20231222122235.545235-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247934468100001 Content-Type: text/plain; charset="utf-8" Every property in riscv_cpu_options[] will be migrated to riscv_cpu_properties[]. This will make their default values init earlier, allowing cpu_init() functions to overwrite them. We'll also implement common getters and setters that both accelerators will use, allowing them to share validations that TCG is doing. For pmu-mask and pmu-num it's just a matter of migrating the properties from one array to the other. While we're at it, add a 'static' modifier to 'prop_pmu_num' since we're not exporting it. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 70bf10aa7c..34f7616258 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1457,16 +1457,13 @@ static void prop_pmu_num_get(Object *obj, Visitor *= v, const char *name, visit_type_uint8(v, name, &pmu_num, errp); } =20 -const PropertyInfo prop_pmu_num =3D { +static const PropertyInfo prop_pmu_num =3D { .name =3D "pmu-num", .get =3D prop_pmu_num_get, .set =3D prop_pmu_num_set, }; =20 Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, MAKE_64BIT_MASK= (3, 16)), - {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), =20 @@ -1485,6 +1482,10 @@ Property riscv_cpu_options[] =3D { static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 + DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, + MAKE_64BIT_MASK(3, 16)), + {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1703247921; cv=none; d=zohomail.com; s=zohoarc; b=fn5WzD1wygH9Y/7OEAB3PgjH01RX9LNf3T+OL/YFd/TnAd5y1Ihn1TermjwdXSrZadhOoL6aQmaDxJ91kBuP/hIWSvsVQe0pU5HO6OC53EynWFYidnamSti8py2A+GbsaaXlxH2KPUuWR2x0CNEewlXyoO1d2KbFrwK9Ch8Ynkg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703247921; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Oagcc2Zv4k0si9dN/lqEsLqexrn9/qqPDiS/g5OohqM=; b=WFneoEKdBjiA0kNIw1yIAvW44/DAvNMxbFcb7KGPdvQ+4CfXrMmxfaZJ4iSqA9zu5NpFOe0TuFegxo/oA7YwOo9eyJokdzlkfqBDQAX7W3ZCLvG1ZqV1fMQs6OvgOHv09+ya82dD59zIGAW17Bk2DEFN+5nHkjlY+gah9ngCQPo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703247921963879.834613974832; Fri, 22 Dec 2023 04:25:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rGeYI-0001XS-BC; Fri, 22 Dec 2023 07:22:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rGeYH-0001X5-CE for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:22:53 -0500 Received: from mail-io1-xd31.google.com ([2607:f8b0:4864:20::d31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rGeYF-0005yc-Po for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:22:53 -0500 Received: by mail-io1-xd31.google.com with SMTP id ca18e2360f4ac-7b7f93eb935so76328639f.1 for ; Fri, 22 Dec 2023 04:22:51 -0800 (PST) Received: from grind.dc1.ventanamicro.com (201-69-66-51.dial-up.telesp.net.br. [201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:22:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247770; x=1703852570; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Oagcc2Zv4k0si9dN/lqEsLqexrn9/qqPDiS/g5OohqM=; b=Pj9AhRxY43NMKAwMnp0mppNeOvbNuc+vvntrrVk7Khxs1udLlFYOmymoX0wGqEj80T bPPc6n1NLvF4DBSit8r3pNoPjMvZAJVK+9g+GIT0h1GmHpJq/KaHACAmDbAI+u4KqQM1 Yo25FOQlUWeZyQFxxT+Wp7sc1q+JXs28KAC613f2RGc0tOZv7XZ3le5UKdnTU1GNdK5P OsE0KzWJo1+vOoKZ4pL/rSEq17Hdb5KTtKxo3yPFRERQxJ1kJQFV4Hl4QIPTSJUAgwCN 9KIkmyHAayEUBN/FcRaTDsvEPkpC+ScMc0S2HDXxny3On0T/ACL2b9JTxEvfv/rwwxBd HmaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247770; x=1703852570; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Oagcc2Zv4k0si9dN/lqEsLqexrn9/qqPDiS/g5OohqM=; b=M72vU0UUrvgkBsAFUv8DbPTOJf4eOyV7PDjXWZ7InRYdrA/Cl+q/9TlBzm9g6dmyPR m65RZxGuh2vBHr3+OZPMKh8bHQvwTPVG25AN8QKehuRG2kT3mCakkQj98z8sTaFTEY9P 0jeA7QxkidwxpEunPkSd0Y6ndSm8oqOG5im5uIV+h9THgJFOyQ/Dx7LTo96nQKSEsm0y RezP1medUBgIXb4tHaAGNZiS2FcET7Uupldpg28e4JEZRJY9LKDCm10qHdVu+AsQyt39 HcSc6II0nog4YDVrk0abI/isFXog/V54BoEFyJSFCJrLlaW/vxnijF75Ie0HVJg1tsXp /c1w== X-Gm-Message-State: AOJu0Yz3B5x4N0TYsxwZrFpJ6lPBL2ZUwE03BxaGpf+W0e9QptWj2IDd 8ITwjOd3vc6fOXSDNDh6Y4w79pYBXnencj6u/s6d9BEwAw0U0Q== X-Google-Smtp-Source: AGHT+IGGxm2zC4frts7y71/3cieGAzfB5JBJqX9EODDYa40UrW3bqCKYvm+O8BYa+KmDGdlewxyhJQ== X-Received: by 2002:a05:6602:50:b0:7b7:abba:a0d0 with SMTP id z16-20020a056602005000b007b7abbaa0d0mr1204134ioz.43.1703247769819; Fri, 22 Dec 2023 04:22:49 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 03/16] target/riscv: make riscv_cpu_is_generic() public Date: Fri, 22 Dec 2023 09:22:22 -0300 Message-ID: <20231222122235.545235-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d31; envelope-from=dbarboza@ventanamicro.com; helo=mail-io1-xd31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247922426100001 Content-Type: text/plain; charset="utf-8" We'll use this function in target/riscv/cpu.c to implement setters that won't allow vendor CPU options to be changed. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 5 +++++ target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 5 ----- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 34f7616258..fb3d23b047 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -183,6 +183,11 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ex= t_offset, bool en) *ext_enabled =3D en; } =20 +bool riscv_cpu_is_generic(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; +} + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361be6..cfe965e512 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -757,6 +757,7 @@ enum riscv_pmu_event_idx { void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); +bool riscv_cpu_is_generic(Object *cpu_obj); =20 typedef struct RISCVCPUMultiExtConfig { const char *name; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8a35683a34..a09300e908 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -658,11 +658,6 @@ bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) =3D=3D NU= LL; } =20 -static bool riscv_cpu_is_generic(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; -} - /* * We'll get here via the following path: * --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1703247912; cv=none; d=zohomail.com; s=zohoarc; b=YzV76UUEVQQ0yeNky7VV+BAODH7bZPQrnvbPNy35c69ov8rr3qyMFYNehckFM6cAUIY51Kzrjk//vjKs1+NS3XhxQZ5EWJkk2rNWMUTxpT7FgLqPAa+iAtJKOjN0Ve/F1LmTd7K36Jn01NeVfRsUL4556oz2d5rWGrbhaOjC9R4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703247912; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=o5PCLfKnIm15G3iihfvhUkVoKe5lIweTL/Udt+M00pE=; b=gavBDuqvGIli0RXQqnjxlJ/r5LozW8mhz4weTTBoBMlGyg8RHfZrZdDVmQX6rAiv0lwDXj59cTT8YobMz+gwjN4KcQcOU00ywNyg70Bw1VP3Mdvxq7YNjf5PufvIgjqLDG+eT6hNb91RuxJ/v1VngzaW/0Jg2Cp7UqrzBzvtI54= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703247912956102.64681724487696; Fri, 22 Dec 2023 04:25:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rGeYR-0001Zp-1a; Fri, 22 Dec 2023 07:23:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rGeYO-0001Yu-UG for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:23:00 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rGeYI-00064C-Ev for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:23:00 -0500 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-5c21e185df5so1376830a12.1 for ; Fri, 22 Dec 2023 04:22:54 -0800 (PST) Received: from grind.dc1.ventanamicro.com (201-69-66-51.dial-up.telesp.net.br. [201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:22:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247773; x=1703852573; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o5PCLfKnIm15G3iihfvhUkVoKe5lIweTL/Udt+M00pE=; b=CdMi2gCP821/AQ5tQickF1CJyDjXdG+taGzRZ+vA1AM0rnDcjBZTMY9NzWzJakEMmu z1EcEIrWdB3LXUbysBenAXkiKRnqNXBrqt6JGeFKxmgRDgKtuBc6QNrFejpFE9M/Pt88 EkQFzD4dDXcSJoiws1HikMU3+nOFqFaq1yctC+pD8yYd3h0tyi+4EkAM1WgXfJgeCGet B1kIPcLC6Dtcoqb1Aa6TpCvY7TooMMb5oTydp3ygazxXaqBPVxQMLk5eP+wy7nMFTTNo 9tv1XXfVIO396KBEbZQoJ74oSeNtWWICzBGaN99R355s8hK7szaWHGBbfUlRftzJIGNU 80sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247773; x=1703852573; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o5PCLfKnIm15G3iihfvhUkVoKe5lIweTL/Udt+M00pE=; b=BTtkiNCeS/ymK2qh2i+pFZUE1PXo2SvGyupDg0FtyPlNk0QWNx1yjj06INgu2Oxe8A w9QB5y0TTOU3ePfImW0t5IbD6HURIpuddDrvF8YeehcbbAdkkcRTHhyivAt6czkh9o/w YQLXK5qhNS+OHAXwnR//3s8LFm/wd0KZ6vHSZSEmxBGpIxAtKxUJwHes4Lgxucb8oAOJ feabXFJtCWQ9mmADATl/kXYct3/envGSas044lXQLnAJ2tOhaVgv/38nVjaS+yd77Z6P YIrh4sFQ59BXD5Gqwd2n2OWYdG2iUsw+j0lG3RwlPI286QEQxT9JrN5fcqZWJ4coVsPS /qOg== X-Gm-Message-State: AOJu0YxKKF4bZVNaVcauumSg/dDdUhXnTKLpHNYyNw3AezAJwr7BgabF 4X6l+v84099J60NvMFTPwCO6PTT0wTr7F17YazsbKY3IZt+muw== X-Google-Smtp-Source: AGHT+IHVH0H/8qqXx6ZSWiuMdWtRpmM7EJx1MlDvGjt4FXbRkT9CRglAwvefH9YVlulTNbnPCMYQgw== X-Received: by 2002:a05:6a20:7491:b0:18f:e56b:9848 with SMTP id p17-20020a056a20749100b0018fe56b9848mr1442446pzd.13.1703247772827; Fri, 22 Dec 2023 04:22:52 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 04/16] target/riscv: move 'mmu' to riscv_cpu_properties[] Date: Fri, 22 Dec 2023 09:22:23 -0300 Message-ID: <20231222122235.545235-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247914425100002 Content-Type: text/plain; charset="utf-8" Commit 7f0bdfb5bfc ("target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()") already did some of the work by making some cpu_init() functions to explictly enable their own 'mmu' default. The generic CPUs didn't get update by that commit, so they are still relying on the defaults set by the 'mmu' option. But having 'mmu' and 'pmp' being default=3Dtrue will force CPUs that doesn't implement these options to set them to 'false' in their cpu_init(), which isn't ideal. We'll move 'mmu' to riscv_cpu_properties[] without any defaults, i.e. the default will be 'false'. Compensate it by manually setting 'mmu =3D true' to the generic CPUs that requires it. Implement a setter for it to forbid the 'mmu' setting to be changed for vendor CPUs. This will allow the option to exist for all CPUs and, at the same time, protect vendor CPUs from undesired changes: $ ./build/qemu-system-riscv64 -M virt -cpu sifive-e51,mmu=3Dtrue qemu-system-riscv64: can't apply global sifive-e51-riscv-cpu.mmu=3Dtrue: CPU 'sifive-e51' does not allow changing the value of 'mmu' Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 67 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 63 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fb3d23b047..080713b9b5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -410,6 +410,8 @@ static void riscv_max_cpu_init(Object *obj) CPURISCVState *env =3D &cpu->env; RISCVMXL mlx =3D MXL_RV64; =20 + cpu->cfg.mmu =3D true; + #ifdef TARGET_RISCV32 mlx =3D MXL_RV32; #endif @@ -424,7 +426,11 @@ static void riscv_max_cpu_init(Object *obj) #if defined(TARGET_RISCV64) static void rv64_base_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + + cpu->cfg.mmu =3D true; + /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV64, 0); /* Set latest version of privileged specification */ @@ -542,13 +548,18 @@ static void rv64_veyron_v1_cpu_init(Object *obj) =20 static void rv128_base_cpu_init(Object *obj) { + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + if (qemu_tcg_mttcg_enabled()) { /* Missing 128-bit aligned atomics */ error_report("128-bit RISC-V currently does not work with Multi " "Threaded TCG. Please use: -accel tcg,thread=3Dsingle= "); exit(EXIT_FAILURE); } - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + + cpu->cfg.mmu =3D true; + /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV128, 0); /* Set latest version of privileged specification */ @@ -560,7 +571,11 @@ static void rv128_base_cpu_init(Object *obj) #else static void rv32_base_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + + cpu->cfg.mmu =3D true; + /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV32, 0); /* Set latest version of privileged specification */ @@ -1431,6 +1446,19 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_ex= ts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +static bool riscv_cpu_is_vendor(Object *obj) +{ + return !riscv_cpu_is_generic(obj); +} + +static void cpu_set_prop_err(RISCVCPU *cpu, const char *propname, + Error **errp) +{ + g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); + error_setg(errp, "CPU '%s' does not allow changing the value of '%s'", + cpuname, propname); +} + static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -1468,8 +1496,37 @@ static const PropertyInfo prop_pmu_num =3D { .set =3D prop_pmu_num_set, }; =20 +static void prop_mmu_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value; + + visit_type_bool(v, name, &value, errp); + + if (cpu->cfg.mmu !=3D value && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, "mmu", errp); + return; + } + + cpu->cfg.mmu =3D value; +} + +static void prop_mmu_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.mmu; + + visit_type_bool(v, name, &value, errp); +} + +static const PropertyInfo prop_mmu =3D { + .name =3D "mmu", + .get =3D prop_mmu_get, + .set =3D prop_mmu_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), =20 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), @@ -1491,6 +1548,8 @@ static Property riscv_cpu_properties[] =3D { MAKE_64BIT_MASK(3, 16)), {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ =20 + {.name =3D "mmu", .info =3D &prop_mmu}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1703247795; cv=none; d=zohomail.com; s=zohoarc; b=GVfHjS/lThJbrI4H2G0OyAtTZ1JKUN/XGQHJxy5oTIIrAM1objirmWwimJxEE7DUQOO6vgx4TxFss+Obodq6sqo6O6TeLKalXCKbmwTHZdgYt71DOZ0xncHQstJeSFs/IkyGv43674iVGXcILJMzw0aK/75TXU0ND8j4lomfTOc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703247795; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jMiNukS15sXZyEFe1/DpEuyjyQKpRoVTTin9o1fOUjw=; b=f3cmyP3Znk15wCRNfMa0KM8pb8m6XApG3RqUTjzun+GeQre/PYbge8Zxlm2Xf7KEWebEkVTQeOR95lFJ921Ic5k02aA22K10sSKGvhrnxmtLFlObqWQ037w2OkIT+vznfnwolTOSZI/6yBR48w4MA5cxShRWD5vk5c/wSTazESw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170324779544642.258538571104964; Fri, 22 Dec 2023 04:23:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rGeYS-0001a7-T0; Fri, 22 Dec 2023 07:23:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rGeYP-0001Z7-Ci for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:23:01 -0500 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rGeYL-00069d-N2 for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:23:01 -0500 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-5c21e185df5so1376870a12.1 for ; Fri, 22 Dec 2023 04:22:57 -0800 (PST) Received: from grind.dc1.ventanamicro.com (201-69-66-51.dial-up.telesp.net.br. [201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:22:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247776; x=1703852576; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jMiNukS15sXZyEFe1/DpEuyjyQKpRoVTTin9o1fOUjw=; b=QmMgr+VHULFWx9+3Kv6cXz7qJmGhSg127781QYqXGJythaZXsT4SX0qUOGNhJYCStH Nst1qlTJA3E74mBwoLHnmmZoaiFTjJRSjGGTPlrUT1HgPG4lR6H8+EJeOAICcQE35ns1 sgrqYZOgzmSN+6XvL90/oTM3kvR+HrPp5hleB0C7ZuMjiRrCWVQp2MI/7EtI7WOYQlhr iGxSueVN2kxecZgoLQVlCqDsvJpCv1pX4inqMCKKY9KtzjkHV0Zm8hoc2n9Q5ZddaIJD luTsQAOjA6SjVGQE0XXWJ1XTHqM0JZf3TU0+noovIyP1SqugH01gR1iyxNKlgU736oO4 ZHGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247776; x=1703852576; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jMiNukS15sXZyEFe1/DpEuyjyQKpRoVTTin9o1fOUjw=; b=IVxozQsvAjdsnQUa441AlZnAQeZ2nL99ICRUOeni6Goo/EEUDIKui8F/vnph5+40JV 65vBp9OddVHq6Fa/zHPae/+jmZRa8j1r3tpCHxjwN9oPd175mmltSqq9BHC98NLVRn/C VKf32MJYfCqKvHbnq6+AtbXD5/YZzR79d4iYT8IMbz5W937NrZljp1K4QURrZXPDoEl4 gH4iiquum/XRDlTVmoGA6NOht4Tb/DeYM3APWvUu3Ddy4heJ+J4Z/lITQc3lmI99OggC xqfa1W2qCyFsJZ5ZlKT6CAzu3kciEtVne0Adw1faFECF7VOhaad10e1e8M+pP8h2duh0 Fpeg== X-Gm-Message-State: AOJu0YyDEunOt5Xe2rfO7sktcEJasT6YniZ2kJ9KP4my1HbSoM137+5Y Yy8+WolljY/ouO+R3RAbmHnrx22d0QOu7mbI4fJirOv78KuS+A== X-Google-Smtp-Source: AGHT+IF9U3E6k7sk8LhGa8fFxDLg15xPPDAg7iyHuMn9KB6zMu/e+4LLvs8PpHAHb3met77aFFGr0Q== X-Received: by 2002:a05:6a20:3d89:b0:190:351b:a2ae with SMTP id s9-20020a056a203d8900b00190351ba2aemr1332715pzi.62.1703247775764; Fri, 22 Dec 2023 04:22:55 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 05/16] target/riscv: move 'pmp' to riscv_cpu_properties[] Date: Fri, 22 Dec 2023 09:22:24 -0300 Message-ID: <20231222122235.545235-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247796328100003 Content-Type: text/plain; charset="utf-8" Move 'pmp' to riscv_cpu_properties[], creating a new setter() for it that forbids 'pmp' to be changed in vendor CPUs, like we did with the 'mmu' option. We'll also have to manually set 'pmp =3D true' to generic CPUs that were still relying on the previous default to set it. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 080713b9b5..bdb6466c84 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -411,6 +411,7 @@ static void riscv_max_cpu_init(Object *obj) RISCVMXL mlx =3D MXL_RV64; =20 cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; =20 #ifdef TARGET_RISCV32 mlx =3D MXL_RV32; @@ -430,6 +431,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &cpu->env; =20 cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; =20 /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV64, 0); @@ -559,6 +561,7 @@ static void rv128_base_cpu_init(Object *obj) } =20 cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; =20 /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV128, 0); @@ -575,6 +578,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &cpu->env; =20 cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; =20 /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV32, 0); @@ -1526,9 +1530,37 @@ static const PropertyInfo prop_mmu =3D { .set =3D prop_mmu_set, }; =20 -Property riscv_cpu_options[] =3D { - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), +static void prop_pmp_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value; + + visit_type_bool(v, name, &value, errp); =20 + if (cpu->cfg.pmp !=3D value && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + return; + } + + cpu->cfg.pmp =3D value; +} + +static void prop_pmp_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.pmp; + + visit_type_bool(v, name, &value, errp); +} + +static const PropertyInfo prop_pmp =3D { + .name =3D "pmp", + .get =3D prop_pmp_get, + .set =3D prop_pmp_set, +}; + +Property riscv_cpu_options[] =3D { DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), =20 @@ -1549,6 +1581,7 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ =20 {.name =3D "mmu", .info =3D &prop_mmu}, + {.name =3D "pmp", .info =3D &prop_pmp}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1703247903; cv=none; d=zohomail.com; s=zohoarc; b=ZXrE07Cyqh3zYq45NZSWo46zUotdFIATbjDS/TiHXZ8aEorL5H9IRokYATpX3dQV2+CLoCE8TG7AAdA3Y77kn16YlOTkHdrGOUygqzIZFZXqMeGhCI4NFeoQfhE6FHFFuH8m2ZGFELOYM80TowsPQ6CNt9B5e2Ur+GRMB/2ARvY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703247903; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8l/9hykJG5FQUK8/sY9Emc0HqMF3QSzRWQv9f85u3n8=; b=SLFtgNVUxTH0zgfsFRwQO5q2aEjK/xr6tBWgopIS3yBQ4dIIFTGwJWx5iZnt5GGHsG8LQF+3n5/mITpu45Q9RB0j0hQmqpF3anoIbFjh+Tt/77l9LZNbMFE2Hy6O2r5LOsqVCwvMs6XJIW0yIRUCG3agiM2vambZNLclueSR9ZU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703247903191780.0877933818028; Fri, 22 Dec 2023 04:25:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rGeYa-0001ct-Ev; Fri, 22 Dec 2023 07:23:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rGeYY-0001bo-DO for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:23:10 -0500 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rGeYO-00069w-Jn for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:23:10 -0500 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-6d7750e2265so1141260b3a.3 for ; Fri, 22 Dec 2023 04:23:00 -0800 (PST) Received: from grind.dc1.ventanamicro.com (201-69-66-51.dial-up.telesp.net.br. [201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:22:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247779; x=1703852579; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8l/9hykJG5FQUK8/sY9Emc0HqMF3QSzRWQv9f85u3n8=; b=U11Dda4AxJtIPzESoD/4WtlqlfyYPArW/rz05QVy6X9zdfPvzWUuWQRLNnm9mI9khr /RHD4LfGeGUbbZAEqb2HwrBoUK9SXNOtrriFO7q2Owgq3VFZn0WId4RzK5r8rWArrt41 CKPAkgBoffMZJR5AKSIIeTAzfELvv5OyWayp4zkomIreFNda12Y0l31/CE+ZWh+cH9ge mu4McojnEvHoyw75SecJx6uYfiYyaN9PowOvX7YnQ3nxJrZ97uZ9l2WtLykEfqmOku11 +4s/+nP6whl1OfZ6WArLbnkBTPw1oMwM8q24d7L+1rBbG17I4mkM91QC4T4OZM9lFJWa 5Iow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247779; x=1703852579; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8l/9hykJG5FQUK8/sY9Emc0HqMF3QSzRWQv9f85u3n8=; b=Qqj0Gq4t4DQCOFd26uh/C3aCtb5qGAyUD0+MJJBpfJ/V6EIGaZgkU98ihvzlXpb5Ha qjK5tUkwpstLTg0NvcB4YdHbj+wqjt2Jgd4R9eShxBNIy/KKU/uAptclFz4moDVJ2SNC Ad6RPuxb5KfWBdtThuneCbeuqClGN24AcJ0CykZbETDommXx/ZF4i1bF/jvF3wLU2uTO eoiIF3BpbIZ8ibM7v725jLi4iTyyRSdHy4Iy5ykxmZUvEUaKnTl5Zaf+JgRAEuBHRVwF 2kvWESRX5Z0Iym18q31TITaHXYXJyQjimhVpdTJyofRbGO7ipU0ocdSoqI23KCbEFjbu s/0g== X-Gm-Message-State: AOJu0Yy9HuBn6suTBb8GY5BKwfS5mw1ZHemt5AKmqp41auZLXKdA9VoF ufRF48bI0p9PXMCQW6dybhDk/FOX6mE9jgQjdoo5U2UsLeFJjQ== X-Google-Smtp-Source: AGHT+IEcJaf47J/vkrb9RM02h0Nx0IvsUc3trOfd5P+AoRaExmZ1Q7YwW+a9OzEll7pVxhgi44VjtQ== X-Received: by 2002:a05:6a00:1c85:b0:6d9:6b40:d2f6 with SMTP id y5-20020a056a001c8500b006d96b40d2f6mr984903pfw.2.1703247778879; Fri, 22 Dec 2023 04:22:58 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 06/16] target/riscv: rework 'priv_spec' Date: Fri, 22 Dec 2023 09:22:25 -0300 Message-ID: <20231222122235.545235-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247904405100023 Content-Type: text/plain; charset="utf-8" 'priv_spec' and 'vext_spec' are two string options used as a fancy way of setting integers in the CPU state (cpu->env.priv_ver and cpu->env.vext_ver). It requires us to deal with string parsing and to store them in cpu_cfg. We must support these string options, but we don't need to store them. We have a precedence for this kind of arrangement in target/ppc/compat.c, ppc_compat_prop_get|set, getters and setters used for the 'max-cpu-compat' class property of the pseries ppc64 machine. We'll do the same with both 'priv_spec' and 'vext_spec'. For 'priv_spec', the validation from riscv_cpu_validate_priv_spec() will be done by the prop_priv_spec_set() setter, while also preventing it to be changed for vendor CPUs. Add two helpers that converts env->priv_ver back and forth to its string representation. These helpers allow us to get a string and set 'env->priv_ver' and return a string giving the current env->priv_ver value. In other words, make the cpu->cfg.priv_spec string obsolete. Last but not the least, move the reworked 'priv_spec' option to riscv_cpu_properties[]. After all said and done, we don't need to store the 'priv_spec' string in the CPU state, and we're now protecting vendor CPUs from priv_ver changes: $ ./build/qemu-system-riscv64 -M virt -cpu sifive-e51,priv_spec=3D"v1.12.0" qemu-system-riscv64: can't apply global sifive-e51-riscv-cpu.priv_spec=3Dv1= .12.0: CPU 'sifive-e51' does not allow changing the value of 'priv_spec' Current 'priv_spec' val: v1.10.0 $ Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 72 +++++++++++++++++++++++++++++++++++++- target/riscv/cpu.h | 3 ++ target/riscv/cpu_cfg.h | 1 - target/riscv/tcg/tcg-cpu.c | 29 --------------- 4 files changed, 74 insertions(+), 31 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bdb6466c84..1302d32de3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1560,8 +1560,76 @@ static const PropertyInfo prop_pmp =3D { .set =3D prop_pmp_set, }; =20 +static int priv_spec_from_str(const char *priv_spec_str) +{ + int priv_version =3D -1; + + if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) { + priv_version =3D PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) { + priv_version =3D PRIV_VERSION_1_11_0; + } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_10_0_STR)) { + priv_version =3D PRIV_VERSION_1_10_0; + } + + return priv_version; +} + +static const char *priv_spec_to_str(int priv_version) +{ + switch (priv_version) { + case PRIV_VERSION_1_10_0: + return PRIV_VER_1_10_0_STR; + case PRIV_VERSION_1_11_0: + return PRIV_VER_1_11_0_STR; + case PRIV_VERSION_1_12_0: + return PRIV_VER_1_12_0_STR; + default: + return NULL; + } +} + +static void prop_priv_spec_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + g_autofree char *value =3D NULL; + int priv_version =3D -1; + + visit_type_str(v, name, &value, errp); + + priv_version =3D priv_spec_from_str(value); + if (priv_version < 0) { + error_setg(errp, "Unsupported privilege spec version '%s'", value); + return; + } + + if (priv_version !=3D cpu->env.priv_ver && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %s\n", name, + object_property_get_str(obj, name, NULL)); + return; + } + + cpu->env.priv_ver =3D priv_version; +} + +static void prop_priv_spec_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + const char *value =3D priv_spec_to_str(cpu->env.priv_ver); + + visit_type_str(v, name, (char **)&value, errp); +} + +static const PropertyInfo prop_priv_spec =3D { + .name =3D "priv_spec", + .get =3D prop_priv_spec_get, + .set =3D prop_priv_spec_set, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), =20 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), @@ -1583,6 +1651,8 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "mmu", .info =3D &prop_mmu}, {.name =3D "pmp", .info =3D &prop_pmp}, =20 + {.name =3D "priv_spec", .info =3D &prop_priv_spec}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cfe965e512..e8a691ca63 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -77,6 +77,9 @@ const char *riscv_get_misa_ext_description(uint32_t bit); #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) =20 /* Privileged specification version */ +#define PRIV_VER_1_10_0_STR "v1.10.0" +#define PRIV_VER_1_11_0_STR "v1.11.0" +#define PRIV_VER_1_12_0_STR "v1.12.0" enum { PRIV_VERSION_1_10_0 =3D 0, PRIV_VERSION_1_11_0, diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index c67a8731d3..2dba1f0007 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -135,7 +135,6 @@ struct RISCVCPUConfig { bool ext_XVentanaCondOps; =20 uint32_t pmu_mask; - char *priv_spec; char *vext_spec; uint16_t vlen; uint16_t elen; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a09300e908..4d67b72d9e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -175,29 +175,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu,= Error **errp) } } =20 -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) -{ - CPURISCVState *env =3D &cpu->env; - int priv_version =3D -1; - - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { - priv_version =3D PRIV_VERSION_1_12_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version =3D PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version =3D PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - - env->priv_ver =3D priv_version; - } -} - static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { @@ -625,12 +602,6 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Er= ror **errp) CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 - riscv_cpu_validate_priv_spec(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - riscv_cpu_validate_misa_priv(env, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.22.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:23:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247782; x=1703852582; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iBtZzwTDCozyPVnBzjjyGBTf1NOZQJ7F92X7kXXP8w4=; b=J2Mfh0ozpzYdgWALbwt8jUsDtbgpMyjzHkd+xbtwCeKR85UjoK2HC2Q63psE71Ef3o kKOwt32eo7ybEw3fcM0Nh4W9Ug/LMHPYWAl5Ij2JkeT3m1WXsj7UY8nOIS+7TpBCzdUl jYrnxF8oe/fnRtKwJYnkIKLZT4FfCE7G97nf3G6sM2rmqEDVx5YGQzaskNOSkRxNjRDC T0+bYeuc5wIzsITPEYcDuxk6lEKw4MnJr9MsAeJoV9xVRvVvby7BXd54Uuvk5EJmrgq7 yBOPM74GHQbbOv0mkPu+sekgPLDzF1xu19530nayWTXbykw8umbM/EKmEixnyr1F9KOU VGbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247782; x=1703852582; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iBtZzwTDCozyPVnBzjjyGBTf1NOZQJ7F92X7kXXP8w4=; b=wtBVzyUm82qQ4L89iXGZABZzUQiZapxDcBjFvtt7qaashCP8WmN3g0qs/vv7EOdL16 8OLSU6D7x+VxjFmy48GcllygOMvFIS+CUhHkpdTWL+q9QswP18MvDYD6G5kLMFWTFEq/ AmruWfL8yd3QkFKU35Gglre9nJAApRv/PdzM6/OfooioHMEf6JRiR54KeSesOFHyA9l7 a1R252nvMW6AoRqSYPh6xsEn8CmV6l3BeoWzXLf2qvnSacqiBRoMHWGlbHkIm/nG2SV7 nrHQf4HoDcD8kkkZ+11/tJ2rtpnIvVewxbFaWAPBzKHIPPP7sVq92iCNDhjogn8gluOZ kBBw== X-Gm-Message-State: AOJu0YwiMltWuFCcHyS/Y9Nx1CTSMfAL/itAguffw5mpvOYu+NDavG8D q/7IXK5PL3ifrknlLr6lTWOo5b0Egvt3BCouAabHGTIlQP//lg== X-Google-Smtp-Source: AGHT+IHu5rcO9FXWC3M7p3HrPaPGBpZp2+FhSU88J8KmWm9sQDOAGieTifsoDIVq0jEtU2kNaKGPNA== X-Received: by 2002:a05:6a00:4b14:b0:6d9:366a:7836 with SMTP id kq20-20020a056a004b1400b006d9366a7836mr852937pfb.56.1703247781930; Fri, 22 Dec 2023 04:23:01 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 07/16] target/riscv: rework 'vext_spec' Date: Fri, 22 Dec 2023 09:22:26 -0300 Message-ID: <20231222122235.545235-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247870255100003 Content-Type: text/plain; charset="utf-8" The same rework did in 'priv_spec' is done for 'vext_spec'. This time is simpler, since we only accept one value ("v1.0") and we'll always have env->vext_ver set to VEXT_VERSION_1_00_0, thus we don't need helpers to convert string to 'vext_ver' back and forth like we needed for 'priv_spec'. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 42 ++++++++++++++++++++++++++++++++++---- target/riscv/cpu.h | 1 + target/riscv/cpu_cfg.h | 1 - target/riscv/tcg/tcg-cpu.c | 15 -------------- 4 files changed, 39 insertions(+), 20 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1302d32de3..d6625399a7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1237,6 +1237,8 @@ static void riscv_cpu_post_init(Object *obj) =20 static void riscv_cpu_init(Object *obj) { + RISCVCPU *cpu =3D RISCV_CPU(obj); + #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); @@ -1249,8 +1251,11 @@ static void riscv_cpu_init(Object *obj) * for all CPUs. Each accelerator will decide what to do when * users disable them. */ - RISCV_CPU(obj)->cfg.ext_zicntr =3D true; - RISCV_CPU(obj)->cfg.ext_zihpm =3D true; + cpu->cfg.ext_zicntr =3D true; + cpu->cfg.ext_zihpm =3D true; + + /* vext_spec is always 1_00_0 */ + cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; } =20 typedef struct misa_ext_info { @@ -1629,9 +1634,37 @@ static const PropertyInfo prop_priv_spec =3D { .set =3D prop_priv_spec_set, }; =20 -Property riscv_cpu_options[] =3D { - DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), +static void prop_vext_spec_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + g_autofree char *value =3D NULL; + + visit_type_str(v, name, &value, errp); + + if (!g_strcmp0(value, VEXT_VER_1_00_0_STR)) { + error_setg(errp, "Unsupported vector spec version '%s'", value); + return; + } + + cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; +} + +static void prop_vext_spec_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const char *value =3D VEXT_VER_1_00_0_STR; =20 + visit_type_str(v, name, (char **)&value, errp); +} + +static const PropertyInfo prop_vext_spec =3D { + .name =3D "vext_spec", + .get =3D prop_vext_spec_get, + .set =3D prop_vext_spec_set, +}; + +Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 @@ -1652,6 +1685,7 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "pmp", .info =3D &prop_pmp}, =20 {.name =3D "priv_spec", .info =3D &prop_priv_spec}, + {.name =3D "vext_spec", .info =3D &prop_vext_spec}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e8a691ca63..53101b82c5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -89,6 +89,7 @@ enum { }; =20 #define VEXT_VERSION_1_00_0 0x00010000 +#define VEXT_VER_1_00_0_STR "v1.0" =20 enum { TRANSLATE_SUCCESS, diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2dba1f0007..7112af6c4c 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -135,7 +135,6 @@ struct RISCVCPUConfig { bool ext_XVentanaCondOps; =20 uint32_t pmu_mask; - char *vext_spec; uint16_t vlen; uint16_t elen; uint16_t cbom_blocksize; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 4d67b72d9e..6501c29d8e 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -201,21 +201,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, "in the range [8, 64]"); return; } - - if (cfg->vext_spec) { - if (!g_strcmp0(cfg->vext_spec, "v1.0")) { - env->vext_ver =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, "Unsupported vector spec version '%s'", - cfg->vext_spec); - return; - } - } else if (env->vext_ver =3D=3D 0) { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - - env->vext_ver =3D VEXT_VERSION_1_00_0; - } } =20 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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[201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.23.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:23:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247785; x=1703852585; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ohkcTHo+nO+qUyiKr9PwLX4xkcWJcEp6mLlOiRy/wj8=; b=bBTW/DFnh/Ck9FdlveukDF4NRCIMMeNTMghXHA4DmWvWirfD39wCH931f0cy+62kak WifeOX93griBol4KoVhww4kx5h840lBbsus9grE1CSt9+7yhaQKe8zx0YUsCnnetzVmq c0wq+/7hyiGca8fyBh3qaw+4ytqDBjLOdF0KNK7Mgfcqu2UVWZJuKAZRZS1Cy6mGBxHM u1ggAioEpbUYNzFGWPqaXM5o9Rrhpnf7Y+p20annvPUY7CRZfYylWdAPHQX6a8rVQATJ qKunxG+EhVtAWim45Ndyf9L7PwSLMmjBLMrkMpXzQQEGpZ8CibbjLxLQYouI66ll9tz+ NrEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247785; x=1703852585; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ohkcTHo+nO+qUyiKr9PwLX4xkcWJcEp6mLlOiRy/wj8=; b=J5DC/rTns1IPALPZpYQrnl4a8DCYoGT2Wn/q9NG4PJdayXfQUk8t1LrGIr0jtVY6Sp k2TnL4o5SAN2LK20+pXGLgM4iACQEfX+8yFNjb9+PFjHDMP+o20x/HfPNijyGmWUHs7z PnbeP/a5ShSXLAh/vfEGOyESP6vB4/SMSTGclzsZjmEBuy4YA0+JZziWfXBfor5md3AS mcTT789KI6p60gyf84hCt08znfKp4AETvBIABQHLuCRtsweNjjYx5cn4SHegcU259o9b st5unM1Qn/ez3X+4xk15/XwH0biM8OH/dOCck0Djf2TLHurZnDHcccplhy7oa9uryZNM OepQ== X-Gm-Message-State: AOJu0YyJ8Tk+lXQs6zYHx8E1dLdBFkN2ecrAdv0vfHM3tvnLlAm3jClP dDjt/tNOGZy9RRIYNqoKgBLeG0t+qbzV8pweDgjBDjI15zF4WQ== X-Google-Smtp-Source: AGHT+IFhEaB7dA+SXEVIqb0pLI/6H6vpDW2g0cMBqmA1rPdbcGO4ZlNo/sbXKzI/nvDaDag6WAIE4A== X-Received: by 2002:aa7:8611:0:b0:6d9:83a8:658a with SMTP id p17-20020aa78611000000b006d983a8658amr1191057pfn.43.1703247784921; Fri, 22 Dec 2023 04:23:04 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 08/16] target/riscv: move 'vlen' to riscv_cpu_properties[] Date: Fri, 22 Dec 2023 09:22:27 -0300 Message-ID: <20231222122235.545235-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247942431100001 Content-Type: text/plain; charset="utf-8" Turning 'vlen' into a class property will allow its default value to be overwritten by cpu_init() later on, solving the issue we have now where CPU specific settings are getting overwritten by the default. For 'vlen', 'elen' and the blocksize options we need a way of tracking if the user set a value for them. This is benign for TCG since the cost of always validating these values are small, but for KVM we need syscalls to read the host values to make the validations. Knowing whether the user didn't touch the values makes a difference. We'll track user setting for these properties using a hash, like we do in the TCG driver. Common validation bits are moved from riscv_cpu_validate_v() to prop_vlen_set() to be shared with KVM. And, as done with every option we migrated to riscv_cpu_properties[], vendor CPUs can't have their 'vlen' value changed. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 63 +++++++++++++++++++++++++++++++++++++- target/riscv/tcg/tcg-cpu.c | 5 --- 2 files changed, 62 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d6625399a7..c2ff50bcab 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -29,6 +29,7 @@ #include "qapi/visitor.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" +#include "hw/core/qdev-prop-internal.h" #include "migration/vmstate.h" #include "fpu/softfloat-helpers.h" #include "sysemu/kvm.h" @@ -53,6 +54,15 @@ const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF,= RVD, RVV, #define BYTE(x) (x) #endif =20 +/* Hash that stores general user set numeric options */ +static GHashTable *general_user_opts; + +static void cpu_option_add_user_setting(const char *optname, uint32_t valu= e) +{ + g_hash_table_insert(general_user_opts, (gpointer)optname, + GUINT_TO_POINTER(value)); +} + #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 @@ -1244,6 +1254,8 @@ static void riscv_cpu_init(Object *obj) IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); #endif /* CONFIG_USER_ONLY */ =20 + general_user_opts =3D g_hash_table_new(g_str_hash, g_str_equal); + /* * The timer and performance counters extensions were supported * in QEMU before they were added as discrete extensions in the @@ -1664,8 +1676,54 @@ static const PropertyInfo prop_vext_spec =3D { .set =3D prop_vext_spec_set, }; =20 +static void prop_vlen_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + if (!is_power_of_2(value)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + + /* Always allow setting a default value */ + if (cpu->cfg.vlen =3D=3D 0) { + cpu->cfg.vlen =3D value; + return; + } + + if (value !=3D cpu->cfg.vlen && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.vlen); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.vlen =3D value; +} + +static void prop_vlen_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.vlen; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_vlen =3D { + .name =3D "vlen", + .get =3D prop_vlen_get, + .set =3D prop_vlen_set, + .set_default_value =3D qdev_propinfo_set_default_value_uint, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), =20 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), @@ -1687,6 +1745,9 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "priv_spec", .info =3D &prop_priv_spec}, {.name =3D "vext_spec", .info =3D &prop_vext_spec}, =20 + {.name =3D "vlen", .info =3D &prop_vlen, + .set_default =3D true, .defval.u =3D 128}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 6501c29d8e..8ec858e096 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -178,11 +178,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu,= Error **errp) static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { - if (!is_power_of_2(cfg->vlen)) { - error_setg(errp, "Vector extension VLEN must be power of 2"); - return; - } - if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { error_setg(errp, "Vector extension implementation only supports VLEN " --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1703247811; cv=none; d=zohomail.com; s=zohoarc; b=lrBxLH8Hm8MsHkSICPx6eXOnBruC4S9avfsUrRykM5VI9zcnXlkn/EBC65H82EI98Ni9q5YhxQWFMX1ApI4KehGT1ucxbUNUgFgHAcf/x4gZuV+ATm0zVJij4JD8fpLifmdTTGE03V+8re3IkPXuQDlCzkGysevFLuLL3TPRgRk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703247811; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.23.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:23:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247788; x=1703852588; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xVk73oD5tkPjlMefdi1dGnXgulNf3GxsdmvCZQ8ytTI=; b=QXmu6QhoaVx+SlU573Tu3zHcdppO/HjpFIMt57JkPKYd2N4hfJUBis8428/cIYnSOX 6pJWsfJR23hnHubTnnaKizFRMCPkeOHXAqyS+lQ0v2UO3Q/0X1t6oPSktwJ2nFeKyJqZ m/l2nl8NwdpTR/r3AQ2vJYS+6H+kl+gIlW9aGL2hp7uiQ8C0XAIp1crj33mn9QmeS3cj SollE5o8lYb2h+KXdPgoq9cc+HOj5lETGIioMafgRUxWtKqVA1a/yrkuwkNAhoFdbrZB LnSlTZsJzSNs7LeMHi1CRnC1DtqlQzg5R5XWow78Vz1G0elegMXqGM3mTDb8IJg5zd10 fqCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247788; x=1703852588; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xVk73oD5tkPjlMefdi1dGnXgulNf3GxsdmvCZQ8ytTI=; b=tEFkhM50EntJxML1bIoDEHKNYbLJY7U5lMD5U/9WXx4iRyKksXQTJ/+Tcoa5ThCjOg EAQ6agRIugT3c24gpCJl3aT2r0eX4TCOT0a+5UuJ3oCLzUq0BCvb5JUbpFyowN6joHOa 6JkA09y/02FKJTz1SwA5D32kJ6VsDZV4jqodgRSoIkMwKiFWC/xFVMruVumjqVUFLQNN G72eFZfJHbuePCF5mRvRCnpzGMsVZ7ZkPQX819d+ULrp1wToqBE3MI/n5iboYGgkvRYE vfCXtyCcHKV1j1kZ83/0X9kd29LcFzhQWTbw11fNwBZo31nooU5j8cOHhcP5Y+5iGuJt cUsg== X-Gm-Message-State: AOJu0Yy5SAIcivuAHmvxdUzkZ4faMooxMK+wMLH/kaw40z77YNvIk4cG cbDyO6Lonsmj/emJEjUJUP42ko+hIkTa7f9MYh15TGnRQJlVnw== X-Google-Smtp-Source: AGHT+IF+WQ6I/SF5ic+IzPNb0Ynh9e4qgJBkfz6hTkyIq17hbY5ic54swjk0z4uGgoynwpdWBWLaCA== X-Received: by 2002:a05:6358:63a8:b0:174:b807:1208 with SMTP id k40-20020a05635863a800b00174b8071208mr1096983rwh.62.1703247787943; Fri, 22 Dec 2023 04:23:07 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 09/16] target/riscv: move 'elen' to riscv_cpu_properties[] Date: Fri, 22 Dec 2023 09:22:28 -0300 Message-ID: <20231222122235.545235-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247814087100003 Content-Type: text/plain; charset="utf-8" Do the same thing we did with 'vlen' in the previous patch with 'elen'. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 52 ++++++++++++++++++++++++++++++++++++-- target/riscv/tcg/tcg-cpu.c | 5 ---- 2 files changed, 50 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c2ff50bcab..8be619b6f1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1723,9 +1723,54 @@ static const PropertyInfo prop_vlen =3D { .set_default_value =3D qdev_propinfo_set_default_value_uint, }; =20 -Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), +static void prop_elen_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + if (!is_power_of_2(value)) { + error_setg(errp, "Vector extension ELEN must be power of 2"); + return; + } + + /* Always allow setting a default value */ + if (cpu->cfg.elen =3D=3D 0) { + cpu->cfg.elen =3D value; + return; + } + + if (value !=3D cpu->cfg.elen && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.elen); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.elen =3D value; +} + +static void prop_elen_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.elen; =20 + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_elen =3D { + .name =3D "elen", + .get =3D prop_elen_get, + .set =3D prop_elen_set, + .set_default_value =3D qdev_propinfo_set_default_value_uint, +}; + +Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 @@ -1748,6 +1793,9 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "vlen", .info =3D &prop_vlen, .set_default =3D true, .defval.u =3D 128}, =20 + {.name =3D "elen", .info =3D &prop_elen, + .set_default =3D true, .defval.u =3D 64}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8ec858e096..84064ef7e0 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -185,11 +185,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, return; } =20 - if (!is_power_of_2(cfg->elen)) { - error_setg(errp, "Vector extension ELEN must be power of 2"); - return; - } - if (cfg->elen > 64 || cfg->elen < 8) { error_setg(errp, "Vector extension implementation only supports ELEN " --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1703247898; cv=none; d=zohomail.com; s=zohoarc; b=LyhBKzF6z4BtF9NS9ShD7EHp1D+Ppd1AjQW74IIabSmXm3HAjFbCI8MZ5353bEFdXKRqXUeE6y62KapfGf6+YLFWqBHcFfFBfpzcCIrVPddeufNR3u7zrv1qs80Tx5aLdXh0vYjEWf/TqMR5TSf1hIkwV5PLLIj71PAodBVFbTo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703247898; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:23:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247791; x=1703852591; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YBdFO1/O1xsYMUcgtmKgi1/AljKQg+BgIlpJLJG998U=; b=G4YnKrdI6qR/YIz8PQfgC6zhBr1kDuKKYCaY2qQSrQbmMwDj/aMAKb+tuPthtyEcM1 OjZ5ghn2y6jxf9IxR9+Al3tvJNGx/+MGlCSzderpG3ZfvJspi+9qiwlL0zL7tS/mp89y pc7TPnJeb96/1Q22autalWM2BebEWFhGlqctK4tupws4gvw1nbyph27HrX0FeYEr0fWS jqibTxzsfrc5M2eWGwGmL7fXPEP8GVeGI82en7oi7KCF9Oeb4SqJlUAkxG7qnRcP8JYF guHoF5whP7uWUdHDXnsYpwKV9yp6Mn6pw2S2mmuBH+4M5OxZbBvyLYRmfqD8ASBrLqtX 1nGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247791; x=1703852591; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YBdFO1/O1xsYMUcgtmKgi1/AljKQg+BgIlpJLJG998U=; b=fh3RDRwoQWoAWzR1StySGOziC9Uk+LJIqrz1hMgD66Ol1pMdHtCpLdakl+V7tKAhuS 4ow3hrxZmGfijgr+rE/lZG3lSNoqgxfFCy5+uDl/tGB8p0YnbPRF7DvuUmgwGbp1SVUT b+8e3O5MAfbz2IHvx1HptvnGTNwCap9PgusRByaPmkEQ73Cy2h3oF+tXuo7/2NBEA0My MuStW/fL1DwYtWzRZzExfkkiTbQ0jGIOU0BeON3lZxWLeRufrtLV/gZnz1WwIMz2x5vY yiqsXx9yLlZUnvQ/z5xyEbpzWfjM2ZP5K9WdR22flGwkYyrN0PvcPiy2X0z2AZt8S/44 9G8g== X-Gm-Message-State: AOJu0YyhGULVabie+QVYVjf28gWeU1ra8RZUYnV7KKslIX9xgxGmoU29 IVvAvoCLuDbfCWo50QUqfsIaGz1i6YIfNUUM9uVtUZnfyRhLQg== X-Google-Smtp-Source: AGHT+IFfh54e4U+6AzhBnWFB4AlLrA1/nhXCG+B4zu8MtwRla4vWW9c+q4hZj0wbk9NnfF9t3nYffA== X-Received: by 2002:a05:6a20:7da4:b0:194:dd52:bdc7 with SMTP id v36-20020a056a207da400b00194dd52bdc7mr1482747pzj.56.1703247790897; Fri, 22 Dec 2023 04:23:10 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 10/16] target/riscv: create finalize_features() for KVM Date: Fri, 22 Dec 2023 09:22:29 -0300 Message-ID: <20231222122235.545235-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247900327100011 Content-Type: text/plain; charset="utf-8" To turn cbom_blocksize and cboz_blocksize into class properties we need KVM specific changes. KVM is creating its own version of these options with a customized setter() that prevents users from picking an invalid value during init() time. This comes at the cost of duplicating each option that KVM supports. This will keep happening for each new shared option KVM implements in the future. We can avoid that by using the same property TCG uses and adding specific KVM handling during finalize() time, like TCG already does with riscv_tcg_cpu_finalize_features(). To do that, the common CPU property offers a way of knowing if an option was user set or not, sparing us from doing unneeded syscalls. riscv_kvm_cpu_finalize_features() is then created using the same KVMScratch CPU we already use during init() time, since finalize() time is still too early to use the official KVM CPU for it. cbom_blocksize and cboz_blocksize are then handled during finalize() in the same way they're handled by their KVM specific setter. With this change we can proceed with the blocksize changes in the common code without breaking the KVM driver. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 16 +++++++--- target/riscv/cpu.h | 1 + target/riscv/kvm/kvm-cpu.c | 59 ++++++++++++++++++++++++++++++++++++ target/riscv/kvm/kvm_riscv.h | 1 + 4 files changed, 72 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8be619b6f1..f49d31d753 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -63,6 +63,11 @@ static void cpu_option_add_user_setting(const char *optn= ame, uint32_t value) GUINT_TO_POINTER(value)); } =20 +bool riscv_cpu_option_set(const char *optname) +{ + return g_hash_table_contains(general_user_opts, optname); +} + #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 @@ -1056,17 +1061,18 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Err= or **errp) { Error *local_err =3D NULL; =20 - /* - * KVM accel does not have a specialized finalize() - * callback because its extensions are validated - * in the get()/set() callbacks of each property. - */ if (tcg_enabled()) { riscv_tcg_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } + } else if (kvm_enabled()) { + riscv_kvm_cpu_finalize_features(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 53101b82c5..988471c7ba 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -495,6 +495,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); +bool riscv_cpu_option_set(const char *optname); =20 #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 62a1e51f0a..70fb075846 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1490,6 +1490,65 @@ static void kvm_cpu_instance_init(CPUState *cs) } } =20 +void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + KVMScratchCPU kvmcpu; + struct kvm_one_reg reg; + uint64_t val; + int ret; + + /* short-circuit without spinning the scratch CPU */ + if (!cpu->cfg.ext_zicbom && !cpu->cfg.ext_zicboz) { + return; + } + + if (!kvm_riscv_create_scratch_vcpu(&kvmcpu)) { + error_setg(errp, "Unable to create scratch KVM cpu"); + return; + } + + if (cpu->cfg.ext_zicbom && + riscv_cpu_option_set(kvm_cbom_blocksize.name)) { + + reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + kvm_cbom_blocksize.kvm_reg_id); + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_setg(errp, "Unable to read cbom_blocksize, error %d", er= rno); + return; + } + + if (cpu->cfg.cbom_blocksize !=3D val) { + error_setg(errp, "Unable to set cbom_blocksize to a different " + "value than the host (%lu)", val); + return; + } + } + + if (cpu->cfg.ext_zicboz && + riscv_cpu_option_set(kvm_cboz_blocksize.name)) { + + reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + kvm_cboz_blocksize.kvm_reg_id); + reg.addr =3D (uint64_t)&val; + ret =3D ioctl(kvmcpu.cpufd, KVM_GET_ONE_REG, ®); + if (ret !=3D 0) { + error_setg(errp, "Unable to read cbom_blocksize, error %d", er= rno); + return; + } + + if (cpu->cfg.cboz_blocksize !=3D val) { + error_setg(errp, "Unable to set cboz_blocksize to a different " + "value than the host (%lu)", val); + return; + } + } + + kvm_riscv_destroy_scratch_vcpu(&kvmcpu); +} + static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); diff --git a/target/riscv/kvm/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h index 8329cfab82..4bd98fddc7 100644 --- a/target/riscv/kvm/kvm_riscv.h +++ b/target/riscv/kvm/kvm_riscv.h @@ -27,5 +27,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t= group_shift, uint64_t guest_num); void riscv_kvm_aplic_request(void *opaque, int irq, int level); int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state); +void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp); =20 #endif --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.23.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:23:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247794; x=1703852594; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qjT1roLG7CfvuK19j5grmNGYenzehWol3dj+uSF8GyA=; b=Gqq5I7lL3cnScp8AG3OE7ZMGvG0wfHLMsuXhLOYrERbDoz8H/PD7yD1lP/e5Laej5X rjWNeiCm0b4y9dwhwmHbWSjVfE6BmCfld+IUxSZBVXZEqhEBLE1QbJPHAopfIiBSoQQy 2YdjBdmlrnK69ewKS38+yoIQVtv1CfaMBf8lnmhM/WGs4mHbtflO6DqqSsujf7lVK06d 6Kg10u/ey5P6bvdVQuSb1E5aaileGJvDzo2bKfeK0yscd84Gpi7pRufVpuOq5RB+Jnf7 f0z7LOj2GJbavJ+QXZ/qrOJmGb6bLIepAw+AFqXzGOZDIG9bWnHmDI9lOAM3IZ5DKHZl 49EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247794; x=1703852594; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qjT1roLG7CfvuK19j5grmNGYenzehWol3dj+uSF8GyA=; b=xUBNL3VWw6Cs62M0z+XiVCl2Xo1dGq9ghGAMSEwQVecqVcjxT+hhUzvgiz1JMvTZfM kVOQc4UvLe1vYiWWLvVOl0RjwOLxj8ZD/nQzY4iphhW6ofO+nV64qP/pQToSQ9LCRbGB HYx9MBv1iLZxJJGYIuGeSbrf3L6NPzLnuT5qyYMhymCaJXu1rh3yqCTV8o9bSh6MVBJH rNIFume5zS1rE6TohPNLodxM7ktHmEhotbivS6zDCpiE+UEDcm4q+WjUORHFfBxXiSM1 MYHNQELJwHHwE4HSJl/POKi+mZmQ6Ha+xdAvbTJTktC0L54TCjCVe6DhyCwqQ5ddDRA1 3+IA== X-Gm-Message-State: AOJu0Yzv5MIs304kkqCQQHcRBGqT1TvfZ7ncsnbNIbzmeu7UorB6PiuR dNUC/I9XUYK0S7+DQA0ZHHVc8CXbRgzlJI8ogv+QtXzoYYejOw== X-Google-Smtp-Source: AGHT+IE4F8vjbnuH1cEv7ZyNUOxqqActUpSzljHjqq8vuqIT6Q+jNaSUbXGP16FUumkDPGLYReLPRw== X-Received: by 2002:a05:6a20:2593:b0:190:4b34:577d with SMTP id k19-20020a056a20259300b001904b34577dmr1085489pzd.88.1703247793879; Fri, 22 Dec 2023 04:23:13 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 11/16] target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[] Date: Fri, 22 Dec 2023 09:22:30 -0300 Message-ID: <20231222122235.545235-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247836220100001 Content-Type: text/plain; charset="utf-8" After adding a KVM finalize() implementation, turn cbom_blocksize into a class property. Follow the same design we used with 'vlen' and 'elen'. The duplicated 'cbom_blocksize' KVM property can be removed from kvm_riscv_add_cpu_user_properties(). Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 46 +++++++++++++++++++++++++++++++++++++- target/riscv/kvm/kvm-cpu.c | 4 ---- 2 files changed, 45 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f49d31d753..50825522b2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1776,8 +1776,49 @@ static const PropertyInfo prop_elen =3D { .set_default_value =3D qdev_propinfo_set_default_value_uint, }; =20 +static void prop_cbom_blksize_set(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + /* Always allow setting a default value */ + if (cpu->cfg.cbom_blocksize =3D=3D 0) { + cpu->cfg.cbom_blocksize =3D value; + return; + } + + if (value !=3D cpu->cfg.cbom_blocksize && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.cbom_blocksize); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.cbom_blocksize =3D value; +} + +static void prop_cbom_blksize_get(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.cbom_blocksize; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_cbom_blksize =3D { + .name =3D "cbom_blocksize", + .get =3D prop_cbom_blksize_get, + .set =3D prop_cbom_blksize_set, + .set_default_value =3D qdev_propinfo_set_default_value_uint, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_END_OF_LIST(), @@ -1802,6 +1843,9 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "elen", .info =3D &prop_elen, .set_default =3D true, .defval.u =3D 64}, =20 + {.name =3D "cbom_blocksize", .info =3D &prop_cbom_blksize, + .set_default =3D true, .defval.u =3D 64}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 70fb075846..1866b56913 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -484,10 +484,6 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) NULL, multi_cfg); } =20 - object_property_add(cpu_obj, "cbom_blocksize", "uint16", - NULL, kvm_cpu_set_cbomz_blksize, - NULL, &kvm_cbom_blocksize); - object_property_add(cpu_obj, "cboz_blocksize", "uint16", NULL, kvm_cpu_set_cbomz_blksize, NULL, &kvm_cboz_blocksize); --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1703247898; cv=none; d=zohomail.com; s=zohoarc; b=UrQWmlaN2tnsoLMP4MZdAbIF753X5wv8jCENnRc148WUJ6G0nKr5BCGBR9Gngt78RHJ/OlL+3S7RtL2NgCHaZ0siRFw6qfsHbJ4NBoI/C2wPJLl4wN/4QN3svjeayXxTalROSCZvvQzwgkNB3m+cqvasdlGOGyz8sT4c9uwdK6o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703247898; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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[201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.23.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:23:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247797; x=1703852597; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hjpf3AGLXfHTv0VRbfE18QlHn2bcFZdBUtge7yKuVWs=; b=Tv0A1zFIAIMQeGcRuyb9rZBAJXWndBCOl3jzMz8Pi8hBf2W+7O3nQVq9sqhmN8/4Lq KI9X046zjPfKbTRRprCWDlpM4U3QplxlbY6FR6znhYc6EDH73woW0QxFULmD4drMNDQO UzFY2kSZ5r17+iKL55Uw7XTlv5IFdMEXRlREskzUkkEWgtX1gxN8nJ1ys8NS/tq0GSv4 nQ5n/zjqDYa0cnZ+d0Xjf8umSmh1yEdPswHZlqS/k0ZHWjGCFnoyLy0Vy2EupN2xrDSz AblC3NQ3EVz6NWNoWiieeoh4NcebOimhyWwF6pgog4DHdlmISmOoQrD2L9EmIUUS3xKe f7ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247797; x=1703852597; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hjpf3AGLXfHTv0VRbfE18QlHn2bcFZdBUtge7yKuVWs=; b=qXAmjT5PWKEBmFtc+551EseiqrH9od//tc0aC255vywIM4ht48dh2XZDGZfcCLG5E8 Bqk6hYcf4XqpGWJbTvuEUbhA54YxOVeGwUwSVPV7rDnYtqrgglcHgec/WXIvLC7mYdKo wSyt3PHwXVFYdANOeMJT++W3ncWYolCdv9UUINLO2GgdH7CDHnld6UY9Le7d+Xc01IK0 WtTSMlBU/ONc8rzCCYfnsTBj7rMiVOesXjjny2r3qZMk0IWrU29e0kfaWIPF1QTrmswU E0MemFU8D+eHsBD+Wv0HaMoZY0Xm61x1n+BUBa/hbdOS+GzzRPbd8+wehMTX+90aqAI8 aWOw== X-Gm-Message-State: AOJu0Yx3AH8ONH5gkOeH10Fi3CxECMXieNDBQpUqz2YyM+WTRYTvxnIi 49z1xYcmJ8V65p4iFxYJmPVHbFNSUk+/rM7ZKjGt/fmAITNwSg== X-Google-Smtp-Source: AGHT+IGm46nQeudZhzPk2GGwUBH/X2oPoIjV9OtEHZ/AyE1ok4i8fmbRTVTuA/vKSDlfWdinj7fIbg== X-Received: by 2002:a6b:da08:0:b0:7ba:94d4:c342 with SMTP id x8-20020a6bda08000000b007ba94d4c342mr1274727iob.8.1703247796843; Fri, 22 Dec 2023 04:23:16 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 12/16] target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[] Date: Fri, 22 Dec 2023 09:22:31 -0300 Message-ID: <20231222122235.545235-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-io1-xd2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247900316100010 Content-Type: text/plain; charset="utf-8" Do the same we did with 'cbom_blocksize' in the previous patch. Remove the now unused kvm_cpu_set_cbomz_blksize() setter. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 45 +++++++++++++++++++++++++++++++++++++- target/riscv/kvm/kvm-cpu.c | 28 ------------------------ 2 files changed, 44 insertions(+), 29 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 50825522b2..f30058518a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1818,8 +1818,49 @@ static const PropertyInfo prop_cbom_blksize =3D { .set_default_value =3D qdev_propinfo_set_default_value_uint, }; =20 +static void prop_cboz_blksize_set(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint16_t value; + + if (!visit_type_uint16(v, name, &value, errp)) { + return; + } + + /* Always allow setting a default value */ + if (cpu->cfg.cboz_blocksize =3D=3D 0) { + cpu->cfg.cboz_blocksize =3D value; + return; + } + + if (value !=3D cpu->cfg.cboz_blocksize && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + error_append_hint(errp, "Current '%s' val: %u\n", + name, cpu->cfg.cboz_blocksize); + return; + } + + cpu_option_add_user_setting(name, value); + cpu->cfg.cboz_blocksize =3D value; +} + +static void prop_cboz_blksize_get(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + uint16_t value =3D RISCV_CPU(obj)->cfg.cboz_blocksize; + + visit_type_uint16(v, name, &value, errp); +} + +static const PropertyInfo prop_cboz_blksize =3D { + .name =3D "cboz_blocksize", + .get =3D prop_cboz_blksize_get, + .set =3D prop_cboz_blksize_set, + .set_default_value =3D qdev_propinfo_set_default_value_uint, +}; + Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_END_OF_LIST(), }; @@ -1845,6 +1886,8 @@ static Property riscv_cpu_properties[] =3D { =20 {.name =3D "cbom_blocksize", .info =3D &prop_cbom_blksize, .set_default =3D true, .defval.u =3D 64}, + {.name =3D "cboz_blocksize", .info =3D &prop_cboz_blksize, + .set_default =3D true, .defval.u =3D 64}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 1866b56913..137a8ab2bb 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -343,30 +343,6 @@ static KVMCPUConfig kvm_cboz_blocksize =3D { .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) }; =20 -static void kvm_cpu_set_cbomz_blksize(Object *obj, Visitor *v, - const char *name, - void *opaque, Error **errp) -{ - KVMCPUConfig *cbomz_cfg =3D opaque; - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint16_t value, *host_val; - - if (!visit_type_uint16(v, name, &value, errp)) { - return; - } - - host_val =3D kvmconfig_get_cfg_addr(cpu, cbomz_cfg); - - if (value !=3D *host_val) { - error_report("Unable to set %s to a different value than " - "the host (%u)", - cbomz_cfg->name, *host_val); - exit(EXIT_FAILURE); - } - - cbomz_cfg->user_set =3D true; -} - static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs) { CPURISCVState *env =3D &cpu->env; @@ -484,10 +460,6 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) NULL, multi_cfg); } =20 - object_property_add(cpu_obj, "cboz_blocksize", "uint16", - NULL, kvm_cpu_set_cbomz_blksize, - NULL, &kvm_cboz_blocksize); - riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); 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[201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.23.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:23:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247800; x=1703852600; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YOG7GjzzHRfLatHdrFLWdWSYTLIf6bifme29NkFErLs=; b=F2IYV+nZqnZ1zzUqx6NDefWaFhLUMTFlfZ8+vV6J8YZqyZCiwWmB9u1fdItYnWpgVR 8+XC9AJia2fzKOPSePKnKj9VnA2NfqnxLqQGSjUpzvW/hVTRuacQBaRWsq3e9bS8dzUK vA3K0/P6jTyBkKHDIx2L7y2n8JcsHft+mqIuUQV78WbmUtV8A9Lkma8AL9+EHu41D1Tw f7yioKOkC2RlM8h7z8L0VkZxLWcQV+i7I3ePVFkr0yIM8ACY/nWuE+v1ac9JfImlPhHC wRLk/jQGE0NJudCT+rSGGD9bb/4buDHXnHq4xPo6n7/ISmRBaDYImIkBl/OEkNynv87L sM1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247800; x=1703852600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YOG7GjzzHRfLatHdrFLWdWSYTLIf6bifme29NkFErLs=; b=G+qSuy5g7I1OW42CgTo7FOlIlb30dXb3sZ/AOwK8pTztESWV3+v7fTo+A12xV8/Tmk vqE9ZdgOZKy82ZnIlYirUg1cepOnorsbzroGAJiOCZ2Sgzmz/z1c8sRkumX2ppE/utiK B45d5TimEciGPbGB/06TMNALXM03uzSfYTrUn7GDBS4DdOVgTkjZ2/YaHqK2hEWSlSk/ Ca+wnm5SgkSE02C2mJIWdmx8Z+UQiVhHCPFmSvFY47hn9jiM3z/tLmTIqztkzetbgfCI 5sSxKbaDLqqL4Nm6lmpF+NOJVoFzYT5GZa8uTMx9uGiosPBV9vumkA2RdwpuLboPblAv mtRg== X-Gm-Message-State: AOJu0YyURFtZp11JENVHJZqX00vsVx74SY+wunwYLB4HU46v6us7PLMX xBJ5KJwuVsMNfatO0uBXxx+dmkYYES6rVT9q5WUaHToOf33mAg== X-Google-Smtp-Source: AGHT+IEFTjxgHsbSnfiabKY7tsWfEVffMExprXFVqAh6H2jw37VriuXH2cq7H6ygJ0VLiYFHtBIrnQ== X-Received: by 2002:a05:6a20:8e0c:b0:18d:10d7:3313 with SMTP id y12-20020a056a208e0c00b0018d10d73313mr1571708pzj.20.1703247799839; Fri, 22 Dec 2023 04:23:19 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 13/16] target/riscv: remove riscv_cpu_options[] Date: Fri, 22 Dec 2023 09:22:32 -0300 Message-ID: <20231222122235.545235-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247902348100019 Content-Type: text/plain; charset="utf-8" The array is empty and can be removed. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 5 ----- target/riscv/cpu.h | 1 - target/riscv/kvm/kvm-cpu.c | 9 --------- target/riscv/tcg/tcg-cpu.c | 4 ---- 4 files changed, 19 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f30058518a..7b1cc5d0c9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1860,11 +1860,6 @@ static const PropertyInfo prop_cboz_blksize =3D { .set_default_value =3D qdev_propinfo_set_default_value_uint, }; =20 -Property riscv_cpu_options[] =3D { - - DEFINE_PROP_END_OF_LIST(), -}; - static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 988471c7ba..f06987687a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -774,7 +774,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_extension= s[]; extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; -extern Property riscv_cpu_options[]; =20 typedef struct isa_ext_data { const char *name; diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 137a8ab2bb..5800abc9c6 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1443,19 +1443,10 @@ void kvm_riscv_aia_create(MachineState *machine, ui= nt64_t group_shift, static void kvm_cpu_instance_init(CPUState *cs) { Object *obj =3D OBJECT(RISCV_CPU(cs)); - DeviceState *dev =3D DEVICE(obj); =20 riscv_init_kvm_registers(obj); =20 kvm_riscv_add_cpu_user_properties(obj); - - for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { - /* Check if we have a specific KVM handler for the option */ - if (object_property_find(obj, prop->name)) { - continue; - } - qdev_property_add_static(dev, prop); - } } =20 void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 84064ef7e0..d3eeedc758 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -889,10 +889,6 @@ static void riscv_cpu_add_user_properties(Object *obj) riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); =20 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); - - for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { - qdev_property_add_static(DEVICE(obj), prop); - } } =20 /* --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1703247884; cv=none; d=zohomail.com; s=zohoarc; b=A2w751/31vREYp0My0qyXww3MghbNDNYUZ9RIwQ6oTnVKustGT9+lmXblqpVvp+q4k/lAgFSVTWFSbwrDP48miKJM9Wm5sVZd6SuySqqYf7aPRl4HegwtOmd2g4Z3ePuxxBnZG4XVjuCqMNOKLiLjpai0MLJs76Ue418SS+zhU4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703247884; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AOSghogFY34pLnpx65asA63Hfw4zzE9OM1WeOk4a/Mw=; b=F4cUbuMBe8UaI3WdtKDR7GAqjWSYZ2VZROs6KACR57+X+Yf7lWmi7YzjYOBuvV3JRWQtm0l5hALYdVoBQgnVjZvIbTb/Xla6ZtWmMf/vq3lyAAZMl7ZFAT75RqGG7Io7p6As//+sDyxKsh2F0pvWeN/OSCgUuOR+G1veAA5B2nw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703247884940721.8118662529129; Fri, 22 Dec 2023 04:24:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rGeYq-0001xJ-Lm; Fri, 22 Dec 2023 07:23:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rGeYp-0001x1-Qn for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:23:27 -0500 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rGeYo-0006Eu-5b for qemu-devel@nongnu.org; Fri, 22 Dec 2023 07:23:27 -0500 Received: by mail-pg1-x531.google.com with SMTP id 41be03b00d2f7-5cd86e3a9afso1243417a12.1 for ; Fri, 22 Dec 2023 04:23:24 -0800 (PST) Received: from grind.dc1.ventanamicro.com (201-69-66-51.dial-up.telesp.net.br. [201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:23:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247803; x=1703852603; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AOSghogFY34pLnpx65asA63Hfw4zzE9OM1WeOk4a/Mw=; b=Z5AAL8gHFb5vOGQ6eq70w199n96sZw2AHQVAuPkEUPHU82aIktnwQYpb5759w0Dp8e N0O3RWEI9BOPUaY9MHxf0ox0f07EBz68xGhhiSO/46mNyXHzjeqhwyYaSH3DafVNIxQK MrTS6Hx+kYDIBt9tmrvVO09qhulHt6L4cdVaaW3w6w0K7m1S8G63y2JKzDjRwAUTH7Cr ipIgq2Sg+I0JfMhwsAXutpOh3Fkb0QTIdt9bFDh+hEJCzPbAl4QMzpM3dMKUWSZ5leA/ glul7IrY9jQwM4aNyiUPEUZ2++O8iP9nwzO3LTaZzuLlYfOxnCUHorMJZOOk6QBtKZyd KQHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247803; x=1703852603; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AOSghogFY34pLnpx65asA63Hfw4zzE9OM1WeOk4a/Mw=; b=FPBvOE3dMgMr1FplNURMBIfm0QBjR0lh3UU2XAusG7lMkcQgxSsUlZYBMijJVZlaD7 4ZWB1e715a7xhNKakqGAZsEfR7kAkOwMFUgymdFo8Or3xlaRZ9zFe/5WHl6i5lMJ5dSz KlNtIwvMjRQm6pyUEoAc19SGbMN/h0hCDeInjsKtvB0z/+nUWcF9uo/pBYFH767tdtzv aqjD2omBBoXmzdFtw5UXL7VvDrWCOLIlzQLmLjtKB+RT7e6DU2I2S8i0TgG2sQTqHXst zz541oqwgF+bKuvqU9yySQpkEnuznRGW4e6ceSzmlmSXW0WUwZ+cWR+nCFpa+S7i4X3l X8vg== X-Gm-Message-State: AOJu0Yw1P7Mgi3v9E5WJUMZgKUlpXX+YgvbSASDhI4yW6md4uyGz40ve BvVIH8IkP+GxneMJdpYqPoRRF0rlI/1RcrZaNWavZdhY7xsyag== X-Google-Smtp-Source: AGHT+IHUvRbIWBv74g9F3VZmZpDkmLdYDPaJlaqZu9C0+cRDrjGP87KqjONSTb6hvYSxEgNQ4qDQZw== X-Received: by 2002:a05:6a20:8e10:b0:195:ce9:d731 with SMTP id y16-20020a056a208e1000b001950ce9d731mr1756998pzj.42.1703247802869; Fri, 22 Dec 2023 04:23:22 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 14/16] target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[] Date: Fri, 22 Dec 2023 09:22:33 -0300 Message-ID: <20231222122235.545235-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247886289100003 Content-Type: text/plain; charset="utf-8" Keep all class properties in riscv_cpu_properties[]. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 69 +++++++++++++++++++++++++--------------------- 1 file changed, 37 insertions(+), 32 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7b1cc5d0c9..260932e117 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1860,6 +1860,41 @@ static const PropertyInfo prop_cboz_blksize =3D { .set_default_value =3D qdev_propinfo_set_default_value_uint, }; =20 +static void prop_mvendorid_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint32_t prev_val =3D cpu->cfg.mvendorid; + uint32_t value; + + if (!visit_type_uint32(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s mvendorid (0x%x)", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mvendorid =3D value; +} + +static void prop_mvendorid_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint32_t value =3D RISCV_CPU(obj)->cfg.mvendorid; + + visit_type_uint32(v, name, &value, errp); +} + +static const PropertyInfo prop_mvendorid =3D { + .name =3D "mvendorid", + .get =3D prop_mvendorid_get, + .set =3D prop_mvendorid_set, +}; + static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 @@ -1884,6 +1919,8 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "cboz_blocksize", .info =3D &prop_cboz_blksize, .set_default =3D true, .defval.u =3D 64}, =20 + {.name =3D "mvendorid", .info =3D &prop_mvendorid}, + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif @@ -1948,35 +1985,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint32_t prev_val =3D cpu->cfg.mvendorid; - uint32_t value; - - if (!visit_type_uint32(v, name, &value, errp)) { - return; - } - - if (!dynamic_cpu && prev_val !=3D value) { - error_setg(errp, "Unable to change %s mvendorid (0x%x)", - object_get_typename(obj), prev_val); - return; - } - - cpu->cfg.mvendorid =3D value; -} - -static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - uint32_t value =3D RISCV_CPU(obj)->cfg.mvendorid; - - visit_type_uint32(v, name, &value, errp); -} - static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -2086,9 +2094,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; =20 - object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, - cpu_set_mvendorid, NULL, NULL); - object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, cpu_set_mimpid, NULL, NULL); =20 --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:23:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247806; x=1703852606; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7xgzruWaiL2ijKyy0M+AlR7DmJC0Qfumng5s9SdhQIo=; b=fEoAAoV8ZdaTHQeEHcOFEKh4F8It1AHLq+QjXVOzjh9g0Pt9C4gSzZzWhteFO+HNta DR8KbIwlvrHVPzoD17iwYhJ+UqNgH3owGoCZZ0Km9TNlOYIEdHKUDBIjlY3CC0hqm+uq HnL80Bb3VxsB0Nhp65pu5kG+Wm8CZ8VH6Y0QEKvMFeFOjsZUppAaF5nhMSOf/Wjs6dQz 9liPciOjEhQuL6mf2eEWnqnJaJ4sY2UW0LSd5bsmPus7McYiyf7fSI+hm0HWB9jYsbt0 fFs/lR0JCqFAuf6wD1qVc7LMc9xXxF+xFU2lj0n7L1SGueCs2s89A6/lqzr+w4wWVAnS SPFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247806; x=1703852606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7xgzruWaiL2ijKyy0M+AlR7DmJC0Qfumng5s9SdhQIo=; b=hO72ID23M+e0l3PfscvZqTW3uzNaNn7jMEuApqyZTCzqGZx27J0M8dQzpb4+ghdG7K by9WpfJtYpRmmFyzSg5NiGsNM7GjijyPU9nbDBCNFSBN+6WlG5wYnKkQMCdq7CvLAGof BMhKCiigAvdbp1a/z1xJTv+FxVeqfWksdI/bCxk4gqFzBAMgicinkNAciddH2sbLBhh4 yFPxT1dCOWT6VLlnkf1mZNBvtY0A75C5zdT4wyZyvcqH/J/HQ1O+cUuj466kAI+h+wBw EHfqwTtJhIRI4oD0mjXnOtBz7/t74EV1PPhx7+bqWe3Oh94M9v8AKIyPkNGhD9fIHZzY vZlg== X-Gm-Message-State: AOJu0YyceZyaXMjQ/kxZ7B8A3YxiqL03BYY35tamWRf8l5xz8kkOSZpS DA8AB3VYUm56ih+NX2/8FxODGvi4HIO4LYHuA5ehN1FSskKAjQ== X-Google-Smtp-Source: AGHT+IFsU93+27EGlJDMSMArPD1LkuWhySHKrcaj41iJPwM1Qwu92kldpkiPhB6Yq58Vt0nIBhC7tw== X-Received: by 2002:a05:6a00:1c8b:b0:6d8:840a:6d22 with SMTP id y11-20020a056a001c8b00b006d8840a6d22mr905002pfw.60.1703247805837; Fri, 22 Dec 2023 04:23:25 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 15/16] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[] Date: Fri, 22 Dec 2023 09:22:34 -0300 Message-ID: <20231222122235.545235-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247900303100009 Content-Type: text/plain; charset="utf-8" Keep all class properties in riscv_cpu_properties[]. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 68 ++++++++++++++++++++++++---------------------- 1 file changed, 36 insertions(+), 32 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 260932e117..613e8d5ddc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1895,6 +1895,41 @@ static const PropertyInfo prop_mvendorid =3D { .set =3D prop_mvendorid_set, }; =20 +static void prop_mimpid_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.mimpid; + uint64_t value; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")", + object_get_typename(obj), prev_val); + return; + } + + cpu->cfg.mimpid =3D value; +} + +static void prop_mimpid_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint64_t value =3D RISCV_CPU(obj)->cfg.mimpid; + + visit_type_uint64(v, name, &value, errp); +} + +static const PropertyInfo prop_mimpid =3D { + .name =3D "mimpid", + .get =3D prop_mimpid_get, + .set =3D prop_mimpid_set, +}; + static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 @@ -1920,6 +1955,7 @@ static Property riscv_cpu_properties[] =3D { .set_default =3D true, .defval.u =3D 64}, =20 {.name =3D "mvendorid", .info =3D &prop_mvendorid}, + {.name =3D "mimpid", .info =3D &prop_mimpid}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -1985,35 +2021,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint64_t prev_val =3D cpu->cfg.mimpid; - uint64_t value; - - if (!visit_type_uint64(v, name, &value, errp)) { - return; - } - - if (!dynamic_cpu && prev_val !=3D value) { - error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")", - object_get_typename(obj), prev_val); - return; - } - - cpu->cfg.mimpid =3D value; -} - -static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - uint64_t value =3D RISCV_CPU(obj)->cfg.mimpid; - - visit_type_uint64(v, name, &value, errp); -} - static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -2094,9 +2101,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; =20 - object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, - cpu_set_mimpid, NULL, NULL); - object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, cpu_set_marchid, NULL, NULL); =20 --=20 2.43.0 From nobody Tue Nov 26 22:36:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[201.69.66.51]) by smtp.gmail.com with ESMTPSA id g14-20020aa7874e000000b006ce7ad8c14esm3274901pfo.164.2023.12.22.04.23.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Dec 2023 04:23:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1703247809; x=1703852609; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4UXlD3dOTjdlaaDzoJWLbuNG3zI/mUMwmpOBZW6W3Y4=; b=HID45G0ZJ+4ctLB8BxReb4xIaDJMrzpFAIV2sXsaU/qQ7q/Akxiemr/ogcZNvNa+9v 4ytAsjfdBAewLEhtbIKPBjh5YbhiF5tWBzqfTxQTcWlrWoio4F+OCZoxFZ6BaacP2wEN IhHELEYoyVzd+NQTnwca4v5L2yPK1F4rfgSPw1+BXUvGDn7IX9/vKnLSiL7UYDFy8kRQ RO7G5F30GslgdY6LYH7Emtrfbiy4QvCWesbw5jQNQx1OsEj9sHGawkZkAWKe1wb7ar07 RSmgCZ4gnHSAo0bIJdtCti0yYCMkaoMDBkGB1m34pWGEFZKC7ggI3jDfVnln7r5+jrh5 iBeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703247809; x=1703852609; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4UXlD3dOTjdlaaDzoJWLbuNG3zI/mUMwmpOBZW6W3Y4=; b=hEFJ3bRciYKqPHD01S+00i802Bo6O1vRlYkTnKbe7PrCY1ViO75HHMjvgj/wALjcR0 ui/VRr/0X4gIOHx5zdJt5wteTbfFumQf9jvLSGW7CyW4ppsFsCyn43WUK1wmM2A0Wr1A 4Z0+SSk/2+DidxoGQjVJqszeEoRTPAvVwtPaGaSKMOfhoHA3yc7+w93b5ZZ6h30Y6MBc n6+3wflTUcvobs+LQyA4Z5L+0csWvONQ7iCKx9y2piHJOpYxmNdeP4n0HWWd/Z/cWJFa kp+jDQgREzW3xpEa/MtfODrYiTkRNaGdoo4gQ+gmakSfORI7MfbmmdbJH0gGuyzMu9P7 UGrQ== X-Gm-Message-State: AOJu0YyKt7JGJjBIcpxWoH88JUT8fbM3sQdvIbG6wiiZoUf8/1uLPeN5 quu3xTeazbO8LGPXla2TviZ1HkjTX9Z0ydZMQlGqiYWmlCifDg== X-Google-Smtp-Source: AGHT+IGY9pHsQCHlXPVGv9iQtg0eYdkXsN7WIzAsNnBignS6fw8PgUUvV9kazr5qMGGrpXbDiuLr8Q== X-Received: by 2002:a05:6358:4182:b0:172:93d5:e81 with SMTP id w2-20020a056358418200b0017293d50e81mr1253007rwc.7.1703247808935; Fri, 22 Dec 2023 04:23:28 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v2 16/16] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[] Date: Fri, 22 Dec 2023 09:22:35 -0300 Message-ID: <20231222122235.545235-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231222122235.545235-1-dbarboza@ventanamicro.com> References: <20231222122235.545235-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703247900360100012 Content-Type: text/plain; charset="utf-8" Keep all class properties in riscv_cpu_properties[]. Signed-off-by: Daniel Henrique Barboza Tested-by: Vladimir Isaev --- target/riscv/cpu.c | 110 +++++++++++++++++++++++---------------------- 1 file changed, 57 insertions(+), 53 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 613e8d5ddc..d2400fd447 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1930,6 +1930,62 @@ static const PropertyInfo prop_mimpid =3D { .set =3D prop_mimpid_set, }; =20 +static void prop_marchid_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + uint64_t prev_val =3D cpu->cfg.marchid; + uint64_t value, invalid_val; + uint32_t mxlen =3D 0; + + if (!visit_type_uint64(v, name, &value, errp)) { + return; + } + + if (!dynamic_cpu && prev_val !=3D value) { + error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", + object_get_typename(obj), prev_val); + return; + } + + switch (riscv_cpu_mxl(&cpu->env)) { + case MXL_RV32: + mxlen =3D 32; + break; + case MXL_RV64: + case MXL_RV128: + mxlen =3D 64; + break; + default: + g_assert_not_reached(); + } + + invalid_val =3D 1LL << (mxlen - 1); + + if (value =3D=3D invalid_val) { + error_setg(errp, "Unable to set marchid with MSB (%u) bit set " + "and the remaining bits zero", mxlen); + return; + } + + cpu->cfg.marchid =3D value; +} + +static void prop_marchid_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + uint64_t value =3D RISCV_CPU(obj)->cfg.marchid; + + visit_type_uint64(v, name, &value, errp); +} + +static const PropertyInfo prop_marchid =3D { + .name =3D "marchid", + .get =3D prop_marchid_get, + .set =3D prop_marchid_set, +}; + static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 @@ -1956,6 +2012,7 @@ static Property riscv_cpu_properties[] =3D { =20 {.name =3D "mvendorid", .info =3D &prop_mvendorid}, {.name =3D "mimpid", .info =3D &prop_mimpid}, + {.name =3D "marchid", .info =3D &prop_marchid}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), @@ -2021,56 +2078,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - bool dynamic_cpu =3D riscv_cpu_is_dynamic(obj); - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint64_t prev_val =3D cpu->cfg.marchid; - uint64_t value, invalid_val; - uint32_t mxlen =3D 0; - - if (!visit_type_uint64(v, name, &value, errp)) { - return; - } - - if (!dynamic_cpu && prev_val !=3D value) { - error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", - object_get_typename(obj), prev_val); - return; - } - - switch (riscv_cpu_mxl(&cpu->env)) { - case MXL_RV32: - mxlen =3D 32; - break; - case MXL_RV64: - case MXL_RV128: - mxlen =3D 64; - break; - default: - g_assert_not_reached(); - } - - invalid_val =3D 1LL << (mxlen - 1); - - if (value =3D=3D invalid_val) { - error_setg(errp, "Unable to set marchid with MSB (%u) bit set " - "and the remaining bits zero", mxlen); - return; - } - - cpu->cfg.marchid =3D value; -} - -static void cpu_get_marchid(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - uint64_t value =3D RISCV_CPU(obj)->cfg.marchid; - - visit_type_uint64(v, name, &value, errp); -} - static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); @@ -2101,9 +2108,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; =20 - object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, - cpu_set_marchid, NULL, NULL); - device_class_set_props(dc, riscv_cpu_properties); } =20 --=20 2.43.0