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Thu, 21 Dec 2023 09:51:59 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH 05/16] target/riscv: move 'pmp' to riscv_cpu_properties[] Date: Thu, 21 Dec 2023 14:51:26 -0300 Message-ID: <20231221175137.497379-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231221175137.497379-1-dbarboza@ventanamicro.com> References: <20231221175137.497379-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703181265506100007 Content-Type: text/plain; charset="utf-8" Move 'pmp' to riscv_cpu_properties[], creating a new setter() for it that forbids 'pmp' to be changed in vendor CPUs, like we did with the 'mmu' option. We'll also have to manually set 'pmp =3D true' to generic CPUs that were still relying on the previous default to set it. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 90dd2bccf6..cd20489f1b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -411,6 +411,7 @@ static void riscv_max_cpu_init(Object *obj) RISCVMXL mlx =3D MXL_RV64; =20 cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; =20 #ifdef TARGET_RISCV32 mlx =3D MXL_RV32; @@ -430,6 +431,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &cpu->env; =20 cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; =20 /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV64, 0); @@ -559,6 +561,7 @@ static void rv128_base_cpu_init(Object *obj) } =20 cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; =20 /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV128, 0); @@ -575,6 +578,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &cpu->env; =20 cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; =20 /* We set this in the realise function */ riscv_cpu_set_misa(env, MXL_RV32, 0); @@ -1526,9 +1530,37 @@ const PropertyInfo prop_mmu =3D { .set =3D prop_mmu_set, }; =20 -Property riscv_cpu_options[] =3D { - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), +static void prop_pmp_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value; + + visit_type_bool(v, name, &value, errp); =20 + if (cpu->cfg.pmp !=3D value && riscv_cpu_is_vendor(obj)) { + cpu_set_prop_err(cpu, name, errp); + return; + } + + cpu->cfg.pmp =3D value; +} + +static void prop_pmp_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.pmp; + + visit_type_bool(v, name, &value, errp); +} + +const PropertyInfo prop_pmp =3D { + .name =3D "pmp", + .get =3D prop_pmp_get, + .set =3D prop_pmp_set, +}; + +Property riscv_cpu_options[] =3D { DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), =20 @@ -1549,6 +1581,7 @@ static Property riscv_cpu_properties[] =3D { {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ =20 {.name =3D "mmu", .info =3D &prop_mmu}, + {.name =3D "pmp", .info =3D &prop_pmp}, =20 #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), --=20 2.43.0