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Thu, 21 Dec 2023 09:51:50 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH 02/16] target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[] Date: Thu, 21 Dec 2023 14:51:23 -0300 Message-ID: <20231221175137.497379-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231221175137.497379-1-dbarboza@ventanamicro.com> References: <20231221175137.497379-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12c; envelope-from=dbarboza@ventanamicro.com; helo=mail-il1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1703181153744100001 Content-Type: text/plain; charset="utf-8" Every property in riscv_cpu_options[] will be migrated to riscv_cpu_properties[]. This will make their default values init earlier, allowing cpu_init() functions to overwrite them. We'll also implement common getters and setters that both accelerators will use, allowing them to share validations that TCG is doing. For pmu-mask and pmu-num it's just a matter of migrating the properties from one array to the other. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 70bf10aa7c..ba62792e30 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1464,9 +1464,6 @@ const PropertyInfo prop_pmu_num =3D { }; =20 Property riscv_cpu_options[] =3D { - DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, MAKE_64BIT_MASK= (3, 16)), - {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), =20 @@ -1485,6 +1482,10 @@ Property riscv_cpu_options[] =3D { static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 + DEFINE_PROP_UINT32("pmu-mask", RISCVCPU, cfg.pmu_mask, + MAKE_64BIT_MASK(3, 16)), + {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ + #ifndef CONFIG_USER_ONLY DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), #endif --=20 2.43.0