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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=89.207.88.248; envelope-from=vadim.shakirov@syntacore.com; helo=mta-04.yadro.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_PERMERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 21 Dec 2023 08:45:53 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @syntacore.com) (identity @syntacore.com) X-ZM-MESSAGEID: 1703166420249100003 Content-Type: text/plain; charset="utf-8" In the AIA specification in the paragraph "Virtual interrupts for VS level" it is indicated for interrupts 13-63: if the bit in hideleg is enabled, then the corresponding vsip and vsie bits are aliases to sip and sie Signed-off-by: Vadim Shakirov Reviewed-by: Daniel Henrique Barboza --- target/riscv/csr.c | 36 ++++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 36f807d5f6..46a5d0c69a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1129,7 +1129,7 @@ static RISCVException write_stimecmph(CPURISCVState *= env, int csrno, =20 static const uint64_t delegable_ints =3D S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | LOCAL_INTERRUPT= S; -static const uint64_t vs_delegable_ints =3D VS_MODE_INTERRUPTS; +static const uint64_t vs_delegable_ints =3D VS_MODE_INTERRUPTS | LOCAL_INT= ERRUPTS; static const uint64_t all_ints =3D M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ @@ -1167,7 +1167,7 @@ static const target_ulong sip_writable_mask =3D SIP_S= SIP | MIP_USIP | MIP_UEIP | static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; -static const target_ulong vsip_writable_mask =3D MIP_VSSIP; +static const target_ulong vsip_writable_mask =3D MIP_VSSIP | LOCAL_INTERRU= PTS; =20 const bool valid_vm_1_10_32[16] =3D { [VM_1_10_MBARE] =3D true, @@ -2416,20 +2416,34 @@ static RISCVException write_sstatus(CPURISCVState *= env, int csrno, return write_mstatus(env, CSR_MSTATUS, newval); } =20 + +static uint64_t vsi_to_mi(uint64_t vsi) +{ + uint64_t mi; + + mi =3D (vsi & (VS_MODE_INTERRUPTS >> 1)) << 1; + mi |=3D vsi & LOCAL_INTERRUPTS; + + return mi; +} + static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t rval, mask =3D env->hideleg & VS_MODE_INTERRUPTS; + uint64_t rval, mask =3D env->hideleg & (VS_MODE_INTERRUPTS | + LOCAL_INTERRUPTS); =20 /* Bring VS-level bits to correct position */ - new_val =3D (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; - wr_mask =3D (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; + new_val =3D vsi_to_mi(new_val); + wr_mask =3D vsi_to_mi(wr_mask); =20 ret =3D rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); + if (ret_val) { - *ret_val =3D (rval & mask) >> 1; + *ret_val =3D (rval & (env->hideleg & VS_MODE_INTERRUPTS)) >> 1; + *ret_val |=3D rval & (env->hideleg & LOCAL_INTERRUPTS); } =20 return ret; @@ -2630,16 +2644,18 @@ static RISCVException rmw_vsip64(CPURISCVState *env= , int csrno, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t rval, mask =3D env->hideleg & VS_MODE_INTERRUPTS; + uint64_t rval, mask =3D env->hideleg & (VS_MODE_INTERRUPTS | + LOCAL_INTERRUPTS); =20 /* Bring VS-level bits to correct position */ - new_val =3D (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; - wr_mask =3D (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; + new_val =3D vsi_to_mi(new_val); + wr_mask =3D vsi_to_mi(wr_mask); =20 ret =3D rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask & vsip_writable_mask); if (ret_val) { - *ret_val =3D (rval & mask) >> 1; + *ret_val =3D (rval & (env->hideleg & VS_MODE_INTERRUPTS)) >> 1; + *ret_val |=3D rval & (env->hideleg & LOCAL_INTERRUPTS); } =20 return ret; --=20 2.34.1