From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155188; cv=none; d=zohomail.com; s=zohoarc; b=B1jtMYBFR2A6UjZJWhgJ6poD+OzMLdiVQuMdX4ecQLwkzAS8lmgKFQebOFiMsjOznwPBG8ORI6btZXuOTmPdfLBxU5Kw8joj8crt9TNWRznTCfdVlhGKdoaof5cXhsh7N9Cgsuj7gS2yzQ00hvIvfH9yadZKnng9Mx5IBNtqmZc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703155188; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RdsiaowAjsV2VhJV7X+uJO6SS3PjKGOvNs318qpxEnc=; b=H9AalETqfuBUHWhWlvW15ZERW144bW0rBcONXUCglpmeAKITS+AJqhhzec3J/8x2YJUWJiG3E+HUaC1U/pgq4fxLEMOcKhHrsQpziGdq3HpI3ADTCLlTZ2Ipd+n9WqUttSY1mfFLeHWlHDpamVMDIgii4J0pr31K91I0GVj1eh0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703155188916375.56725282688683; Thu, 21 Dec 2023 02:39:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rGGRy-0003sv-Ht; Thu, 21 Dec 2023 05:38:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rGGRo-0003jr-E8 for qemu-devel@nongnu.org; Thu, 21 Dec 2023 05:38:37 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rGGRd-0003q7-In for qemu-devel@nongnu.org; Thu, 21 Dec 2023 05:38:34 -0500 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-3365424df34so471933f8f.1 for ; Thu, 21 Dec 2023 02:38:21 -0800 (PST) Received: from draig.lan ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id c18-20020a05600c0a5200b0040c6d559490sm2887676wmq.3.2023.12.21.02.38.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Dec 2023 02:38:19 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id 0FE0E5F8AF; Thu, 21 Dec 2023 10:38:19 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703155100; x=1703759900; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RdsiaowAjsV2VhJV7X+uJO6SS3PjKGOvNs318qpxEnc=; b=smoqC5XBHIKRLdCzjk3C+N3c7Npc7lkVyPWKOvabPiCS7DrFTW9enRo7alMKR5yHGQ MEwSok6GxE0ShU2VqtOpNOBHrhyGB7d7O8chqqN7qxbAUuppL/udGWJXfdB+/WqZdTwh 4e291lO2YA7o7fupbrfgmuPUsyTeI7wDXlSNhpG3tRh3jL1tdyqLrUy6TKnEnS3Is9mG rKOGRoZJHqRP+SNVjJL5jHySlcAdIZd5omdxsQwKaLcNsg46ahaJWL65DP5q5AS6PU4I lwNt+/axVQl0k5UhaeFhz7uzvR4lYsCqUlyIgB3rHwoacPCZ+k1uehnUGi5vqF3PEViy dYtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703155100; x=1703759900; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RdsiaowAjsV2VhJV7X+uJO6SS3PjKGOvNs318qpxEnc=; b=NvCfo6/x8X/q8tS4afoMj7c/b+xukmWTGDucPhkkNoGPgjsfgQ+g5Zvn0t8hXhQeY5 4hBAEMVBHL14ufBhoF3N6BeJaVUBgnIpPZlEGHr+sOcMon4kJZdef+P3HXyb7SK69/mr sf+udMbicGj/B+YIoFEpHKHyKCbolZg1jhlh3OqqP9d68NRl1NLEbo6btnItaklXK4Cw H9GwCYmo/uGro/7pOJL+EStD8Qtvy0IS3QEg085es/uUsYaNxdrBLVH6xedVpHGPUx4v omTDvp2sOWmuPxS8cXCrALKwCqJpbBiV878aUZQPtbgwR5pe3Crt154BMKN8GfnzFDYf 0IAg== X-Gm-Message-State: AOJu0YyraJi+WdoIliH6GCiKoZQ66M1tZBoV8ewqI7JHu2du6R+r/v6A TqQ5P1lOUFay3xv7gT3PiYJwGg== X-Google-Smtp-Source: AGHT+IGNQvXI1TaGTd5rITt67gBKkdTgtOk28s10TrQMNaMkVZnKYF8g1lcS1QVjmQIWgMwv/uml1w== X-Received: by 2002:a05:600c:3108:b0:40c:29fb:2c4b with SMTP id g8-20020a05600c310800b0040c29fb2c4bmr624080wmo.148.1703155099929; Thu, 21 Dec 2023 02:38:19 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng Subject: [PATCH 01/40] tests/avocado: Add a test for a little-endian microblaze machine Date: Thu, 21 Dec 2023 10:37:39 +0000 Message-Id: <20231221103818.1633766-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155189791100001 From: Thomas Huth We've already got a test for a big endian microblaze machine, but so far we lack one for a little endian machine. Now that the QEMU advent calendar featured such an image, we can test the little endian mode, too. Signed-off-by: Thomas Huth Message-Id: <20231215161851.71508-1-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/avocado/machine_microblaze.py | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/tests/avocado/machine_microblaze.py b/tests/avocado/machine_mi= croblaze.py index 8d0efff30d2..807709cd11e 100644 --- a/tests/avocado/machine_microblaze.py +++ b/tests/avocado/machine_microblaze.py @@ -5,6 +5,8 @@ # This work is licensed under the terms of the GNU GPL, version 2 or # later. See the COPYING file in the top-level directory. =20 +import time +from avocado_qemu import exec_command, exec_command_and_wait_for_pattern from avocado_qemu import QemuSystemTest from avocado_qemu import wait_for_console_pattern from avocado.utils import archive @@ -33,3 +35,27 @@ def test_microblaze_s3adsp1800(self): # The kernel sometimes gets stuck after the "This architecture ..." # message, that's why we don't test for a later string here. This # needs some investigation by a microblaze wizard one day... + + def test_microblazeel_s3adsp1800(self): + """ + :avocado: tags=3Darch:microblazeel + :avocado: tags=3Dmachine:petalogix-s3adsp1800 + """ + + self.require_netdev('user') + tar_url =3D ('http://www.qemu-advent-calendar.org/2023/download/' + 'day13.tar.gz') + tar_hash =3D '6623d5fff5f84cfa8f34e286f32eff6a26546f44' + file_path =3D self.fetch_asset(tar_url, asset_hash=3Dtar_hash) + archive.extract(file_path, self.workdir) + self.vm.set_console() + self.vm.add_args('-kernel', self.workdir + '/day13/xmaton.bin') + self.vm.add_args('-nic', 'user,tftp=3D' + self.workdir + '/day13/') + self.vm.launch() + wait_for_console_pattern(self, 'QEMU Advent Calendar 2023') + time.sleep(0.1) + exec_command(self, 'root') + time.sleep(0.1) + exec_command_and_wait_for_pattern(self, + 'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png', + '821cd3cab8efd16ad6ee5acc3642a8ea') --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng Subject: [PATCH 02/40] tests/avocado: use snapshot=on in kvm_xen_guest Date: Thu, 21 Dec 2023 10:37:40 +0000 Message-Id: <20231221103818.1633766-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155185813100006 This ensures the rootfs is never permanently changed as we don't need persistence between tests anyway. Signed-off-by: Alex Benn=C3=A9e --- tests/avocado/kvm_xen_guest.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/avocado/kvm_xen_guest.py b/tests/avocado/kvm_xen_guest.py index 5391283113e..f8cb458d5db 100644 --- a/tests/avocado/kvm_xen_guest.py +++ b/tests/avocado/kvm_xen_guest.py @@ -59,7 +59,7 @@ def common_vm_setup(self): def run_and_check(self): self.vm.add_args('-kernel', self.kernel_path, '-append', self.kernel_params, - '-drive', f"file=3D{self.rootfs},if=3Dnone,forma= t=3Draw,id=3Ddrv0", + '-drive', f"file=3D{self.rootfs},if=3Dnone,snaps= hot=3Don,format=3Draw,id=3Ddrv0", '-device', 'xen-disk,drive=3Ddrv0,vdev=3Dxvda', '-device', 'virtio-net-pci,netdev=3Dunet', '-netdev', 'user,id=3Dunet,hostfwd=3D:127.0.0.1:0= -:22') --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng Subject: [PATCH 03/40] gitlab: include microblazeel in testing Date: Thu, 21 Dec 2023 10:37:41 +0000 Message-Id: <20231221103818.1633766-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155356728100005 This reverts aeb5f8f248e (gitlab: build the correct microblaze target) now we actually have a little-endian test in avocado thanks to this years advent calendar. Signed-off-by: Alex Benn=C3=A9e --- .gitlab-ci.d/buildtest.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index 91663946de4..ef71dfe8665 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -41,7 +41,7 @@ build-system-ubuntu: variables: IMAGE: ubuntu2204 CONFIGURE_ARGS: --enable-docs - TARGETS: alpha-softmmu microblaze-softmmu mips64el-softmmu + TARGETS: alpha-softmmu microblazeel-softmmu mips64el-softmmu MAKE_CHECK_ARGS: check-build =20 check-system-ubuntu: @@ -61,7 +61,7 @@ avocado-system-ubuntu: variables: IMAGE: ubuntu2204 MAKE_CHECK_ARGS: check-avocado - AVOCADO_TAGS: arch:alpha arch:microblaze arch:mips64el + AVOCADO_TAGS: arch:alpha arch:microblazeel arch:mips64el =20 build-system-debian: extends: --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng Subject: [PATCH 04/40] chardev: use bool for fe_is_open Date: Thu, 21 Dec 2023 10:37:42 +0000 Message-Id: <20231221103818.1633766-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155342708100001 The function qemu_chr_fe_init already treats be->fe_open as a bool and if it acts like a bool it should be one. While we are at it make the variable name more descriptive and add kdoc decorations. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20231211145959.93759-1-alex.bennee@linaro.org> --- v2 - rename to fe_is_open at f4bug's request --- include/chardev/char-fe.h | 19 ++++++++++++------- chardev/char-fe.c | 16 ++++++++-------- chardev/char.c | 2 +- 3 files changed, 21 insertions(+), 16 deletions(-) diff --git a/include/chardev/char-fe.h b/include/chardev/char-fe.h index 0ff6f875116..ecef1828355 100644 --- a/include/chardev/char-fe.h +++ b/include/chardev/char-fe.h @@ -7,8 +7,12 @@ typedef void IOEventHandler(void *opaque, QEMUChrEvent event); typedef int BackendChangeHandler(void *opaque); =20 -/* This is the backend as seen by frontend, the actual backend is - * Chardev */ +/** + * struct CharBackend - back end as seen by front end + * @fe_is_open: the front end is ready for IO + * + * The actual backend is Chardev + */ struct CharBackend { Chardev *chr; IOEventHandler *chr_event; @@ -17,7 +21,7 @@ struct CharBackend { BackendChangeHandler *chr_be_change; void *opaque; int tag; - int fe_open; + bool fe_is_open; }; =20 /** @@ -156,12 +160,13 @@ void qemu_chr_fe_set_echo(CharBackend *be, bool echo); =20 /** * qemu_chr_fe_set_open: + * @be: a CharBackend + * @is_open: the front end open status * - * Set character frontend open status. This is an indication that the - * front end is ready (or not) to begin doing I/O. - * Without associated Chardev, do nothing. + * This is an indication that the front end is ready (or not) to begin + * doing I/O. Without associated Chardev, do nothing. */ -void qemu_chr_fe_set_open(CharBackend *be, int fe_open); +void qemu_chr_fe_set_open(CharBackend *be, bool is_open); =20 /** * qemu_chr_fe_printf: diff --git a/chardev/char-fe.c b/chardev/char-fe.c index 7789f7be9c8..20222a4cad5 100644 --- a/chardev/char-fe.c +++ b/chardev/char-fe.c @@ -211,7 +211,7 @@ bool qemu_chr_fe_init(CharBackend *b, Chardev *s, Error= **errp) } } =20 - b->fe_open =3D false; + b->fe_is_open =3D false; b->tag =3D tag; b->chr =3D s; return true; @@ -257,7 +257,7 @@ void qemu_chr_fe_set_handlers_full(CharBackend *b, bool sync_state) { Chardev *s; - int fe_open; + bool fe_open; =20 s =3D b->chr; if (!s) { @@ -265,10 +265,10 @@ void qemu_chr_fe_set_handlers_full(CharBackend *b, } =20 if (!opaque && !fd_can_read && !fd_read && !fd_event) { - fe_open =3D 0; + fe_open =3D false; remove_fd_in_watch(s); } else { - fe_open =3D 1; + fe_open =3D true; } b->chr_can_read =3D fd_can_read; b->chr_read =3D fd_read; @@ -336,7 +336,7 @@ void qemu_chr_fe_set_echo(CharBackend *be, bool echo) } } =20 -void qemu_chr_fe_set_open(CharBackend *be, int fe_open) +void qemu_chr_fe_set_open(CharBackend *be, bool is_open) { Chardev *chr =3D be->chr; =20 @@ -344,12 +344,12 @@ void qemu_chr_fe_set_open(CharBackend *be, int fe_ope= n) return; } =20 - if (be->fe_open =3D=3D fe_open) { + if (be->fe_is_open =3D=3D is_open) { return; } - be->fe_open =3D fe_open; + be->fe_is_open =3D is_open; if (CHARDEV_GET_CLASS(chr)->chr_set_fe_open) { - CHARDEV_GET_CLASS(chr)->chr_set_fe_open(chr, fe_open); + CHARDEV_GET_CLASS(chr)->chr_set_fe_open(chr, is_open); } } =20 diff --git a/chardev/char.c b/chardev/char.c index 996a024c7a2..0653b112e92 100644 --- a/chardev/char.c +++ b/chardev/char.c @@ -750,7 +750,7 @@ static int qmp_query_chardev_foreach(Object *obj, void = *data) =20 value->label =3D g_strdup(chr->label); value->filename =3D g_strdup(chr->filename); - value->frontend_open =3D chr->be && chr->be->fe_open; + value->frontend_open =3D chr->be && chr->be->fe_is_open; =20 QAPI_LIST_PREPEND(*list, value); =20 --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH 05/40] qtest: bump min meson timeout to 60 seconds Date: Thu, 21 Dec 2023 10:37:43 +0000 Message-Id: <20231221103818.1633766-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155169918100005 From: Daniel P. Berrang=C3=A9 Even some of the relatively fast qtests can sometimes hit the 30 second timeout in GitLab CI under high parallelism/load conditions. Bump the min to 60 seconds to give a higher margin for reliability. Reviewed-by: Thomas Huth Signed-off-by: Daniel P. Berrang=C3=A9 Message-ID: <20230717182859.707658-2-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-2-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 47dabf91d04..366872ed57b 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -1,12 +1,7 @@ slow_qtests =3D { - 'ahci-test' : 60, 'bios-tables-test' : 120, - 'boot-serial-test' : 60, 'migration-test' : 150, 'npcm7xx_pwm-test': 150, - 'prom-env-test' : 60, - 'pxe-test' : 60, - 'qos-test' : 60, 'qom-test' : 300, 'test-hmp' : 120, } @@ -383,8 +378,8 @@ foreach dir : target_dirs env: qtest_env, args: ['--tap', '-k'], protocol: 'tap', - timeout: slow_qtests.get(test, 30), - priority: slow_qtests.get(test, 30), + timeout: slow_qtests.get(test, 60), + priority: slow_qtests.get(test, 60), suite: ['qtest', 'qtest-' + target_base]) endforeach endforeach --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH 06/40] qtest: bump migration-test timeout to 8 minutes Date: Thu, 21 Dec 2023 10:37:44 +0000 Message-Id: <20231221103818.1633766-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155493558100007 From: Daniel P. Berrang=C3=A9 The migration test should take between 1 min 30 and 2 mins on reasonably modern hardware. The test is not especially compute bound, rather its running time is dominated by the guest RAM size relative to the bandwidth cap, which forces each iteration to take at least 30 seconds. None the less under high load conditions with multiple QEMU processes spawned and competing with other parallel tests, the worst case running time might be somewhat extended. Bumping the timeout to 8 minutes gives us good headroom, while still catching stuck tests relatively quickly. Reviewed-by: Thomas Huth Signed-off-by: Daniel P. Berrang=C3=A9 Message-ID: <20230717182859.707658-3-berrange@redhat.com> [thuth: Bump timeout to 8 minutes to make it work on very loaded systems, t= oo] Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-3-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 366872ed57b..f184d051cfe 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -1,6 +1,6 @@ slow_qtests =3D { 'bios-tables-test' : 120, - 'migration-test' : 150, + 'migration-test' : 480, 'npcm7xx_pwm-test': 150, 'qom-test' : 300, 'test-hmp' : 120, --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH 07/40] qtest: bump qom-test timeout to 15 minutes Date: Thu, 21 Dec 2023 10:37:45 +0000 Message-Id: <20231221103818.1633766-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155338505100001 From: Daniel P. Berrang=C3=A9 The qom-test is periodically hitting the 5 minute timeout when running on the aarch64 emulator under GitLab CI. With an --enable-debug build it can take over 10 minutes for arm/aarch64 targets. Setting timeout to 15 minutes gives enough headroom to hopefully make it reliable. Reviewed-by: Thomas Huth Signed-off-by: Daniel P. Berrang=C3=A9 Message-ID: <20230717182859.707658-4-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-4-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index f184d051cfe..000ac54b7d6 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -2,7 +2,7 @@ slow_qtests =3D { 'bios-tables-test' : 120, 'migration-test' : 480, 'npcm7xx_pwm-test': 150, - 'qom-test' : 300, + 'qom-test' : 900, 'test-hmp' : 120, } =20 --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155230; cv=none; d=zohomail.com; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH 08/40] qtest: bump npcm7xx_pwn-test timeout to 5 minutes Date: Thu, 21 Dec 2023 10:37:46 +0000 Message-Id: <20231221103818.1633766-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155231961100005 From: Daniel P. Berrang=C3=A9 The npcm7xx_pwn-test takes 3 & 1/2 minutes in a --enable-debug build. Bumping to 5 minutes will give more headroom. Signed-off-by: Daniel P. Berrang=C3=A9 Reviewed-by: Thomas Huth Message-ID: <20230717182859.707658-5-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-5-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 000ac54b7d6..84cec0a847d 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -1,7 +1,7 @@ slow_qtests =3D { 'bios-tables-test' : 120, 'migration-test' : 480, - 'npcm7xx_pwm-test': 150, + 'npcm7xx_pwm-test': 300, 'qom-test' : 900, 'test-hmp' : 120, } --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155230; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH 09/40] qtest: bump test-hmp timeout to 4 minutes Date: Thu, 21 Dec 2023 10:37:47 +0000 Message-Id: <20231221103818.1633766-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155232010100006 From: Daniel P. Berrang=C3=A9 The hmp test takes just under 3 minutes in a --enable-debug build. Bumping to 4 minutes will give more headroom. Signed-off-by: Daniel P. Berrang=C3=A9 Reviewed-by: Thomas Huth Message-ID: <20230717182859.707658-6-berrange@redhat.com> [thuth: fix copy-n-paste error in the description] Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-6-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 84cec0a847d..7a4160df046 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -3,7 +3,7 @@ slow_qtests =3D { 'migration-test' : 480, 'npcm7xx_pwm-test': 300, 'qom-test' : 900, - 'test-hmp' : 120, + 'test-hmp' : 240, } =20 qtests_generic =3D [ --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH 10/40] qtest: bump pxe-test timeout to 10 minutes Date: Thu, 21 Dec 2023 10:37:48 +0000 Message-Id: <20231221103818.1633766-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155280285100007 From: Daniel P. Berrang=C3=A9 The pxe-test uses the boot_sector_test() function, and that already uses a timeout of 600 seconds. So adjust the timeout on the meson side accordingly. Signed-off-by: Daniel P. Berrang=C3=A9 [thuth: Bump timeout to 600s and adjust commit description] Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-7-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 7a4160df046..ec93d5a384f 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -4,6 +4,7 @@ slow_qtests =3D { 'npcm7xx_pwm-test': 300, 'qom-test' : 900, 'test-hmp' : 240, + 'pxe-test': 600, } =20 qtests_generic =3D [ --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155345; cv=none; d=zohomail.com; s=zohoarc; b=bf6433K/W75F+wn2ddmUuQhurjq07wHgzGOy9LHvleEiib6ibLd4AHzexxrOK/tr/MvweRYMR+wLL0cu0GBSlR40cGVLraKWvOv7DQw1P2KtEI/00bvBmMFvgmTNzWCfmd+hD3/NzSiWtrK69TYQfRO9Uu07UroBu2BHBdNa3XU= ARC-Message-Signature: i=1; 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Thu, 21 Dec 2023 02:38:30 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH 11/40] qtest: bump prom-env-test timeout to 6 minutes Date: Thu, 21 Dec 2023 10:37:49 +0000 Message-Id: <20231221103818.1633766-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155346641100003 From: Daniel P. Berrang=C3=A9 The prom-env-test can take more than 5 minutes in a --enable-debug build on a loaded system. Bumping to 6 minutes will give more headroom. Signed-off-by: Daniel P. Berrang=C3=A9 [thuth: Bump timeout to 6 minutes instead of 3] Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-8-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index ec93d5a384f..c7944e8dbe9 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -5,6 +5,7 @@ slow_qtests =3D { 'qom-test' : 900, 'test-hmp' : 240, 'pxe-test': 600, + 'prom-env-test': 360, } =20 qtests_generic =3D [ --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155169; cv=none; d=zohomail.com; s=zohoarc; b=nEjYjwRuUyjL8lEQe7Q5SKa8JlnVM5ptNaS8vCCmV5NaIeI2pbhB9kvwI8scY+voJ+O1wCDiASma3SCfkF2fNTTqo5LdkUwuz6u0cxdQSOzPLq+8XBn/AsiQoGKmg3JdRgYf1bPk1AwzSeEw9TYnTl3GCRcXa1oqcFcfhVWUHKM= ARC-Message-Signature: i=1; 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Thu, 21 Dec 2023 02:38:34 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH 12/40] qtest: bump boot-serial-test timeout to 3 minutes Date: Thu, 21 Dec 2023 10:37:50 +0000 Message-Id: <20231221103818.1633766-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155171699100007 From: Daniel P. Berrang=C3=A9 The boot-serial-test takes about 1 + 1/2 minutes in a --enable-debug build. Bumping to 3 minutes will give more headroom. Signed-off-by: Daniel P. Berrang=C3=A9 Reviewed-by: Thomas Huth Message-ID: <20230717182859.707658-9-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-9-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c7944e8dbe9..dc1e6da5c7b 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -6,6 +6,7 @@ slow_qtests =3D { 'test-hmp' : 240, 'pxe-test': 600, 'prom-env-test': 360, + 'boot-serial-test': 180, } =20 qtests_generic =3D [ --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155272; cv=none; d=zohomail.com; s=zohoarc; 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bh=G7uxGZGov81O+5jLuoaBr/C5I/uZZh1/zGx1+p9cIt8=; b=T6CwSQDfbbcusFTvNVDbyIqd0LNAeRNcgAJdGRT1H1wJ8qiTVYPKT+umRxlyjTdUNf KYgTQvEHxWGZd8eG918GXRaTM+xTxSEzZcSINUnbU+L+d7fItZZMLQ59/hVDmRhDH8N1 MksR58ULfqjIE5Zj2IN/jxL3dAQ7FPds9BIGhP33donSG/SC9cEZIHsbydpQTpwVXnQl +Olxt9WPOy4TieT1/OMMLYr82FwQUcgscXk472sCVRnnz02fiASYB/NgSdxd+Dxdbip4 1tKxtUTqPIkP0T9v01o6GmSx5jxeIjlXJ3t3WU0St2zGPnlqYUhOR6AcpVT/EUZPvubj YYMw== X-Gm-Message-State: AOJu0YwpgrxjleVXOH4wsqZ6si7BdMKrjS1felmDqKENshTwm79FcLv1 llE/FDqrJSgT0COYetJjICtY9A== X-Google-Smtp-Source: AGHT+IHDkK7DDkGONkWeeg1etyQrE038hwJH58HJmds12JAmwy22MbScTVnibljXYstd5tpPwiyrKA== X-Received: by 2002:a5d:5385:0:b0:336:6f89:9eca with SMTP id d5-20020a5d5385000000b003366f899ecamr616253wrv.66.1703155111228; Thu, 21 Dec 2023 02:38:31 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH 13/40] qtest: bump qos-test timeout to 2 minutes Date: Thu, 21 Dec 2023 10:37:51 +0000 Message-Id: <20231221103818.1633766-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155274144100001 From: Daniel P. Berrang=C3=A9 The qos-test takes just under 1 minute in a --enable-debug build. Bumping to 2 minutes will give more headroom. Signed-off-by: Daniel P. Berrang=C3=A9 Reviewed-by: Thomas Huth Message-ID: <20230717182859.707658-10-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-10-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index dc1e6da5c7b..b02ca540cff 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -7,6 +7,7 @@ slow_qtests =3D { 'pxe-test': 600, 'prom-env-test': 360, 'boot-serial-test': 180, + 'qos-test': 120, } =20 qtests_generic =3D [ --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155279; cv=none; d=zohomail.com; s=zohoarc; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH 14/40] qtest: bump aspeed_smc-test timeout to 6 minutes Date: Thu, 21 Dec 2023 10:37:52 +0000 Message-Id: <20231221103818.1633766-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155280318100009 From: Daniel P. Berrang=C3=A9 On a loaded system with --enable-debug, this test can take longer than 5 minutes. Raising the timeout to 6 minutes gives greater headroom for such situations. Signed-off-by: Daniel P. Berrang=C3=A9 [thuth: Increase the timeout to 6 minutes for very loaded systems] Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-11-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index b02ca540cff..da53dd66c97 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -1,4 +1,5 @@ slow_qtests =3D { + 'aspeed_smc-test': 360, 'bios-tables-test' : 120, 'migration-test' : 480, 'npcm7xx_pwm-test': 300, --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155183; cv=none; d=zohomail.com; s=zohoarc; b=Gew3CNoRl0Uvy84SPdnQEy8ycru1JXUiAcEbxLYqlZ9RHfDBEw4m5rxZoL0MZ9nIToV4rhnYqzRgKgjkumt0fMHmgQz/RMjZvCtCLuA1GygPdTuMhzWry20NiH8WwVi8KZYMRd0VrcMlWbS8LFPek1vwplGIUZugDNGlBA3Rijs= ARC-Message-Signature: i=1; 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Thu, 21 Dec 2023 02:38:33 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH 15/40] qtest: bump bios-table-test timeout to 9 minutes Date: Thu, 21 Dec 2023 10:37:53 +0000 Message-Id: <20231221103818.1633766-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155185791100005 From: Daniel P. Berrang=C3=A9 This is reliably hitting the current 2 minute timeout in GitLab CI, and for the TCI job, it even hits a 6 minute timeout. Reviewed-by: Thomas Huth Signed-off-by: Daniel P. Berrang=C3=A9 Message-ID: <20230717182859.707658-12-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-12-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index da53dd66c97..6e8d00d53cb 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -1,6 +1,6 @@ slow_qtests =3D { 'aspeed_smc-test': 360, - 'bios-tables-test' : 120, + 'bios-tables-test' : 540, 'migration-test' : 480, 'npcm7xx_pwm-test': 300, 'qom-test' : 900, --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155911; cv=none; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng Subject: [PATCH 16/40] tests/qtest: Bump the device-introspect-test timeout to 12 minutes Date: Thu, 21 Dec 2023 10:37:54 +0000 Message-Id: <20231221103818.1633766-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155913851100003 From: Thomas Huth When running the test in slow mode on a very loaded system with the arm/aarch64 target and with --enable-debug, it can take longer than 10 minutes to finish the introspection test. Bump the timeout to twelve minutes to make sure that it also finishes in such situations. Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-13-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 6e8d00d53cb..16916ae857b 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -1,6 +1,7 @@ slow_qtests =3D { 'aspeed_smc-test': 360, 'bios-tables-test' : 540, + 'device-introspect-test' : 720, 'migration-test' : 480, 'npcm7xx_pwm-test': 300, 'qom-test' : 900, --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155904; cv=none; d=zohomail.com; s=zohoarc; b=nKROdXab3VF+eWlBV6Sq1qC9KeSYg4kg6UQXTclFGRbZi1nETeTbeL5T3qgOX5iEplOJiOfM4si2nat5BMlFu6exv2cKdoURmrigtXiEQj9U3eHchPv2zEZPgm8jSceIU14IWlpcSfak3ApN62Bwm7Io/INzAUm2YmFkwe0iqnA= ARC-Message-Signature: i=1; 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Thu, 21 Dec 2023 02:47:04 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng Subject: [PATCH 17/40] tests/unit: Bump test-aio-multithread test timeout to 2 minutes Date: Thu, 21 Dec 2023 10:37:55 +0000 Message-Id: <20231221103818.1633766-18-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155905865100001 From: Thomas Huth When running the tests in slow mode on a very loaded system and with --enable-debug, the test-aio-multithread can take longer than 1 minute. Bump the timeout to two minutes to make sure that it also passes in such situations. Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-14-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/unit/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/unit/meson.build b/tests/unit/meson.build index a05d4710904..0b0c7c14115 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -172,6 +172,7 @@ test_env.set('G_TEST_SRCDIR', meson.current_source_dir(= )) test_env.set('G_TEST_BUILDDIR', meson.current_build_dir()) =20 slow_tests =3D { + 'test-aio-multithread' : 120, 'test-crypto-tlscredsx509': 45, 'test-crypto-tlssession': 45 } --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703156174; cv=none; d=zohomail.com; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng Subject: [PATCH 18/40] tests/unit: Bump test-crypto-block test timeout to 5 minutes Date: Thu, 21 Dec 2023 10:37:56 +0000 Message-Id: <20231221103818.1633766-19-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703156175453100001 From: Thomas Huth When running the tests in slow mode on a very loaded system and with --enable-debug, the test-crypto-block can take longer than 4 minutes. Bump the timeout to 5 minutes to make sure that it also passes in such situations. Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-15-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/unit/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/unit/meson.build b/tests/unit/meson.build index 0b0c7c14115..a99dec43120 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -173,6 +173,7 @@ test_env.set('G_TEST_BUILDDIR', meson.current_build_dir= ()) =20 slow_tests =3D { 'test-aio-multithread' : 120, + 'test-crypto-block' : 300, 'test-crypto-tlscredsx509': 45, 'test-crypto-tlssession': 45 } --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155353; cv=none; d=zohomail.com; s=zohoarc; b=kYqoO4mPyB+nDFucCsCIxVpyzOq3auSuZFwdgHYrqGQhmuXOFVQyesnW3vyi06KHWicUcO7LYJeN6eDYEeGY2/XJOhH21rGjXN7F0JA6jqavdkzBdHfcbXobAszVjE0/qZ/yY7ncMgHreraboAPcSipObQ1biK8tnI7kLO/TGIs= ARC-Message-Signature: i=1; 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Thu, 21 Dec 2023 02:38:33 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng Subject: [PATCH 19/40] tests/fp: Bump fp-test-mulAdd test timeout to 3 minutes Date: Thu, 21 Dec 2023 10:37:57 +0000 Message-Id: <20231221103818.1633766-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155354811100003 From: Thomas Huth When running the tests in slow mode with --enable-debug on a very loaded system, the fp-test-mulAdd test can take longer than 2 minutes. Bump the timeout to three minutes to make sure it passes in such situations, too. Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-16-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- tests/fp/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/fp/meson.build b/tests/fp/meson.build index cbc17392d67..3b7fc637499 100644 --- a/tests/fp/meson.build +++ b/tests/fp/meson.build @@ -124,7 +124,7 @@ test('fp-test-mulAdd', fptest, # no fptest_rounding_args args: fptest_args + ['f16_mulAdd', 'f32_mulAdd', 'f64_mulAdd', 'f128_mulAdd'], - suite: ['softfloat-slow', 'softfloat-ops-slow', 'slow'], timeout: 90) + suite: ['softfloat-slow', 'softfloat-ops-slow', 'slow'], timeout: 180) =20 executable( 'fp-bench', --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH 20/40] mtest2make: stop disabling meson test timeouts Date: Thu, 21 Dec 2023 10:37:58 +0000 Message-Id: <20231221103818.1633766-21-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155865502100001 From: Daniel P. Berrang=C3=A9 The mtest2make.py script passes the arg '-t 0' to 'meson test' which disables all test timeouts. This is a major source of pain when running in GitLab CI and a test gets stuck. It will stall until GitLab kills the CI job. This leaves us with little easily consumable information about the stalled test. The TAP format doesn't show the test name until it is completed, and TAP output from multiple tests it interleaved. So we have to analyse the log to figure out what tests had un-finished TAP output present and thus infer which test case caused the hang. This is very time consuming and error prone. By allowing meson to kill stalled tests, we get a direct display of what test program got stuck, which lets us more directly focus in on what specific test case within the test program hung. The other issue with disabling meson test timeouts by default is that it makes it more likely that maintainers inadvertantly introduce slowdowns. For example the recent-ish change that accidentally made migrate-test take 15-20 minutes instead of around 1 minute. The main risk of this change is that the individual test timeouts might be too short to allow completion in high load scenarios. Thus, there is likely to be some short term pain where we have to bump the timeouts for certain tests to make them reliable enough. The preceeding few patches raised the timeouts for all failures that were immediately apparent in GitLab CI. Even with the possible short term instability, this should still be a net win for debuggability of failed CI pipelines over the long term. Signed-off-by: Daniel P. Berrang=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20230717182859.707658-13-berrange@redhat.com> Signed-off-by: Thomas Huth Message-Id: <20231215070357.10888-17-thuth@redhat.com> Signed-off-by: Alex Benn=C3=A9e --- scripts/mtest2make.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/mtest2make.py b/scripts/mtest2make.py index 179dd548718..eb01a05ddbd 100644 --- a/scripts/mtest2make.py +++ b/scripts/mtest2make.py @@ -27,7 +27,8 @@ def names(self, base): .speed.slow =3D $(foreach s,$(sort $(filter-out %-thorough, $1)), --suite = $s) .speed.thorough =3D $(foreach s,$(sort $1), --suite $s) =20 -.mtestargs =3D --no-rebuild -t 0 +TIMEOUT_MULTIPLIER =3D 1 +.mtestargs =3D --no-rebuild -t $(TIMEOUT_MULTIPLIER) ifneq ($(SPEED), quick) .mtestargs +=3D --setup $(SPEED) endif --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 21/40] hw/riscv: Use misa_mxl instead of misa_mxl_max Date: Thu, 21 Dec 2023 10:37:59 +0000 Message-Id: <20231221103818.1633766-22-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155831683100001 From: Akihiko Odaki The effective MXL value matters when booting. Signed-off-by: Akihiko Odaki Message-Id: <20231213-riscv-v7-1-a760156a337f@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- hw/riscv/boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 0ffca05189f..bc67c0bd189 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -36,7 +36,7 @@ =20 bool riscv_is_32bit(RISCVHartArrayState *harts) { - return harts->harts[0].env.misa_mxl_max =3D=3D MXL_RV32; + return harts->harts[0].env.misa_mxl =3D=3D MXL_RV32; } =20 /* --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155764; cv=none; d=zohomail.com; s=zohoarc; b=Z+154l16m/PB9KOZKcOStIB6iGyKfsxOfxX6Ea9WmzQWJfwXNP+12o550T0zjeB7aU6igujkgOC2TXyWoiEo0lU6UCrUmM7ovIzEeuMK/ozBqOcdNuzPb91TMP7cR7DuSm6k0hoLs3YrygQt3MuGOWMbgwGFQABAyDT//Hwa5Kc= ARC-Message-Signature: i=1; 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Thu, 21 Dec 2023 02:46:59 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 22/40] target/riscv: Remove misa_mxl validation Date: Thu, 21 Dec 2023 10:38:00 +0000 Message-Id: <20231221103818.1633766-23-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155764974100001 From: Akihiko Odaki It is initialized with a simple assignment and there is little room for error. In fact, the validation is even more complex. Signed-off-by: Akihiko Odaki Acked-by: LIU Zhiwei Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Message-Id: <20231213-riscv-v7-2-a760156a337f@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- target/riscv/tcg/tcg-cpu.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8a35683a345..ee17f65afb6 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -148,7 +148,7 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState = *env, Error **errp) } } =20 -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); CPUClass *cc =3D CPU_CLASS(mcc); @@ -168,11 +168,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu,= Error **errp) default: g_assert_not_reached(); } - - if (env->misa_mxl_max !=3D env->misa_mxl) { - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); - return; - } } =20 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) @@ -673,7 +668,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) static bool tcg_cpu_realize(CPUState *cs, Error **errp) { RISCVCPU *cpu =3D RISCV_CPU(cs); - Error *local_err =3D NULL; =20 if (!riscv_cpu_tcg_compatible(cpu)) { g_autofree char *name =3D riscv_cpu_get_name(cpu); @@ -682,14 +676,11 @@ static bool tcg_cpu_realize(CPUState *cs, Error **err= p) return false; } =20 - riscv_cpu_validate_misa_mxl(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return false; - } + riscv_cpu_validate_misa_mxl(cpu); =20 #ifndef CONFIG_USER_ONLY CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; =20 CPU(cs)->tcg_cflags |=3D CF_PCREL; =20 --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 23/40] target/riscv: Move misa_mxl_max to class Date: Thu, 21 Dec 2023 10:38:01 +0000 Message-Id: <20231221103818.1633766-24-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155738906100003 From: Akihiko Odaki misa_mxl_max is common for all instances of a RISC-V CPU class so they are better put into class. Signed-off-by: Akihiko Odaki Message-Id: <20231213-riscv-v7-3-a760156a337f@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- target/riscv/cpu.h | 4 +- target/riscv/cpu.c | 118 +++++++++++++++++++------------------ target/riscv/gdbstub.c | 12 ++-- target/riscv/kvm/kvm-cpu.c | 10 ++-- target/riscv/machine.c | 7 +-- target/riscv/tcg/tcg-cpu.c | 12 ++-- target/riscv/translate.c | 3 +- 7 files changed, 87 insertions(+), 79 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361be64..060b7f69a74 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -169,7 +169,6 @@ struct CPUArchState { =20 /* RISCVMXL, but uint32_t for vmstate migration */ uint32_t misa_mxl; /* current mxl */ - uint32_t misa_mxl_max; /* max mxl for this cpu */ uint32_t misa_ext; /* current extensions */ uint32_t misa_ext_mask; /* max ext for this cpu */ uint32_t xl; /* current xlen */ @@ -450,6 +449,7 @@ struct RISCVCPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; + uint32_t misa_mxl_max; /* max mxl for this cpu */ }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) @@ -756,7 +756,7 @@ enum riscv_pmu_event_idx { /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); -void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); +void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); =20 typedef struct RISCVCPUMultiExtConfig { const char *name; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 83c7c0cf07b..2ab61df2217 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -274,9 +274,8 @@ const char *riscv_cpu_get_trap_name(target_ulong cause,= bool async) } } =20 -void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext) { - env->misa_mxl_max =3D env->misa_mxl =3D mxl; env->misa_ext_mask =3D env->misa_ext =3D ext; } =20 @@ -378,11 +377,7 @@ static void riscv_any_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; -#if defined(TARGET_RISCV32) - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | = RVU); -#elif defined(TARGET_RISCV64) - riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | = RVU); -#endif + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU); =20 #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), @@ -403,16 +398,14 @@ static void riscv_max_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - RISCVMXL mlx =3D MXL_RV64; =20 -#ifdef TARGET_RISCV32 - mlx =3D MXL_RV32; -#endif - riscv_cpu_set_misa(env, mlx, 0); env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), mlx =3D=3D MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); +#ifdef TARGET_RISCV32 + set_satp_mode_max_supported(cpu, VM_1_10_SV32); +#else + set_satp_mode_max_supported(cpu, VM_1_10_SV57); +#endif #endif } =20 @@ -420,8 +413,6 @@ static void riscv_max_cpu_init(Object *obj) static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV64, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -433,8 +424,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - riscv_cpu_set_misa(env, MXL_RV64, - RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | = RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -452,7 +442,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -469,7 +459,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_11_0; =20 cpu->cfg.ext_zfa =3D true; @@ -500,7 +490,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); env->priv_ver =3D PRIV_VERSION_1_12_0; =20 /* Enable ISA extensions */ @@ -544,8 +534,6 @@ static void rv128_base_cpu_init(Object *obj) exit(EXIT_FAILURE); } CPURISCVState *env =3D &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV128, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -556,8 +544,6 @@ static void rv128_base_cpu_init(Object *obj) static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV32, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -569,8 +555,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - riscv_cpu_set_misa(env, MXL_RV32, - RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | = RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -588,7 +573,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -605,7 +590,7 @@ static void rv32_ibex_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -622,7 +607,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -845,7 +830,7 @@ static void riscv_cpu_reset_hold(Object *obj) mcc->parent_phases.hold(obj); } #ifndef CONFIG_USER_ONLY - env->misa_mxl =3D env->misa_mxl_max; + env->misa_mxl =3D mcc->misa_mxl_max; env->priv =3D PRV_M; env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); if (env->misa_mxl > MXL_RV32) { @@ -1213,6 +1198,12 @@ static void riscv_cpu_post_init(Object *obj) =20 static void riscv_cpu_init(Object *obj) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + + env->misa_mxl =3D mcc->misa_mxl_max; + #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); @@ -1657,7 +1648,7 @@ static void cpu_get_marchid(Object *obj, Visitor *v, = const char *name, visit_type_bool(v, name, &value, errp); } =20 -static void riscv_cpu_class_init(ObjectClass *c, void *data) +static void riscv_cpu_common_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); CPUClass *cc =3D CPU_CLASS(c); @@ -1699,6 +1690,13 @@ static void riscv_cpu_class_init(ObjectClass *c, voi= d *data) device_class_set_props(dc, riscv_cpu_properties); } =20 +static void riscv_cpu_class_init(ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + + mcc->misa_mxl_max =3D (uint32_t)(uintptr_t)data; +} + static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) { @@ -1764,18 +1762,22 @@ void riscv_cpu_list(void) g_slist_free(list); } =20 -#define DEFINE_CPU(type_name, initfn) \ - { \ - .name =3D type_name, \ - .parent =3D TYPE_RISCV_CPU, \ - .instance_init =3D initfn \ +#define DEFINE_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name =3D (type_name), \ + .parent =3D TYPE_RISCV_CPU, \ + .instance_init =3D (initfn), \ + .class_init =3D riscv_cpu_class_init, \ + .class_data =3D (void *)(misa_mxl_max) \ } =20 -#define DEFINE_DYNAMIC_CPU(type_name, initfn) \ - { \ - .name =3D type_name, \ - .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ - .instance_init =3D initfn \ +#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name =3D (type_name), \ + .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ + .instance_init =3D (initfn), \ + .class_init =3D riscv_cpu_class_init, \ + .class_data =3D (void *)(misa_mxl_max) \ } =20 static const TypeInfo riscv_cpu_type_infos[] =3D { @@ -1788,29 +1790,31 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .instance_post_init =3D riscv_cpu_post_init, .abstract =3D true, .class_size =3D sizeof(RISCVCPUClass), - .class_init =3D riscv_cpu_class_init, + .class_init =3D riscv_cpu_common_class_init, }, { .name =3D TYPE_RISCV_DYNAMIC_CPU, .parent =3D TYPE_RISCV_CPU, .abstract =3D true, }, - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32, riscv_any_cpu_in= it), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_in= it), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cp= u_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nomm= u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cp= u_init), #elif defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_in= it), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_in= it), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cp= u_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cp= u_init), + DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cp= u_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_= cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_c= pu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_i= nit), #endif }; =20 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 58b3ace0fe9..365040228a1 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -49,6 +49,7 @@ static const struct TypeSize vec_lanes[] =3D { =20 int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; target_ulong tmp; @@ -61,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) return 0; } =20 - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: return gdb_get_reg32(mem_buf, tmp); case MXL_RV64: @@ -75,12 +76,13 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) =20 int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; int length =3D 0; target_ulong tmp; =20 - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: tmp =3D (int32_t)ldl_p(mem_buf); length =3D 4; @@ -214,11 +216,12 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, u= int8_t *mem_buf, int n) =20 static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; GString *s =3D g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize =3D 16 << env->misa_mxl_max; + int bitsize =3D 16 << mcc->misa_mxl_max; int i; =20 #if !defined(CONFIG_USER_ONLY) @@ -310,6 +313,7 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, i= nt base_reg) =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; if (env->misa_ext & RVD) { @@ -326,7 +330,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) ricsv_gen_dynamic_vector_xml(cs, base_reg= ), "riscv-vector.xml", 0); } - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 45b6cf1cfa0..f5624e553b6 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1501,14 +1501,14 @@ static void kvm_cpu_accel_register_types(void) } type_init(kvm_cpu_accel_register_types); =20 -static void riscv_host_cpu_init(Object *obj) +static void riscv_host_cpu_class_init(ObjectClass *c, void *data) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); =20 #if defined(TARGET_RISCV32) - env->misa_mxl_max =3D env->misa_mxl =3D MXL_RV32; + mcc->misa_mxl_max =3D MXL_RV32; #elif defined(TARGET_RISCV64) - env->misa_mxl_max =3D env->misa_mxl =3D MXL_RV64; + mcc->misa_mxl_max =3D MXL_RV64; #endif } =20 @@ -1516,7 +1516,7 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU_HOST, .parent =3D TYPE_RISCV_CPU, - .instance_init =3D riscv_host_cpu_init, + .class_init =3D riscv_host_cpu_class_init, } }; =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index fdde243e040..4c8d9a66595 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -178,10 +178,9 @@ static const VMStateDescription vmstate_pointermasking= =3D { =20 static bool rv128_needed(void *opaque) { - RISCVCPU *cpu =3D opaque; - CPURISCVState *env =3D &cpu->env; + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(opaque); =20 - return env->misa_mxl_max =3D=3D MXL_RV128; + return mcc->misa_mxl_max =3D=3D MXL_RV128; } =20 static const VMStateDescription vmstate_rv128 =3D { @@ -372,7 +371,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.vext_ver, RISCVCPU), VMSTATE_UINT32(env.misa_mxl, RISCVCPU), VMSTATE_UINT32(env.misa_ext, RISCVCPU), - VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), + VMSTATE_UNUSED(4), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_BOOL(env.virt_enabled, RISCVCPU), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ee17f65afb6..7f6712c81a4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -152,10 +152,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); CPUClass *cc =3D CPU_CLASS(mcc); - CPURISCVState *env =3D &cpu->env; =20 /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { #ifdef TARGET_RISCV64 case MXL_RV64: case MXL_RV128: @@ -274,6 +273,7 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVC= PU *cpu) */ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 @@ -454,7 +454,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } } @@ -462,7 +462,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } if (riscv_has_ext(env, RVD)) { @@ -470,7 +470,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) } } =20 - if (env->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { + if (mcc->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension is only relevant to RV32"); return; } @@ -956,7 +956,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) const RISCVCPUMultiExtConfig *prop; =20 /* Enable RVG, RVJ and RVV that are disabled by default */ - riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV= ); + riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { isa_ext_update_enabled(cpu, prop->offset, true); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f0be79bb160..7e383c5eebf 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1167,6 +1167,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPURISCVState *env =3D cpu_env(cs); + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); uint32_t tb_flags =3D ctx->base.tb->flags; =20 @@ -1188,7 +1189,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->cfg_vta_all_1s =3D cpu->cfg.rvv_ta_all_1s; ctx->vstart_eq_zero =3D FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); - ctx->misa_mxl_max =3D env->misa_mxl_max; + ctx->misa_mxl_max =3D mcc->misa_mxl_max; ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 24/40] target/riscv: Validate misa_mxl_max only once Date: Thu, 21 Dec 2023 10:38:02 +0000 Message-Id: <20231221103818.1633766-25-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155750873100005 From: Akihiko Odaki misa_mxl_max is now a class member and initialized only once for each class. This also moves the initialization of gdb_core_xml_file which will be referenced before realization in the future. Signed-off-by: Akihiko Odaki Message-Id: <20231213-riscv-v7-4-a760156a337f@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- target/riscv/cpu.c | 21 +++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 23 ----------------------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2ab61df2217..b799f133604 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1247,6 +1247,26 @@ static const MISAExtInfo misa_ext_info_arr[] =3D { MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), }; =20 +static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc) +{ + CPUClass *cc =3D CPU_CLASS(mcc); + + /* Validate that MISA_MXL is set properly. */ + switch (mcc->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } +} + static int riscv_validate_misa_info_idx(uint32_t bit) { int idx; @@ -1695,6 +1715,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); =20 mcc->misa_mxl_max =3D (uint32_t)(uintptr_t)data; + riscv_cpu_validate_misa_mxl(mcc); } =20 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 7f6712c81a4..eb243e011ca 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -148,27 +148,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState= *env, Error **errp) } } =20 -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); - CPUClass *cc =3D CPU_CLASS(mcc); - - /* Validate that MISA_MXL is set properly. */ - switch (mcc->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } -} - static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; @@ -676,8 +655,6 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) return false; } =20 - riscv_cpu_validate_misa_mxl(cpu); - #ifndef CONFIG_USER_ONLY CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155748; cv=none; d=zohomail.com; s=zohoarc; b=S0arzAscip6nrp11DF5BDu4Ux5ZRiHydxA7WGGhEgjt6izqcH8jmZQYBEMwYnm6gvHUEWHwzU7nyYPS0GpwiL5DHJVJHQz9vw52hkWSbUV77S5VKhDmw6u+/3JpMYbIOyRo4nnfxL27JswlByNhxhGYvszTSE2I6oBr9E5XsHGA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Thu, 21 Dec 2023 02:47:01 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 25/40] target/arm: Use GDBFeature for dynamic XML Date: Thu, 21 Dec 2023 10:38:03 +0000 Message-Id: <20231221103818.1633766-26-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155750879100006 From: Akihiko Odaki In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Acked-by: Richard Henderson Message-Id: <20231213-gdb-v17-1-777047380591@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 21 +++--- target/arm/internals.h | 2 +- target/arm/gdbstub.c | 142 ++++++++++++++++++++--------------------- target/arm/gdbstub64.c | 95 +++++++++++++-------------- 4 files changed, 123 insertions(+), 137 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a0282e0d281..b2f8ac81f06 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -25,6 +25,7 @@ #include "hw/registerfields.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/gdbstub.h" #include "qapi/qapi-types-common.h" =20 /* ARM processors have a weak memory model */ @@ -136,23 +137,21 @@ enum { */ =20 /** - * DynamicGDBXMLInfo: - * @desc: Contains the XML descriptions. - * @num: Number of the registers in this XML seen by GDB. + * DynamicGDBFeatureInfo: + * @desc: Contains the feature descriptions. * @data: A union with data specific to the set of registers * @cpregs_keys: Array that contains the corresponding Key of * a given cpreg with the same order of the cpreg * in the XML description. */ -typedef struct DynamicGDBXMLInfo { - char *desc; - int num; +typedef struct DynamicGDBFeatureInfo { + GDBFeature desc; union { struct { uint32_t *keys; } cpregs; } data; -} DynamicGDBXMLInfo; +} DynamicGDBFeatureInfo; =20 /* CPU state for each instance of a generic timer (in cp15 c14) */ typedef struct ARMGenericTimer { @@ -878,10 +877,10 @@ struct ArchCPU { uint64_t *cpreg_vmstate_values; int32_t cpreg_vmstate_array_len; =20 - DynamicGDBXMLInfo dyn_sysreg_xml; - DynamicGDBXMLInfo dyn_svereg_xml; - DynamicGDBXMLInfo dyn_m_systemreg_xml; - DynamicGDBXMLInfo dyn_m_secextreg_xml; + DynamicGDBFeatureInfo dyn_sysreg_feature; + DynamicGDBFeatureInfo dyn_svereg_feature; + DynamicGDBFeatureInfo dyn_m_systemreg_feature; + DynamicGDBFeatureInfo dyn_m_secextreg_feature; =20 /* Timers used by the generic (architected) timer */ QEMUTimer *gt_timer[NUM_GTIMERS]; diff --git a/target/arm/internals.h b/target/arm/internals.h index 143d57c0fe4..1136710741f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1446,7 +1446,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *= env) } =20 #ifdef TARGET_AARCH64 -int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg); +GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 28f546a5ff9..5949adfb31a 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -26,11 +26,11 @@ #include "cpu-features.h" #include "cpregs.h" =20 -typedef struct RegisterSysregXmlParam { +typedef struct RegisterSysregFeatureParam { CPUState *cs; - GString *s; + GDBFeatureBuilder builder; int n; -} RegisterSysregXmlParam; +} RegisterSysregFeatureParam; =20 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect whatever the target description contains. Due to a historical mishap @@ -216,7 +216,7 @@ static int arm_gdb_get_sysreg(CPUARMState *env, GByteAr= ray *buf, int reg) const ARMCPRegInfo *ri; uint32_t key; =20 - key =3D cpu->dyn_sysreg_xml.data.cpregs.keys[reg]; + key =3D cpu->dyn_sysreg_feature.data.cpregs.keys[reg]; ri =3D get_arm_cp_reginfo(cpu->cp_regs, key); if (ri) { if (cpreg_field_is_64bit(ri)) { @@ -233,34 +233,32 @@ static int arm_gdb_set_sysreg(CPUARMState *env, uint8= _t *buf, int reg) return 0; } =20 -static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_= xml, +static void arm_gen_one_feature_sysreg(GDBFeatureBuilder *builder, + DynamicGDBFeatureInfo *dyn_feature, ARMCPRegInfo *ri, uint32_t ri_key, - int bitsize, int regnum) + int bitsize, int n) { - g_string_append_printf(s, "name); - g_string_append_printf(s, " bitsize=3D\"%d\"", bitsize); - g_string_append_printf(s, " regnum=3D\"%d\"", regnum); - g_string_append_printf(s, " group=3D\"cp_regs\"/>"); - dyn_xml->data.cpregs.keys[dyn_xml->num] =3D ri_key; - dyn_xml->num++; + gdb_feature_builder_append_reg(builder, ri->name, bitsize, n, + "int", "cp_regs"); + + dyn_feature->data.cpregs.keys[n] =3D ri_key; } =20 -static void arm_register_sysreg_for_xml(gpointer key, gpointer value, - gpointer p) +static void arm_register_sysreg_for_feature(gpointer key, gpointer value, + gpointer p) { uint32_t ri_key =3D (uintptr_t)key; ARMCPRegInfo *ri =3D value; - RegisterSysregXmlParam *param =3D (RegisterSysregXmlParam *)p; - GString *s =3D param->s; + RegisterSysregFeatureParam *param =3D p; ARMCPU *cpu =3D ARM_CPU(param->cs); CPUARMState *env =3D &cpu->env; - DynamicGDBXMLInfo *dyn_xml =3D &cpu->dyn_sysreg_xml; + DynamicGDBFeatureInfo *dyn_feature =3D &cpu->dyn_sysreg_feature; =20 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) { if (arm_feature(env, ARM_FEATURE_AARCH64)) { if (ri->state =3D=3D ARM_CP_STATE_AA64) { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64, - param->n++); + arm_gen_one_feature_sysreg(¶m->builder, dyn_feature, + ri, ri_key, 64, param->n++); } } else { if (ri->state =3D=3D ARM_CP_STATE_AA32) { @@ -269,32 +267,32 @@ static void arm_register_sysreg_for_xml(gpointer key,= gpointer value, return; } if (ri->type & ARM_CP_64BIT) { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64, - param->n++); + arm_gen_one_feature_sysreg(¶m->builder, dyn_featur= e, + ri, ri_key, 64, param->n++); } else { - arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32, - param->n++); + arm_gen_one_feature_sysreg(¶m->builder, dyn_featur= e, + ri, ri_key, 32, param->n++); } } } } } =20 -static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) +static GDBFeature *arm_gen_dynamic_sysreg_feature(CPUState *cs, int base_r= eg) { ARMCPU *cpu =3D ARM_CPU(cs); - GString *s =3D g_string_new(NULL); - RegisterSysregXmlParam param =3D {cs, s, base_reg}; - - cpu->dyn_sysreg_xml.num =3D 0; - cpu->dyn_sysreg_xml.data.cpregs.keys =3D g_new(uint32_t, g_hash_table_= size(cpu->cp_regs)); - g_string_printf(s, ""); - g_string_append_printf(s, "= "); - g_string_append_printf(s, ""); - g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, ¶m= ); - g_string_append_printf(s, ""); - cpu->dyn_sysreg_xml.desc =3D g_string_free(s, false); - return cpu->dyn_sysreg_xml.num; + RegisterSysregFeatureParam param =3D {cs}; + gsize num_regs =3D g_hash_table_size(cpu->cp_regs); + + gdb_feature_builder_init(¶m.builder, + &cpu->dyn_sysreg_feature.desc, + "org.qemu.gdb.arm.sys.regs", + "system-registers.xml", + base_reg); + cpu->dyn_sysreg_feature.data.cpregs.keys =3D g_new(uint32_t, num_regs); + g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_feature, &p= aram); + gdb_feature_builder_end(¶m.builder); + return &cpu->dyn_sysreg_feature.desc; } =20 #ifdef CONFIG_TCG @@ -386,31 +384,29 @@ static int arm_gdb_set_m_systemreg(CPUARMState *env, = uint8_t *buf, int reg) return 0; /* TODO */ } =20 -static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg) +static GDBFeature *arm_gen_dynamic_m_systemreg_feature(CPUState *cs, + int base_reg) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - GString *s =3D g_string_new(NULL); - int base_reg =3D orig_base_reg; + GDBFeatureBuilder builder; + int reg =3D 0; int i; =20 - g_string_printf(s, ""); - g_string_append_printf(s, "= "); - g_string_append_printf(s, "\n"); + gdb_feature_builder_init(&builder, &cpu->dyn_m_systemreg_feature.desc, + "org.gnu.gdb.arm.m-system", "arm-m-system.xml= ", + base_reg); =20 for (i =3D 0; i < ARRAY_SIZE(m_sysreg_def); i++) { if (arm_feature(env, m_sysreg_def[i].feature)) { - g_string_append_printf(s, - "\n", - m_sysreg_def[i].name, base_reg++); + gdb_feature_builder_append_reg(&builder, m_sysreg_def[i].name,= 32, + reg++, "int", NULL); } } =20 - g_string_append_printf(s, ""); - cpu->dyn_m_systemreg_xml.desc =3D g_string_free(s, false); - cpu->dyn_m_systemreg_xml.num =3D base_reg - orig_base_reg; + gdb_feature_builder_end(&builder); =20 - return cpu->dyn_m_systemreg_xml.num; + return &cpu->dyn_m_systemreg_feature.desc; } =20 #ifndef CONFIG_USER_ONLY @@ -428,31 +424,31 @@ static int arm_gdb_set_m_secextreg(CPUARMState *env, = uint8_t *buf, int reg) return 0; /* TODO */ } =20 -static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg) +static GDBFeature *arm_gen_dynamic_m_secextreg_feature(CPUState *cs, + int base_reg) { ARMCPU *cpu =3D ARM_CPU(cs); - GString *s =3D g_string_new(NULL); - int base_reg =3D orig_base_reg; + GDBFeatureBuilder builder; + char *name; + int reg =3D 0; int i; =20 - g_string_printf(s, ""); - g_string_append_printf(s, "= "); - g_string_append_printf(s, "= \n"); + gdb_feature_builder_init(&builder, &cpu->dyn_m_secextreg_feature.desc, + "org.gnu.gdb.arm.secext", "arm-m-secext.xml", + base_reg); =20 for (i =3D 0; i < ARRAY_SIZE(m_sysreg_def); i++) { - g_string_append_printf(s, - "\n", - m_sysreg_def[i].name, base_reg++); - g_string_append_printf(s, - "\n", - m_sysreg_def[i].name, base_reg++); + name =3D g_strconcat(m_sysreg_def[i].name, "_ns", NULL); + gdb_feature_builder_append_reg(&builder, name, 32, reg++, + "int", NULL); + name =3D g_strconcat(m_sysreg_def[i].name, "_s", NULL); + gdb_feature_builder_append_reg(&builder, name, 32, reg++, + "int", NULL); } =20 - g_string_append_printf(s, ""); - cpu->dyn_m_secextreg_xml.desc =3D g_string_free(s, false); - cpu->dyn_m_secextreg_xml.num =3D base_reg - orig_base_reg; + gdb_feature_builder_end(&builder); =20 - return cpu->dyn_m_secextreg_xml.num; + return &cpu->dyn_m_secextreg_feature.desc; } #endif #endif /* CONFIG_TCG */ @@ -462,14 +458,14 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, con= st char *xmlname) ARMCPU *cpu =3D ARM_CPU(cs); =20 if (strcmp(xmlname, "system-registers.xml") =3D=3D 0) { - return cpu->dyn_sysreg_xml.desc; + return cpu->dyn_sysreg_feature.desc.xml; } else if (strcmp(xmlname, "sve-registers.xml") =3D=3D 0) { - return cpu->dyn_svereg_xml.desc; + return cpu->dyn_svereg_feature.desc.xml; } else if (strcmp(xmlname, "arm-m-system.xml") =3D=3D 0) { - return cpu->dyn_m_systemreg_xml.desc; + return cpu->dyn_m_systemreg_feature.desc.xml; #ifndef CONFIG_USER_ONLY } else if (strcmp(xmlname, "arm-m-secext.xml") =3D=3D 0) { - return cpu->dyn_m_secextreg_xml.desc; + return cpu->dyn_m_secextreg_feature.desc.xml; #endif } return NULL; @@ -487,7 +483,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) */ #ifdef TARGET_AARCH64 if (isar_feature_aa64_sve(&cpu->isar)) { - int nreg =3D arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs); + int nreg =3D arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_re= gs)->num_regs; gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, aarch64_gdb_set_sve_reg, nreg, "sve-registers.xml", 0); @@ -533,20 +529,20 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) 1, "arm-m-profile-mve.xml", 0); } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_re= gs), + arm_gen_dynamic_sysreg_feature(cs, cs->gdb_nu= m_regs)->num_regs, "system-registers.xml", 0); =20 #ifdef CONFIG_TCG if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { gdb_register_coprocessor(cs, arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, - arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs), + arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs)->num= _regs, "arm-m-system.xml", 0); #ifndef CONFIG_USER_ONLY if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { gdb_register_coprocessor(cs, arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg, - arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs), + arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs)-= >num_regs, "arm-m-secext.xml", 0); } #endif diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index d7b79a6589b..5286d5c6043 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -247,7 +247,7 @@ int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t= *buf, int reg) return 0; } =20 -static void output_vector_union_type(GString *s, int reg_width, +static void output_vector_union_type(GDBFeatureBuilder *builder, int reg_w= idth, const char *name) { struct TypeSize { @@ -282,10 +282,10 @@ static void output_vector_union_type(GString *s, int = reg_width, =20 /* First define types and totals in a whole VL */ for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { - g_string_append_printf(s, - "", - name, vec_lanes[i].sz, vec_lanes[i].suffix, - vec_lanes[i].gdb_type, reg_width / vec_lane= s[i].size); + gdb_feature_builder_append_tag( + builder, "", + name, vec_lanes[i].sz, vec_lanes[i].suffix, + vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size); } =20 /* @@ -296,86 +296,77 @@ static void output_vector_union_type(GString *s, int = reg_width, for (i =3D 0; i < ARRAY_SIZE(suf); i++) { int bits =3D 8 << i; =20 - g_string_append_printf(s, "", name, suf[i]); + gdb_feature_builder_append_tag(builder, "", + name, suf[i]); for (j =3D 0; j < ARRAY_SIZE(vec_lanes); j++) { if (vec_lanes[j].size =3D=3D bits) { - g_string_append_printf(s, "", - vec_lanes[j].suffix, name, - vec_lanes[j].sz, vec_lanes[j].suffi= x); + gdb_feature_builder_append_tag( + builder, "", + vec_lanes[j].suffix, name, + vec_lanes[j].sz, vec_lanes[j].suffix); } } - g_string_append(s, ""); + gdb_feature_builder_append_tag(builder, ""); } =20 /* And now the final union of unions */ - g_string_append_printf(s, "", name); + gdb_feature_builder_append_tag(builder, "", name); for (i =3D ARRAY_SIZE(suf) - 1; i >=3D 0; i--) { - g_string_append_printf(s, "= ", - suf[i], name, suf[i]); + gdb_feature_builder_append_tag(builder, + "", + suf[i], name, suf[i]); } - g_string_append(s, ""); + gdb_feature_builder_append_tag(builder, ""); } =20 -int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg) +GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cs, int base_reg) { ARMCPU *cpu =3D ARM_CPU(cs); - GString *s =3D g_string_new(NULL); - DynamicGDBXMLInfo *info =3D &cpu->dyn_svereg_xml; int reg_width =3D cpu->sve_max_vq * 128; int pred_width =3D cpu->sve_max_vq * 16; - int base_reg =3D orig_base_reg; + GDBFeatureBuilder builder; + char *name; + int reg =3D 0; int i; =20 - g_string_printf(s, ""); - g_string_append_printf(s, "= "); - g_string_append_printf(s, ""); + gdb_feature_builder_init(&builder, &cpu->dyn_svereg_feature.desc, + "org.gnu.gdb.aarch64.sve", "sve-registers.xml= ", + base_reg); =20 /* Create the vector union type. */ - output_vector_union_type(s, reg_width, "svev"); + output_vector_union_type(&builder, reg_width, "svev"); =20 /* Create the predicate vector type. */ - g_string_append_printf(s, - "", - pred_width / 8); + gdb_feature_builder_append_tag( + &builder, "= ", + pred_width / 8); =20 /* Define the vector registers. */ for (i =3D 0; i < 32; i++) { - g_string_append_printf(s, - "", - i, reg_width, base_reg++); + name =3D g_strdup_printf("z%d", i); + gdb_feature_builder_append_reg(&builder, name, reg_width, reg++, + "svev", NULL); } =20 /* fpscr & status registers */ - g_string_append_printf(s, "", base_reg++); - g_string_append_printf(s, "", base_reg++); + gdb_feature_builder_append_reg(&builder, "fpsr", 32, reg++, + "int", "float"); + gdb_feature_builder_append_reg(&builder, "fpcr", 32, reg++, + "int", "float"); =20 /* Define the predicate registers. */ for (i =3D 0; i < 16; i++) { - g_string_append_printf(s, - "", - i, pred_width, base_reg++); + name =3D g_strdup_printf("p%d", i); + gdb_feature_builder_append_reg(&builder, name, pred_width, reg++, + "svep", NULL); } - g_string_append_printf(s, - "", - pred_width, base_reg++); + gdb_feature_builder_append_reg(&builder, "ffr", pred_width, reg++, + "svep", "vector"); =20 /* Define the vector length pseudo-register. */ - g_string_append_printf(s, - "", - base_reg++); + gdb_feature_builder_append_reg(&builder, "vg", 64, reg++, "int", NULL); =20 - g_string_append_printf(s, ""); + gdb_feature_builder_end(&builder); =20 - info->desc =3D g_string_free(s, false); - info->num =3D base_reg - orig_base_reg; - return info->num; + return &cpu->dyn_svereg_feature.desc; } --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155846; cv=none; d=zohomail.com; s=zohoarc; b=HbYgEf158jecJySQuU7fEZmwc53BFcnmnla3HS5Zyl9kuLXYxaCLhuJHA+izj/pbcKUYvZy3zrXzSOgfesasoB5z075vT8CxqDV+h7v4ICUE9XdNINp7N8iQGE5hAt0ELGC5sZ3eyJENtQ8M59jvnIoULXzj6CGb66QdKS8G4B0= ARC-Message-Signature: i=1; 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Thu, 21 Dec 2023 02:47:06 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 26/40] target/ppc: Use GDBFeature for dynamic XML Date: Thu, 21 Dec 2023 10:38:04 +0000 Message-Id: <20231221103818.1633766-27-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155847528100003 From: Akihiko Odaki In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Reviewed-by: Richard Henderson Message-Id: <20231213-gdb-v17-2-777047380591@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- target/ppc/cpu-qom.h | 1 + target/ppc/cpu.h | 4 +--- target/ppc/cpu_init.c | 4 ---- target/ppc/gdbstub.c | 51 ++++++++++++++++--------------------------- 4 files changed, 21 insertions(+), 39 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 0241609efef..8247fa23367 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -20,6 +20,7 @@ #ifndef QEMU_PPC_CPU_QOM_H #define QEMU_PPC_CPU_QOM_H =20 +#include "exec/gdbstub.h" #include "hw/core/cpu.h" =20 #ifdef TARGET_PPC64 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa296..f87c26f98a6 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1471,8 +1471,7 @@ struct PowerPCCPUClass { int bfd_mach; uint32_t l1_dcache_size, l1_icache_size; #ifndef CONFIG_USER_ONLY - unsigned int gdb_num_sprs; - const char *gdb_spr_xml; + GDBFeature gdb_spr; #endif const PPCHash64Options *hash64_opts; struct ppc_radix_page_info *radix_page_info; @@ -1525,7 +1524,6 @@ int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t= *buf, int reg); int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg); #ifndef CONFIG_USER_ONLY hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu); const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name); #endif int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 40fe14a6c25..a0178c3ce80 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6682,10 +6682,6 @@ static void init_ppc_proc(PowerPCCPU *cpu) /* PowerPC implementation specific initialisations (SPRs, timers, ...)= */ (*pcc->init_proc)(env); =20 -#if !defined(CONFIG_USER_ONLY) - ppc_gdb_gen_spr_xml(cpu); -#endif - /* MSR bits & flags consistency checks */ if (env->msr_mask & (1 << 25)) { switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index ec5731e5d67..e3be3dbd109 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -300,15 +300,23 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, ui= nt8_t *mem_buf, int n) } =20 #ifndef CONFIG_USER_ONLY -void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu) +static void gdb_gen_spr_feature(CPUState *cs) { - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cs); + PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; - GString *xml; - char *spr_name; + GDBFeatureBuilder builder; unsigned int num_regs =3D 0; int i; =20 + if (pcc->gdb_spr.xml) { + return; + } + + gdb_feature_builder_init(&builder, &pcc->gdb_spr, + "org.qemu.power.spr", "power-spr.xml", + cs->gdb_num_regs); + for (i =3D 0; i < ARRAY_SIZE(env->spr_cb); i++) { ppc_spr_t *spr =3D &env->spr_cb[i]; =20 @@ -326,35 +334,13 @@ void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu) */ spr->gdb_id =3D num_regs; num_regs++; - } - - if (pcc->gdb_spr_xml) { - return; - } =20 - xml =3D g_string_new(""); - g_string_append(xml, ""); - g_string_append(xml, ""); - - for (i =3D 0; i < ARRAY_SIZE(env->spr_cb); i++) { - ppc_spr_t *spr =3D &env->spr_cb[i]; - - if (!spr->name) { - continue; - } - - spr_name =3D g_ascii_strdown(spr->name, -1); - g_string_append_printf(xml, ""); + gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name= , -1), + TARGET_LONG_BITS, num_regs, + "int", "spr"); } =20 - g_string_append(xml, ""); - - pcc->gdb_num_sprs =3D num_regs; - pcc->gdb_spr_xml =3D g_string_free(xml, false); + gdb_feature_builder_end(&builder); } =20 const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name) @@ -362,7 +348,7 @@ const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const= char *xml_name) PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cs); =20 if (strcmp(xml_name, "power-spr.xml") =3D=3D 0) { - return pcc->gdb_spr_xml; + return pcc->gdb_spr.xml; } return NULL; } @@ -599,7 +585,8 @@ void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc) 32, "power-vsx.xml", 0); } #ifndef CONFIG_USER_ONLY + gdb_gen_spr_feature(cs); gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, - pcc->gdb_num_sprs, "power-spr.xml", 0); + pcc->gdb_spr.num_regs, "power-spr.xml", 0); #endif } --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 27/40] target/riscv: Use GDBFeature for dynamic XML Date: Thu, 21 Dec 2023 10:38:05 +0000 Message-Id: <20231221103818.1633766-28-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155869773100003 From: Akihiko Odaki In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki Message-Id: <20231213-gdb-v17-3-777047380591@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- target/riscv/cpu.h | 5 +-- target/riscv/cpu.c | 4 +-- target/riscv/gdbstub.c | 79 +++++++++++++++++++----------------------- 3 files changed, 40 insertions(+), 48 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 060b7f69a74..ad7236d7547 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,6 +24,7 @@ #include "hw/registerfields.h" #include "hw/qdev-properties.h" #include "exec/cpu-defs.h" +#include "exec/gdbstub.h" #include "qemu/cpu-float.h" #include "qom/object.h" #include "qemu/int128.h" @@ -424,8 +425,8 @@ struct ArchCPU { =20 CPURISCVState env; =20 - char *dyn_csr_xml; - char *dyn_vreg_xml; + GDBFeature dyn_csr_feature; + GDBFeature dyn_vreg_feature; =20 /* Configuration Settings */ RISCVCPUConfig cfg; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b799f133604..673e937a5d8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1534,9 +1534,9 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState= *cs, const char *xmlname) RISCVCPU *cpu =3D RISCV_CPU(cs); =20 if (strcmp(xmlname, "riscv-csr.xml") =3D=3D 0) { - return cpu->dyn_csr_xml; + return cpu->dyn_csr_feature.xml; } else if (strcmp(xmlname, "riscv-vector.xml") =3D=3D 0) { - return cpu->dyn_vreg_xml; + return cpu->dyn_vreg_feature.xml; } =20 return NULL; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 365040228a1..76b72a95954 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -214,13 +214,14 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, u= int8_t *mem_buf, int n) return 0; } =20 -static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) +static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_re= g) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - GString *s =3D g_string_new(NULL); + GDBFeatureBuilder builder; riscv_csr_predicate_fn predicate; + const char *name; int bitsize =3D 16 << mcc->misa_mxl_max; int i; =20 @@ -233,9 +234,9 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int = base_reg) bitsize =3D 64; } =20 - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""= ); + gdb_feature_builder_init(&builder, &cpu->dyn_csr_feature, + "org.gnu.gdb.riscv.csr", "riscv-csr.xml", + base_reg); =20 for (i =3D 0; i < CSR_TABLE_SIZE; i++) { if (env->priv_ver < csr_ops[i].min_priv_ver) { @@ -243,72 +244,64 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, in= t base_reg) } predicate =3D csr_ops[i].predicate; if (predicate && (predicate(env, i) =3D=3D RISCV_EXCP_NONE)) { - if (csr_ops[i].name) { - g_string_append_printf(s, "", base_reg + i); + + gdb_feature_builder_append_reg(&builder, name, bitsize, i, + "int", NULL); } } =20 - g_string_append_printf(s, ""); - - cpu->dyn_csr_xml =3D g_string_free(s, false); + gdb_feature_builder_end(&builder); =20 #if !defined(CONFIG_USER_ONLY) env->debugger =3D false; #endif =20 - return CSR_TABLE_SIZE; + return &cpu->dyn_csr_feature; } =20 -static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) +static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base= _reg) { RISCVCPU *cpu =3D RISCV_CPU(cs); - GString *s =3D g_string_new(NULL); - g_autoptr(GString) ts =3D g_string_new(""); + GDBFeatureBuilder builder; int reg_width =3D cpu->cfg.vlen; - int num_regs =3D 0; int i; =20 - g_string_printf(s, ""); - g_string_append_printf(s, "= "); - g_string_append_printf(s, ""); + gdb_feature_builder_init(&builder, &cpu->dyn_vreg_feature, + "org.gnu.gdb.riscv.vector", "riscv-vector.xml= ", + base_reg); =20 /* First define types and totals in a whole VL */ for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { int count =3D reg_width / vec_lanes[i].size; - g_string_printf(ts, "%s", vec_lanes[i].id); - g_string_append_printf(s, - "", - ts->str, vec_lanes[i].gdb_type, count); + gdb_feature_builder_append_tag( + &builder, "", + vec_lanes[i].id, vec_lanes[i].gdb_type, count); } =20 /* Define unions */ - g_string_append_printf(s, ""); + gdb_feature_builder_append_tag(&builder, ""); for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { - g_string_append_printf(s, "", - vec_lanes[i].suffix, - vec_lanes[i].id); + gdb_feature_builder_append_tag(&builder, + "", + vec_lanes[i].suffix, vec_lanes[i].i= d); } - g_string_append(s, ""); + gdb_feature_builder_append_tag(&builder, ""); =20 /* Define vector registers */ for (i =3D 0; i < 32; i++) { - g_string_append_printf(s, - "", - i, reg_width, base_reg++); - num_regs++; + gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i), + reg_width, i, "riscv_vector", "vect= or"); } =20 - g_string_append_printf(s, ""); + gdb_feature_builder_end(&builder); =20 - cpu->dyn_vreg_xml =3D g_string_free(s, false); - return num_regs; + return &cpu->dyn_vreg_feature; } =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) @@ -324,10 +317,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState= *cs) 32, "riscv-32bit-fpu.xml", 0); } if (env->misa_ext & RVV) { - int base_reg =3D cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_xml(cs, base_reg= ), + ricsv_gen_dynamic_vector_feature(cs, cs->= gdb_num_regs)->num_regs, "riscv-vector.xml", 0); } switch (mcc->misa_mxl_max) { @@ -347,9 +339,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) } =20 if (cpu->cfg.ext_zicsr) { - int base_reg =3D cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - riscv_gen_dynamic_csr_xml(cs, base_reg), + riscv_gen_dynamic_csr_feature(cs, cs->gdb= _num_regs)->num_regs, "riscv-csr.xml", 0); } } --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703156208; cv=none; d=zohomail.com; s=zohoarc; b=E6rDbuX0lyd0DelyVnky+LN61/0d28F18L5yZzW5dITDQd2GyX4QPUm5AurASM6lhPYqWUpTBRC3qQNxEBPYRj5t3P9M9B5mfoPMxFSMWwIJBSUi/0b1sUHIAdYyCYOv5035b3t215LXX9v+8V5hUxgD0uCevSU5F75J5dVAcCk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703156208; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 21 Dec 2023 02:47:09 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 28/40] gdbstub: Use GDBFeature for gdb_register_coprocessor Date: Thu, 21 Dec 2023 10:38:06 +0000 Message-Id: <20231221103818.1633766-29-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703156209518100002 From: Akihiko Odaki This is a tree-wide change to introduce GDBFeature parameter to gdb_register_coprocessor(). The new parameter just replaces num_regs and xml parameters for now. GDBFeature will be utilized to simplify XML lookup in a following change. Signed-off-by: Akihiko Odaki Acked-by: Alex Benn=C3=A9e Message-Id: <20231213-gdb-v17-4-777047380591@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- include/exec/gdbstub.h | 2 +- gdbstub/gdbstub.c | 13 +++++++------ target/arm/gdbstub.c | 35 +++++++++++++++++++---------------- target/hexagon/cpu.c | 3 +-- target/loongarch/gdbstub.c | 2 +- target/m68k/helper.c | 6 +++--- target/microblaze/cpu.c | 5 +++-- target/ppc/gdbstub.c | 11 ++++++----- target/riscv/gdbstub.c | 20 ++++++++++++-------- target/s390x/gdbstub.c | 28 +++++++--------------------- 10 files changed, 60 insertions(+), 65 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index d8a3c56fa2b..ac6fce99a64 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -38,7 +38,7 @@ typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t = *buf, int reg); */ void gdb_register_coprocessor(CPUState *cpu, gdb_get_reg_cb get_reg, gdb_set_reg_cb set_r= eg, - int num_regs, const char *xml, int g_pos); + const GDBFeature *feature, int g_pos); =20 /** * gdbserver_start: start the gdb server diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 46d752bbc2c..068180c83c7 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -544,7 +544,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *m= em_buf, int reg) =20 void gdb_register_coprocessor(CPUState *cpu, gdb_get_reg_cb get_reg, gdb_set_reg_cb set_r= eg, - int num_regs, const char *xml, int g_pos) + const GDBFeature *feature, int g_pos) { GDBRegisterState *s; guint i; @@ -553,7 +553,7 @@ void gdb_register_coprocessor(CPUState *cpu, for (i =3D 0; i < cpu->gdb_regs->len; i++) { /* Check for duplicates. */ s =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (strcmp(s->xml, xml) =3D=3D 0) { + if (strcmp(s->xml, feature->xmlname) =3D=3D 0) { return; } } @@ -565,17 +565,18 @@ void gdb_register_coprocessor(CPUState *cpu, g_array_set_size(cpu->gdb_regs, i + 1); s =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); s->base_reg =3D cpu->gdb_num_regs; - s->num_regs =3D num_regs; + s->num_regs =3D feature->num_regs; s->get_reg =3D get_reg; s->set_reg =3D set_reg; - s->xml =3D xml; + s->xml =3D feature->xml; =20 /* Add to end of list. */ - cpu->gdb_num_regs +=3D num_regs; + cpu->gdb_num_regs +=3D feature->num_regs; if (g_pos) { if (g_pos !=3D s->base_reg) { error_report("Error: Bad gdb register numbering for '%s', " - "expected %d got %d", xml, g_pos, s->base_reg); + "expected %d got %d", feature->xml, + g_pos, s->base_reg); } else { cpu->gdb_num_g_regs =3D cpu->gdb_num_regs; } diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 5949adfb31a..f2b201d3125 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -483,14 +483,14 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) */ #ifdef TARGET_AARCH64 if (isar_feature_aa64_sve(&cpu->isar)) { - int nreg =3D arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_re= gs)->num_regs; + GDBFeature *feature =3D arm_gen_dynamic_svereg_feature(cs, cs-= >gdb_num_regs); gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, - aarch64_gdb_set_sve_reg, nreg, - "sve-registers.xml", 0); + aarch64_gdb_set_sve_reg, feature, 0); } else { gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg, aarch64_gdb_set_fpu_reg, - 34, "aarch64-fpu.xml", 0); + gdb_find_static_feature("aarch64-fpu.= xml"), + 0); } /* * Note that we report pauth information via the feature name @@ -501,19 +501,22 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) if (isar_feature_aa64_pauth(&cpu->isar)) { gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, aarch64_gdb_set_pauth_reg, - 4, "aarch64-pauth.xml", 0); + gdb_find_static_feature("aarch64-paut= h.xml"), + 0); } #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 49, "arm-neon.xml", 0); + gdb_find_static_feature("arm-neon.xml= "), + 0); } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 33, "arm-vfp3.xml", 0); + gdb_find_static_feature("arm-vfp3.xml= "), + 0); } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 17, "arm-vfp.xml", 0); + gdb_find_static_feature("arm-vfp.xml"= ), 0); } if (!arm_feature(env, ARM_FEATURE_M)) { /* @@ -521,29 +524,29 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) * expose to gdb. */ gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_s= ysreg, - 2, "arm-vfp-sysregs.xml", 0); + gdb_find_static_feature("arm-vfp-sysr= egs.xml"), + 0); } } if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) { gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg, - 1, "arm-m-profile-mve.xml", 0); + gdb_find_static_feature("arm-m-profile-mv= e.xml"), + 0); } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_sysreg_feature(cs, cs->gdb_nu= m_regs)->num_regs, - "system-registers.xml", 0); + arm_gen_dynamic_sysreg_feature(cs, cs->gdb_nu= m_regs), + 0); =20 #ifdef CONFIG_TCG if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { gdb_register_coprocessor(cs, arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, - arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs)->num= _regs, - "arm-m-system.xml", 0); + arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs), 0); #ifndef CONFIG_USER_ONLY if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { gdb_register_coprocessor(cs, arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg, - arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs)-= >num_regs, - "arm-m-secext.xml", 0); + arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs),= 0); } #endif } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 9d1ffc3b4bb..65ac9c75ad0 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -341,8 +341,7 @@ static void hexagon_cpu_realize(DeviceState *dev, Error= **errp) =20 gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register, hexagon_hvx_gdb_write_register, - NUM_VREGS + NUM_QREGS, - "hexagon-hvx.xml", 0); + gdb_find_static_feature("hexagon-hvx.xml"), 0= ); =20 qemu_init_vcpu(cs); cpu_reset(cs); diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index 5fc2f19e965..843a869450e 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -118,5 +118,5 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env, void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs) { gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_= fpu, - 41, "loongarch-fpu.xml", 0); + gdb_find_static_feature("loongarch-fpu.xml"),= 0); } diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 0a1544cd68d..675f2dcd5ad 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -152,10 +152,10 @@ void m68k_cpu_init_gdb(M68kCPU *cpu) =20 if (m68k_feature(env, M68K_FEATURE_CF_FPU)) { gdb_register_coprocessor(cs, cf_fpu_gdb_get_reg, cf_fpu_gdb_set_re= g, - 11, "cf-fp.xml", 18); + gdb_find_static_feature("cf-fp.xml"), 18); } else if (m68k_feature(env, M68K_FEATURE_FPU)) { - gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg, - m68k_fpu_gdb_set_reg, 11, "m68k-fp.xml", = 18); + gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg, m68k_fpu_gdb_se= t_reg, + gdb_find_static_feature("m68k-fp.xml"), 1= 8); } /* TODO: Add [E]MAC registers. */ } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bbb3335cadd..1998f69828f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -297,8 +297,9 @@ static void mb_cpu_initfn(Object *obj) CPUMBState *env =3D &cpu->env; =20 gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect, - mb_cpu_gdb_write_stack_protect, 2, - "microblaze-stack-protect.xml", 0); + mb_cpu_gdb_write_stack_protect, + gdb_find_static_feature("microblaze-stack-pro= tect.xml"), + 0); =20 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); =20 diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index e3be3dbd109..09b852464f3 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -570,23 +570,24 @@ void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc) { if (pcc->insns_flags & PPC_FLOAT) { gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, - 33, "power-fpu.xml", 0); + gdb_find_static_feature("power-fpu.xml"),= 0); } if (pcc->insns_flags & PPC_ALTIVEC) { gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg, - 34, "power-altivec.xml", 0); + gdb_find_static_feature("power-altivec.xm= l"), + 0); } if (pcc->insns_flags & PPC_SPE) { gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg, - 34, "power-spe.xml", 0); + gdb_find_static_feature("power-spe.xml"),= 0); } if (pcc->insns_flags2 & PPC2_VSX) { gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, - 32, "power-vsx.xml", 0); + gdb_find_static_feature("power-vsx.xml"),= 0); } #ifndef CONFIG_USER_ONLY gdb_gen_spr_feature(cs); gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, - pcc->gdb_spr.num_regs, "power-spr.xml", 0); + &pcc->gdb_spr, 0); #endif } diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 76b72a95954..a879869fa1a 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -311,28 +311,32 @@ void riscv_cpu_register_gdb_regs_for_features(CPUStat= e *cs) CPURISCVState *env =3D &cpu->env; if (env->misa_ext & RVD) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 32, "riscv-64bit-fpu.xml", 0); + gdb_find_static_feature("riscv-64bit-fpu.= xml"), + 0); } else if (env->misa_ext & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 32, "riscv-32bit-fpu.xml", 0); + gdb_find_static_feature("riscv-32bit-fpu.= xml"), + 0); } if (env->misa_ext & RVV) { gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_feature(cs, cs->= gdb_num_regs)->num_regs, - "riscv-vector.xml", 0); + ricsv_gen_dynamic_vector_feature(cs, cs->= gdb_num_regs), + 0); } switch (mcc->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, - 1, "riscv-32bit-virtual.xml", 0); + gdb_find_static_feature("riscv-32bit-virt= ual.xml"), + 0); break; case MXL_RV64: case MXL_RV128: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, - 1, "riscv-64bit-virtual.xml", 0); + gdb_find_static_feature("riscv-64bit-virt= ual.xml"), + 0); break; default: g_assert_not_reached(); @@ -340,7 +344,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) =20 if (cpu->cfg.ext_zicsr) { gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - riscv_gen_dynamic_csr_feature(cs, cs->gdb= _num_regs)->num_regs, - "riscv-csr.xml", 0); + riscv_gen_dynamic_csr_feature(cs, cs->gdb= _num_regs), + 0); } } diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 6fbfd41bc86..02c388dc323 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -69,8 +69,6 @@ int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) /* the values represent the positions in s390-acr.xml */ #define S390_A0_REGNUM 0 #define S390_A15_REGNUM 15 -/* total number of registers in s390-acr.xml */ -#define S390_NUM_AC_REGS 16 =20 static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n) { @@ -98,8 +96,6 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *= mem_buf, int n) #define S390_FPC_REGNUM 0 #define S390_F0_REGNUM 1 #define S390_F15_REGNUM 16 -/* total number of registers in s390-fpr.xml */ -#define S390_NUM_FP_REGS 17 =20 static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n) { @@ -132,8 +128,6 @@ static int cpu_write_fp_reg(CPUS390XState *env, uint8_t= *mem_buf, int n) #define S390_V15L_REGNUM 15 #define S390_V16_REGNUM 16 #define S390_V31_REGNUM 31 -/* total number of registers in s390-vx.xml */ -#define S390_NUM_VREGS 32 =20 static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n) { @@ -172,8 +166,6 @@ static int cpu_write_vreg(CPUS390XState *env, uint8_t *= mem_buf, int n) /* the values represent the positions in s390-cr.xml */ #define S390_C0_REGNUM 0 #define S390_C15_REGNUM 15 -/* total number of registers in s390-cr.xml */ -#define S390_NUM_C_REGS 16 =20 #ifndef CONFIG_USER_ONLY static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n) @@ -206,8 +198,6 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t = *mem_buf, int n) #define S390_VIRT_CPUTM_REGNUM 1 #define S390_VIRT_BEA_REGNUM 2 #define S390_VIRT_PREFIX_REGNUM 3 -/* total number of registers in s390-virt.xml */ -#define S390_NUM_VIRT_REGS 4 =20 static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int = n) { @@ -254,8 +244,6 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint8= _t *mem_buf, int n) #define S390_VIRT_KVM_PFT_REGNUM 1 #define S390_VIRT_KVM_PFS_REGNUM 2 #define S390_VIRT_KVM_PFC_REGNUM 3 -/* total number of registers in s390-virt-kvm.xml */ -#define S390_NUM_VIRT_KVM_REGS 4 =20 static int cpu_read_virt_kvm_reg(CPUS390XState *env, GByteArray *mem_buf, = int n) { @@ -303,8 +291,6 @@ static int cpu_write_virt_kvm_reg(CPUS390XState *env, u= int8_t *mem_buf, int n) #define S390_GS_GSD_REGNUM 1 #define S390_GS_GSSM_REGNUM 2 #define S390_GS_GSEPLA_REGNUM 3 -/* total number of registers in s390-gs.xml */ -#define S390_NUM_GS_REGS 4 =20 static int cpu_read_gs_reg(CPUS390XState *env, GByteArray *buf, int n) { @@ -322,33 +308,33 @@ void s390_cpu_gdb_init(CPUState *cs) { gdb_register_coprocessor(cs, cpu_read_ac_reg, cpu_write_ac_reg, - S390_NUM_AC_REGS, "s390-acr.xml", 0); + gdb_find_static_feature("s390-acr.xml"), 0); =20 gdb_register_coprocessor(cs, cpu_read_fp_reg, cpu_write_fp_reg, - S390_NUM_FP_REGS, "s390-fpr.xml", 0); + gdb_find_static_feature("s390-fpr.xml"), 0); =20 gdb_register_coprocessor(cs, cpu_read_vreg, cpu_write_vreg, - S390_NUM_VREGS, "s390-vx.xml", 0); + gdb_find_static_feature("s390-vx.xml"), 0); =20 gdb_register_coprocessor(cs, cpu_read_gs_reg, cpu_write_gs_reg, - S390_NUM_GS_REGS, "s390-gs.xml", 0); + gdb_find_static_feature("s390-gs.xml"), 0); =20 #ifndef CONFIG_USER_ONLY gdb_register_coprocessor(cs, cpu_read_c_reg, cpu_write_c_reg, - S390_NUM_C_REGS, "s390-cr.xml", 0); + gdb_find_static_feature("s390-cr.xml"), 0); =20 gdb_register_coprocessor(cs, cpu_read_virt_reg, cpu_write_virt_reg, - S390_NUM_VIRT_REGS, "s390-virt.xml", 0); + gdb_find_static_feature("s390-virt.xml"), 0); =20 if (kvm_enabled()) { gdb_register_coprocessor(cs, cpu_read_virt_kvm_reg, cpu_write_virt_kvm_reg, - S390_NUM_VIRT_KVM_REGS, "s390-virt-kvm.xm= l", + gdb_find_static_feature("s390-virt-kvm.xm= l"), 0); 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 29/40] gdbstub: Use GDBFeature for GDBRegisterState Date: Thu, 21 Dec 2023 10:38:07 +0000 Message-Id: <20231221103818.1633766-30-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703156102933100002 From: Akihiko Odaki Simplify GDBRegisterState by replacing num_regs and xml members with one member that points to GDBFeature. Signed-off-by: Akihiko Odaki Reviewed-by: Alex Benn=C3=A9e Message-Id: <20231213-gdb-v17-5-777047380591@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- gdbstub/gdbstub.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 068180c83c7..a80729436b6 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -47,10 +47,9 @@ =20 typedef struct GDBRegisterState { int base_reg; - int num_regs; gdb_get_reg_cb get_reg; gdb_set_reg_cb set_reg; - const char *xml; + const GDBFeature *feature; } GDBRegisterState; =20 GDBState gdbserver_state; @@ -391,7 +390,7 @@ static const char *get_feature_xml(const char *p, const= char **newp, g_ptr_array_add( xml, g_markup_printf_escaped("", - r->xml)); + r->feature->xmlname)); } } g_ptr_array_add(xml, g_strdup("")); @@ -513,7 +512,7 @@ static int gdb_read_register(CPUState *cpu, GByteArray = *buf, int reg) if (cpu->gdb_regs) { for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (r->base_reg <=3D reg && reg < r->base_reg + r->num_regs) { + if (r->base_reg <=3D reg && reg < r->base_reg + r->feature->nu= m_regs) { return r->get_reg(env, buf, reg - r->base_reg); } } @@ -534,7 +533,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *m= em_buf, int reg) if (cpu->gdb_regs) { for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (r->base_reg <=3D reg && reg < r->base_reg + r->num_regs) { + if (r->base_reg <=3D reg && reg < r->base_reg + r->feature->nu= m_regs) { return r->set_reg(env, mem_buf, reg - r->base_reg); } } @@ -553,7 +552,7 @@ void gdb_register_coprocessor(CPUState *cpu, for (i =3D 0; i < cpu->gdb_regs->len; i++) { /* Check for duplicates. */ s =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (strcmp(s->xml, feature->xmlname) =3D=3D 0) { + if (s->feature =3D=3D feature) { return; } } @@ -565,10 +564,9 @@ void gdb_register_coprocessor(CPUState *cpu, g_array_set_size(cpu->gdb_regs, i + 1); s =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); s->base_reg =3D cpu->gdb_num_regs; - s->num_regs =3D feature->num_regs; s->get_reg =3D get_reg; s->set_reg =3D set_reg; - s->xml =3D feature->xml; + s->feature =3D feature; =20 /* Add to end of list. */ cpu->gdb_num_regs +=3D feature->num_regs; --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703156247; cv=none; d=zohomail.com; s=zohoarc; b=fnP2M6/eJ4azOC1Sh14rWjOTCA+YbovXRvGwmFXkZrR4x1CqjHWZ2iz26R3kbtDQhH39kwC9kfYEN6RKlNvNvDXNL6hSJLcd4g+1Gm8gdBKnpCRalpm9RnclhVbzO13dann9skKBJf1xGZDPPOuYkXVozlvEy6l/bdgfmyr8k4U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703156247; 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Thu, 21 Dec 2023 02:56:59 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 30/40] gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb Date: Thu, 21 Dec 2023 10:38:08 +0000 Message-Id: <20231221103818.1633766-31-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703156247833100001 From: Akihiko Odaki Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the gdb_read_register and gdb_write_register members of CPUClass to allow to unify the logic to access registers of the core and coprocessors in the future. Signed-off-by: Akihiko Odaki Reviewed-by: Alex Benn=C3=A9e Message-Id: <20231213-gdb-v17-6-777047380591@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- include/exec/gdbstub.h | 4 +- target/arm/internals.h | 12 +++--- target/hexagon/internal.h | 4 +- target/microblaze/cpu.h | 4 +- gdbstub/gdbstub.c | 6 +-- target/arm/gdbstub.c | 51 ++++++++++++++++-------- target/arm/gdbstub64.c | 27 +++++++++---- target/hexagon/gdbstub.c | 10 ++++- target/loongarch/gdbstub.c | 11 ++++-- target/m68k/helper.c | 20 ++++++++-- target/microblaze/gdbstub.c | 9 ++++- target/ppc/gdbstub.c | 46 +++++++++++++++++----- target/riscv/gdbstub.c | 46 ++++++++++++++++------ target/s390x/gdbstub.c | 77 ++++++++++++++++++++++++++++--------- 14 files changed, 236 insertions(+), 91 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index ac6fce99a64..bcaab1bc750 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -24,8 +24,8 @@ typedef struct GDBFeatureBuilder { =20 =20 /* Get or set a register. Returns the size of the register. */ -typedef int (*gdb_get_reg_cb)(CPUArchState *env, GByteArray *buf, int reg); -typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t *buf, int reg); +typedef int (*gdb_get_reg_cb)(CPUState *cpu, GByteArray *buf, int reg); +typedef int (*gdb_set_reg_cb)(CPUState *cpu, uint8_t *buf, int reg); =20 /** * gdb_register_coprocessor() - register a supplemental set of registers diff --git a/target/arm/internals.h b/target/arm/internals.h index 1136710741f..a08f461f444 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1447,12 +1447,12 @@ static inline uint64_t pmu_counter_mask(CPUARMState= *env) =20 #ifdef TARGET_AARCH64 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); -int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); -int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); -int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); -int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); -int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); -int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index d732b6bb3c7..beb08cb7e38 100644 --- a/target/hexagon/internal.h +++ b/target/hexagon/internal.h @@ -33,8 +33,8 @@ =20 int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_bu= f, int n); -int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf,= int n); +int hexagon_hvx_gdb_read_register(CPUState *env, GByteArray *mem_buf, int = n); +int hexagon_hvx_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n); =20 void hexagon_debug_vreg(CPUHexagonState *env, int regnum); void hexagon_debug_qreg(CPUHexagonState *env, int regnum); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b5374365f5f..1906d8f266a 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -381,8 +381,8 @@ G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs= , vaddr vaddr, void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -int mb_cpu_gdb_read_stack_protect(CPUArchState *cpu, GByteArray *buf, int = reg); -int mb_cpu_gdb_write_stack_protect(CPUArchState *cpu, uint8_t *buf, int re= g); +int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *buf, int reg); +int mb_cpu_gdb_write_stack_protect(CPUState *cs, uint8_t *buf, int reg); =20 static inline uint32_t mb_cpu_read_msr(const CPUMBState *env) { diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index a80729436b6..21fea7fffae 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -502,7 +502,6 @@ const GDBFeature *gdb_find_static_feature(const char *x= mlname) static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { CPUClass *cc =3D CPU_GET_CLASS(cpu); - CPUArchState *env =3D cpu_env(cpu); GDBRegisterState *r; =20 if (reg < cc->gdb_num_core_regs) { @@ -513,7 +512,7 @@ static int gdb_read_register(CPUState *cpu, GByteArray = *buf, int reg) for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); if (r->base_reg <=3D reg && reg < r->base_reg + r->feature->nu= m_regs) { - return r->get_reg(env, buf, reg - r->base_reg); + return r->get_reg(cpu, buf, reg - r->base_reg); } } } @@ -523,7 +522,6 @@ static int gdb_read_register(CPUState *cpu, GByteArray = *buf, int reg) static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) { CPUClass *cc =3D CPU_GET_CLASS(cpu); - CPUArchState *env =3D cpu_env(cpu); GDBRegisterState *r; =20 if (reg < cc->gdb_num_core_regs) { @@ -534,7 +532,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *m= em_buf, int reg) for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); if (r->base_reg <=3D reg && reg < r->base_reg + r->feature->nu= m_regs) { - return r->set_reg(env, mem_buf, reg - r->base_reg); + return r->set_reg(cpu, mem_buf, reg - r->base_reg); } } } diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index f2b201d3125..059d84f98e5 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -106,9 +106,10 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) return 0; } =20 -static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +static int vfp_gdb_get_reg(CPUState *cs, GByteArray *buf, int reg) { - ARMCPU *cpu =3D env_archcpu(env); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; =20 /* VFP data registers are always little-endian. */ @@ -130,9 +131,10 @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArra= y *buf, int reg) return 0; } =20 -static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +static int vfp_gdb_set_reg(CPUState *cs, uint8_t *buf, int reg) { - ARMCPU *cpu =3D env_archcpu(env); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; =20 if (reg < nregs) { @@ -156,8 +158,11 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *= buf, int reg) return 0; } =20 -static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) +static int vfp_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); @@ -167,8 +172,11 @@ static int vfp_gdb_get_sysreg(CPUARMState *env, GByteA= rray *buf, int reg) return 0; } =20 -static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +static int vfp_gdb_set_sysreg(CPUState *cs, uint8_t *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0: env->vfp.xregs[ARM_VFP_FPSID] =3D ldl_p(buf); @@ -180,8 +188,11 @@ static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_= t *buf, int reg) return 0; } =20 -static int mve_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +static int mve_gdb_get_reg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0: return gdb_get_reg32(buf, env->v7m.vpr); @@ -190,8 +201,11 @@ static int mve_gdb_get_reg(CPUARMState *env, GByteArra= y *buf, int reg) } } =20 -static int mve_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +static int mve_gdb_set_reg(CPUState *cs, uint8_t *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0: env->v7m.vpr =3D ldl_p(buf); @@ -210,9 +224,10 @@ static int mve_gdb_set_reg(CPUARMState *env, uint8_t *= buf, int reg) * We return the number of bytes copied */ =20 -static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) +static int arm_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg) { - ARMCPU *cpu =3D env_archcpu(env); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; const ARMCPRegInfo *ri; uint32_t key; =20 @@ -228,7 +243,7 @@ static int arm_gdb_get_sysreg(CPUARMState *env, GByteAr= ray *buf, int reg) return 0; } =20 -static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +static int arm_gdb_set_sysreg(CPUState *cs, uint8_t *buf, int reg) { return 0; } @@ -367,8 +382,11 @@ static int m_sysreg_get(CPUARMState *env, GByteArray *= buf, return gdb_get_reg32(buf, *ptr); } =20 -static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int = reg) +static int arm_gdb_get_m_systemreg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + /* * Here, we emulate MRS instruction, where CONTROL has a mix of * banked and non-banked bits. @@ -379,7 +397,7 @@ static int arm_gdb_get_m_systemreg(CPUARMState *env, GB= yteArray *buf, int reg) return m_sysreg_get(env, buf, reg, env->v7m.secure); } =20 -static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg) +static int arm_gdb_set_m_systemreg(CPUState *cs, uint8_t *buf, int reg) { return 0; /* TODO */ } @@ -414,12 +432,15 @@ static GDBFeature *arm_gen_dynamic_m_systemreg_featur= e(CPUState *cs, * For user-only, we see the non-secure registers via m_systemreg above. * For secext, encode the non-secure view as even and secure view as odd. */ -static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int = reg) +static int arm_gdb_get_m_secextreg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + return m_sysreg_get(env, buf, reg >> 1, reg & 1); } =20 -static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg) +static int arm_gdb_set_m_secextreg(CPUState *cs, uint8_t *buf, int reg) { return 0; /* TODO */ } diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 5286d5c6043..caa31ff3fa1 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -72,8 +72,11 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t= *mem_buf, int n) return 0; } =20 -int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0 ... 31: { @@ -92,8 +95,11 @@ int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray= *buf, int reg) } } =20 -int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0 ... 31: /* 128 bit FP register */ @@ -116,9 +122,10 @@ int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t = *buf, int reg) } } =20 -int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg) { - ARMCPU *cpu =3D env_archcpu(env); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; =20 switch (reg) { /* The first 32 registers are the zregs */ @@ -164,9 +171,10 @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArr= ay *buf, int reg) return 0; } =20 -int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg) { - ARMCPU *cpu =3D env_archcpu(env); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; =20 /* The first 32 registers are the zregs */ switch (reg) { @@ -210,8 +218,11 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t = *buf, int reg) return 0; } =20 -int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0: /* pauth_dmask */ case 1: /* pauth_cmask */ @@ -241,7 +252,7 @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteAr= ray *buf, int reg) } } =20 -int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg) { /* All pseudo registers are read-only. */ return 0; diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index 54d37e006e0..6007e6462b9 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -81,8 +81,11 @@ static int gdb_get_qreg(CPUHexagonState *env, GByteArray= *mem_buf, int n) return total; } =20 -int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_bu= f, int n) +int hexagon_hvx_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { + HexagonCPU *cpu =3D HEXAGON_CPU(cs); + CPUHexagonState *env =3D &cpu->env; + if (n < NUM_VREGS) { return gdb_get_vreg(env, mem_buf, n); } @@ -115,8 +118,11 @@ static int gdb_put_qreg(CPUHexagonState *env, uint8_t = *mem_buf, int n) return MAX_VEC_SIZE_BYTES / 8; } =20 -int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf,= int n) +int hexagon_hvx_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { + HexagonCPU *cpu =3D HEXAGON_CPU(cs); + CPUHexagonState *env =3D &cpu->env; + if (n < NUM_VREGS) { return gdb_put_vreg(env, mem_buf, n); } diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index 843a869450e..22c6889011e 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -84,9 +84,11 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8= _t *mem_buf, int n) return length; } =20 -static int loongarch_gdb_get_fpu(CPULoongArchState *env, - GByteArray *mem_buf, int n) +static int loongarch_gdb_get_fpu(CPUState *cs, GByteArray *mem_buf, int n) { + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPULoongArchState *env =3D &cpu->env; + if (0 <=3D n && n < 32) { return gdb_get_reg64(mem_buf, env->fpr[n].vreg.D(0)); } else if (32 <=3D n && n < 40) { @@ -97,9 +99,10 @@ static int loongarch_gdb_get_fpu(CPULoongArchState *env, return 0; } =20 -static int loongarch_gdb_set_fpu(CPULoongArchState *env, - uint8_t *mem_buf, int n) +static int loongarch_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n) { + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPULoongArchState *env =3D &cpu->env; int length =3D 0; =20 if (0 <=3D n && n < 32) { diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 675f2dcd5ad..a5ee4d87e32 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -69,8 +69,11 @@ void m68k_cpu_list(void) g_slist_free(list); } =20 -static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int = n) +static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) { + M68kCPU *cpu =3D M68K_CPU(cs); + CPUM68KState *env =3D &cpu->env; + if (n < 8) { float_status s; return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d,= &s)); @@ -86,8 +89,11 @@ static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteAr= ray *mem_buf, int n) return 0; } =20 -static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n) +static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) { + M68kCPU *cpu =3D M68K_CPU(cs); + CPUM68KState *env =3D &cpu->env; + if (n < 8) { float_status s; env->fregs[n].d =3D float64_to_floatx80(ldq_p(mem_buf), &s); @@ -106,8 +112,11 @@ static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8= _t *mem_buf, int n) return 0; } =20 -static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, in= t n) +static int m68k_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) { + M68kCPU *cpu =3D M68K_CPU(cs); + CPUM68KState *env =3D &cpu->env; + if (n < 8) { int len =3D gdb_get_reg16(mem_buf, env->fregs[n].l.upper); len +=3D gdb_get_reg16(mem_buf, 0); @@ -125,8 +134,11 @@ static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GBy= teArray *mem_buf, int n) return 0; } =20 -static int m68k_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n) +static int m68k_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) { + M68kCPU *cpu =3D M68K_CPU(cs); + CPUM68KState *env =3D &cpu->env; + if (n < 8) { env->fregs[n].l.upper =3D lduw_be_p(mem_buf); env->fregs[n].l.lower =3D ldq_be_p(mem_buf + 4); diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 29ac6e9c0f7..6ffc5ad0752 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -94,8 +94,10 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *m= em_buf, int n) return gdb_get_reg32(mem_buf, val); } =20 -int mb_cpu_gdb_read_stack_protect(CPUMBState *env, GByteArray *mem_buf, in= t n) +int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *mem_buf, int n) { + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + CPUMBState *env =3D &cpu->env; uint32_t val; =20 switch (n) { @@ -153,8 +155,11 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) return 4; } =20 -int mb_cpu_gdb_write_stack_protect(CPUMBState *env, uint8_t *mem_buf, int = n) +int mb_cpu_gdb_write_stack_protect(CPUState *cs, uint8_t *mem_buf, int n) { + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + CPUMBState *env =3D &cpu->env; + switch (n) { case GDB_SP_SHL: env->slr =3D ldl_p(mem_buf); diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 09b852464f3..8ca37b6bf95 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -369,8 +369,10 @@ static int gdb_find_spr_idx(CPUPPCState *env, int n) return -1; } =20 -static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_spr_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; int reg; int len; =20 @@ -385,8 +387,10 @@ static int gdb_get_spr_reg(CPUPPCState *env, GByteArra= y *buf, int n) return len; } =20 -static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_spr_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; int reg; int len; =20 @@ -403,8 +407,10 @@ static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *= mem_buf, int n) } #endif =20 -static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_float_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; uint8_t *mem_buf; if (n < 32) { gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); @@ -421,8 +427,11 @@ static int gdb_get_float_reg(CPUPPCState *env, GByteAr= ray *buf, int n) return 0; } =20 -static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_float_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (n < 32) { ppc_maybe_bswap_register(env, mem_buf, 8); *cpu_fpr_ptr(env, n) =3D ldq_p(mem_buf); @@ -436,8 +445,10 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t= *mem_buf, int n) return 0; } =20 -static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_avr_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; uint8_t *mem_buf; =20 if (n < 32) { @@ -462,8 +473,11 @@ static int gdb_get_avr_reg(CPUPPCState *env, GByteArra= y *buf, int n) return 0; } =20 -static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_avr_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (n < 32) { ppc_avr_t *avr =3D cpu_avr_ptr(env, n); ppc_maybe_bswap_register(env, mem_buf, 16); @@ -484,8 +498,11 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *= mem_buf, int n) return 0; } =20 -static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_spe_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (n < 32) { #if defined(TARGET_PPC64) gdb_get_reg32(buf, env->gpr[n] >> 32); @@ -508,8 +525,11 @@ static int gdb_get_spe_reg(CPUPPCState *env, GByteArra= y *buf, int n) return 0; } =20 -static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_spe_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (n < 32) { #if defined(TARGET_PPC64) target_ulong lo =3D (uint32_t)env->gpr[n]; @@ -537,8 +557,11 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *= mem_buf, int n) return 0; } =20 -static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_vsx_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (n < 32) { gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); @@ -547,8 +570,11 @@ static int gdb_get_vsx_reg(CPUPPCState *env, GByteArra= y *buf, int n) return 0; } =20 -static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_vsx_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (n < 32) { ppc_maybe_bswap_register(env, mem_buf, 8); *cpu_vsrl_ptr(env, n) =3D ldq_p(mem_buf); diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index a879869fa1a..68d0fdc1fd6 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -108,8 +108,11 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t= *mem_buf, int n) return length; } =20 -static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) +static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + if (n < 32) { if (env->misa_ext & RVD) { return gdb_get_reg64(buf, env->fpr[n]); @@ -121,8 +124,11 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByte= Array *buf, int n) return 0; } =20 -static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) +static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + if (n < 32) { env->fpr[n] =3D ldq_p(mem_buf); /* always 64-bit */ return sizeof(uint64_t); @@ -130,8 +136,10 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8= _t *mem_buf, int n) return 0; } =20 -static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) +static int riscv_gdb_get_vector(CPUState *cs, GByteArray *buf, int n) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; uint16_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; if (n < 32) { int i; @@ -146,8 +154,10 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GB= yteArray *buf, int n) return 0; } =20 -static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int = n) +static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; uint16_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; if (n < 32) { int i; @@ -160,8 +170,11 @@ static int riscv_gdb_set_vector(CPURISCVState *env, ui= nt8_t *mem_buf, int n) return 0; } =20 -static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) +static int riscv_gdb_get_csr(CPUState *cs, GByteArray *buf, int n) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + if (n < CSR_TABLE_SIZE) { target_ulong val =3D 0; int result; @@ -174,8 +187,11 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByte= Array *buf, int n) return 0; } =20 -static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) +static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + if (n < CSR_TABLE_SIZE) { target_ulong val =3D ldtul_p(mem_buf); int result; @@ -188,25 +204,31 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint= 8_t *mem_buf, int n) return 0; } =20 -static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n) +static int riscv_gdb_get_virtual(CPUState *cs, GByteArray *buf, int n) { if (n =3D=3D 0) { #ifdef CONFIG_USER_ONLY return gdb_get_regl(buf, 0); #else - return gdb_get_regl(buf, cs->priv); + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + return gdb_get_regl(buf, env->priv); #endif } return 0; } =20 -static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int = n) +static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n) { if (n =3D=3D 0) { #ifndef CONFIG_USER_ONLY - cs->priv =3D ldtul_p(mem_buf) & 0x3; - if (cs->priv =3D=3D PRV_RESERVED) { - cs->priv =3D PRV_S; + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + env->priv =3D ldtul_p(mem_buf) & 0x3; + if (env->priv =3D=3D PRV_RESERVED) { + env->priv =3D PRV_S; } #endif return sizeof(target_ulong); diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 02c388dc323..c1e7c59b822 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -70,8 +70,11 @@ int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) #define S390_A0_REGNUM 0 #define S390_A15_REGNUM 15 =20 -static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_ac_reg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_A0_REGNUM ... S390_A15_REGNUM: return gdb_get_reg32(buf, env->aregs[n]); @@ -80,8 +83,11 @@ static int cpu_read_ac_reg(CPUS390XState *env, GByteArra= y *buf, int n) } } =20 -static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_ac_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_A0_REGNUM ... S390_A15_REGNUM: env->aregs[n] =3D ldl_p(mem_buf); @@ -97,8 +103,11 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t= *mem_buf, int n) #define S390_F0_REGNUM 1 #define S390_F15_REGNUM 16 =20 -static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_fp_reg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_FPC_REGNUM: return gdb_get_reg32(buf, env->fpc); @@ -109,8 +118,11 @@ static int cpu_read_fp_reg(CPUS390XState *env, GByteAr= ray *buf, int n) } } =20 -static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_fp_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_FPC_REGNUM: env->fpc =3D ldl_p(mem_buf); @@ -129,8 +141,10 @@ static int cpu_write_fp_reg(CPUS390XState *env, uint8_= t *mem_buf, int n) #define S390_V16_REGNUM 16 #define S390_V31_REGNUM 31 =20 -static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_vreg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; int ret; =20 switch (n) { @@ -148,8 +162,11 @@ static int cpu_read_vreg(CPUS390XState *env, GByteArra= y *buf, int n) return ret; } =20 -static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_vreg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_V0L_REGNUM ... S390_V15L_REGNUM: env->vregs[n][1] =3D ldtul_p(mem_buf + 8); @@ -168,8 +185,11 @@ static int cpu_write_vreg(CPUS390XState *env, uint8_t = *mem_buf, int n) #define S390_C15_REGNUM 15 =20 #ifndef CONFIG_USER_ONLY -static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_c_reg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_C0_REGNUM ... S390_C15_REGNUM: return gdb_get_regl(buf, env->cregs[n]); @@ -178,8 +198,11 @@ static int cpu_read_c_reg(CPUS390XState *env, GByteArr= ay *buf, int n) } } =20 -static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_c_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_C0_REGNUM ... S390_C15_REGNUM: env->cregs[n] =3D ldtul_p(mem_buf); @@ -199,8 +222,11 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t= *mem_buf, int n) #define S390_VIRT_BEA_REGNUM 2 #define S390_VIRT_PREFIX_REGNUM 3 =20 -static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int = n) +static int cpu_read_virt_reg(CPUState *cs, GByteArray *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_VIRT_CKC_REGNUM: return gdb_get_regl(mem_buf, env->ckc); @@ -215,24 +241,27 @@ static int cpu_read_virt_reg(CPUS390XState *env, GByt= eArray *mem_buf, int n) } } =20 -static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_virt_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_VIRT_CKC_REGNUM: env->ckc =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(env_cpu(env)); + cpu_synchronize_post_init(cs); return 8; case S390_VIRT_CPUTM_REGNUM: env->cputm =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(env_cpu(env)); + cpu_synchronize_post_init(cs); return 8; case S390_VIRT_BEA_REGNUM: env->gbea =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(env_cpu(env)); + cpu_synchronize_post_init(cs); return 8; case S390_VIRT_PREFIX_REGNUM: env->psa =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(env_cpu(env)); + cpu_synchronize_post_init(cs); return 8; default: return 0; @@ -245,8 +274,11 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint= 8_t *mem_buf, int n) #define S390_VIRT_KVM_PFS_REGNUM 2 #define S390_VIRT_KVM_PFC_REGNUM 3 =20 -static int cpu_read_virt_kvm_reg(CPUS390XState *env, GByteArray *mem_buf, = int n) +static int cpu_read_virt_kvm_reg(CPUState *cs, GByteArray *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_VIRT_KVM_PP_REGNUM: return gdb_get_regl(mem_buf, env->pp); @@ -261,8 +293,11 @@ static int cpu_read_virt_kvm_reg(CPUS390XState *env, G= ByteArray *mem_buf, int n) } } =20 -static int cpu_write_virt_kvm_reg(CPUS390XState *env, uint8_t *mem_buf, in= t n) +static int cpu_write_virt_kvm_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_VIRT_KVM_PP_REGNUM: env->pp =3D ldtul_p(mem_buf); @@ -292,13 +327,19 @@ static int cpu_write_virt_kvm_reg(CPUS390XState *env,= uint8_t *mem_buf, int n) #define S390_GS_GSSM_REGNUM 2 #define S390_GS_GSEPLA_REGNUM 3 =20 -static int cpu_read_gs_reg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_gs_reg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + return gdb_get_regl(buf, env->gscb[n]); } =20 -static int cpu_write_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_gs_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + env->gscb[n] =3D ldtul_p(mem_buf); cpu_synchronize_post_init(env_cpu(env)); return 8; --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 31/40] gdbstub: Simplify XML lookup Date: Thu, 21 Dec 2023 10:38:09 +0000 Message-Id: <20231221103818.1633766-32-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155976243100003 From: Akihiko Odaki Now we know all instances of GDBFeature that is used in CPU so we can traverse them to find XML. This removes the need for a CPU-specific lookup function for dynamic XMLs. Signed-off-by: Akihiko Odaki Reviewed-by: Alex Benn=C3=A9e Message-Id: <20231213-gdb-v17-7-777047380591@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- include/exec/gdbstub.h | 6 +++ gdbstub/gdbstub.c | 118 +++++++++++++++++++++-------------------- hw/core/cpu-common.c | 5 +- 3 files changed, 69 insertions(+), 60 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index bcaab1bc750..82a8afa237f 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -27,6 +27,12 @@ typedef struct GDBFeatureBuilder { typedef int (*gdb_get_reg_cb)(CPUState *cpu, GByteArray *buf, int reg); typedef int (*gdb_set_reg_cb)(CPUState *cpu, uint8_t *buf, int reg); =20 +/** + * gdb_init_cpu(): Initialize the CPU for gdbstub. + * @cpu: The CPU to be initialized. + */ +void gdb_init_cpu(CPUState *cpu); + /** * gdb_register_coprocessor() - register a supplemental set of registers * @cpu - the CPU associated with registers diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 21fea7fffae..1d5c1da1b24 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -352,6 +352,7 @@ static const char *get_feature_xml(const char *p, const= char **newp, { CPUState *cpu =3D gdb_get_first_cpu_in_process(process); CPUClass *cc =3D CPU_GET_CLASS(cpu); + GDBRegisterState *r; size_t len; =20 /* @@ -365,7 +366,6 @@ static const char *get_feature_xml(const char *p, const= char **newp, /* Is it the main target xml? */ if (strncmp(p, "target.xml", len) =3D=3D 0) { if (!process->target_xml) { - GDBRegisterState *r; g_autoptr(GPtrArray) xml =3D g_ptr_array_new_with_free_func(g_= free); =20 g_ptr_array_add( @@ -380,18 +380,12 @@ static const char *get_feature_xml(const char *p, con= st char **newp, g_markup_printf_escaped("%s", cc->gdb_arch_name(cpu))); } - g_ptr_array_add( - xml, - g_markup_printf_escaped("", - cc->gdb_core_xml_file)); - if (cpu->gdb_regs) { - for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { - r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, = i); - g_ptr_array_add( - xml, - g_markup_printf_escaped("", - r->feature->xmlname)); - } + for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { + r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + g_ptr_array_add( + xml, + g_markup_printf_escaped("", + r->feature->xmlname)); } g_ptr_array_add(xml, g_strdup("")); g_ptr_array_add(xml, NULL); @@ -400,20 +394,11 @@ static const char *get_feature_xml(const char *p, con= st char **newp, } return process->target_xml; } - /* Is it dynamically generated by the target? */ - if (cc->gdb_get_dynamic_xml) { - g_autofree char *xmlname =3D g_strndup(p, len); - const char *xml =3D cc->gdb_get_dynamic_xml(cpu, xmlname); - if (xml) { - return xml; - } - } - /* Is it one of the encoded gdb-xml/ files? */ - for (int i =3D 0; gdb_static_features[i].xmlname; i++) { - const char *name =3D gdb_static_features[i].xmlname; - if ((strncmp(name, p, len) =3D=3D 0) && - strlen(name) =3D=3D len) { - return gdb_static_features[i].xml; + /* Is it one of the features? */ + for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { + r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + if (strncmp(p, r->feature->xmlname, len) =3D=3D 0) { + return r->feature->xml; } } =20 @@ -508,12 +493,10 @@ static int gdb_read_register(CPUState *cpu, GByteArra= y *buf, int reg) return cc->gdb_read_register(cpu, buf, reg); } =20 - if (cpu->gdb_regs) { - for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { - r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (r->base_reg <=3D reg && reg < r->base_reg + r->feature->nu= m_regs) { - return r->get_reg(cpu, buf, reg - r->base_reg); - } + for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { + r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + if (r->base_reg <=3D reg && reg < r->base_reg + r->feature->num_re= gs) { + return r->get_reg(cpu, buf, reg - r->base_reg); } } return 0; @@ -528,51 +511,70 @@ static int gdb_write_register(CPUState *cpu, uint8_t = *mem_buf, int reg) return cc->gdb_write_register(cpu, mem_buf, reg); } =20 - if (cpu->gdb_regs) { - for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { - r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (r->base_reg <=3D reg && reg < r->base_reg + r->feature->nu= m_regs) { - return r->set_reg(cpu, mem_buf, reg - r->base_reg); - } + for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { + r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + if (r->base_reg <=3D reg && reg < r->base_reg + r->feature->num_re= gs) { + return r->set_reg(cpu, mem_buf, reg - r->base_reg); } } return 0; } =20 +static void gdb_register_feature(CPUState *cpu, int base_reg, + gdb_get_reg_cb get_reg, gdb_set_reg_cb se= t_reg, + const GDBFeature *feature) +{ + GDBRegisterState s =3D { + .base_reg =3D base_reg, + .get_reg =3D get_reg, + .set_reg =3D set_reg, + .feature =3D feature + }; + + g_array_append_val(cpu->gdb_regs, s); +} + +void gdb_init_cpu(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + const GDBFeature *feature; + + cpu->gdb_regs =3D g_array_new(false, false, sizeof(GDBRegisterState)); + + if (cc->gdb_core_xml_file) { + feature =3D gdb_find_static_feature(cc->gdb_core_xml_file); + gdb_register_feature(cpu, 0, + cc->gdb_read_register, cc->gdb_write_register, + feature); + } + + cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D cc->gdb_num_core_regs; +} + void gdb_register_coprocessor(CPUState *cpu, gdb_get_reg_cb get_reg, gdb_set_reg_cb set_r= eg, const GDBFeature *feature, int g_pos) { GDBRegisterState *s; guint i; + int base_reg =3D cpu->gdb_num_regs; =20 - if (cpu->gdb_regs) { - for (i =3D 0; i < cpu->gdb_regs->len; i++) { - /* Check for duplicates. */ - s =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (s->feature =3D=3D feature) { - return; - } + for (i =3D 0; i < cpu->gdb_regs->len; i++) { + /* Check for duplicates. */ + s =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + if (s->feature =3D=3D feature) { + return; } - } else { - cpu->gdb_regs =3D g_array_new(false, false, sizeof(GDBRegisterStat= e)); - i =3D 0; } =20 - g_array_set_size(cpu->gdb_regs, i + 1); - s =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - s->base_reg =3D cpu->gdb_num_regs; - s->get_reg =3D get_reg; - s->set_reg =3D set_reg; - s->feature =3D feature; + gdb_register_feature(cpu, base_reg, get_reg, set_reg, feature); =20 /* Add to end of list. */ cpu->gdb_num_regs +=3D feature->num_regs; if (g_pos) { - if (g_pos !=3D s->base_reg) { + if (g_pos !=3D base_reg) { error_report("Error: Bad gdb register numbering for '%s', " - "expected %d got %d", feature->xml, - g_pos, s->base_reg); + "expected %d got %d", feature->xml, g_pos, base_r= eg); } else { cpu->gdb_num_g_regs =3D cpu->gdb_num_regs; } diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 82dae51a550..cd7903ba6e7 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -27,6 +27,7 @@ #include "qemu/main-loop.h" #include "exec/log.h" #include "exec/cpu-common.h" +#include "exec/gdbstub.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" #include "sysemu/tcg.h" @@ -238,11 +239,10 @@ static void cpu_common_unrealizefn(DeviceState *dev) static void cpu_common_initfn(Object *obj) { CPUState *cpu =3D CPU(obj); - CPUClass *cc =3D CPU_GET_CLASS(obj); =20 + gdb_init_cpu(cpu); cpu->cpu_index =3D UNASSIGNED_CPU_INDEX; cpu->cluster_index =3D UNASSIGNED_CLUSTER_INDEX; - cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D cc->gdb_num_core_regs; /* user-mode doesn't have configurable SMP topology */ /* the default value is changed by qemu_init_vcpu() for system-mode */ cpu->nr_cores =3D 1; @@ -262,6 +262,7 @@ static void cpu_common_finalize(Object *obj) { CPUState *cpu =3D CPU(obj); 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Thu, 21 Dec 2023 02:47:05 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 32/40] gdbstub: Infer number of core registers from XML Date: Thu, 21 Dec 2023 10:38:10 +0000 Message-Id: <20231221103818.1633766-33-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703156209507100001 From: Akihiko Odaki GDBFeature has the num_regs member so use it where applicable to remove magic numbers. Signed-off-by: Akihiko Odaki Message-Id: <20231213-gdb-v17-8-777047380591@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- include/hw/core/cpu.h | 3 ++- target/s390x/cpu.h | 2 -- gdbstub/gdbstub.c | 5 ++++- target/arm/cpu.c | 1 - target/arm/cpu64.c | 1 - target/avr/cpu.c | 1 - target/hexagon/cpu.c | 1 - target/i386/cpu.c | 2 -- target/loongarch/cpu.c | 2 -- target/m68k/cpu.c | 1 - target/microblaze/cpu.c | 1 - target/riscv/cpu.c | 1 - target/rx/cpu.c | 1 - target/s390x/cpu.c | 1 - 14 files changed, 6 insertions(+), 17 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c0c8320413e..a6214610603 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -127,7 +127,8 @@ struct SysemuCPUOps; * @gdb_adjust_breakpoint: Callback for adjusting the address of a * breakpoint. Used by AVR to handle a gdb mis-feature with * its Harvard architecture split code and data. - * @gdb_num_core_regs: Number of core registers accessible to GDB. + * @gdb_num_core_regs: Number of core registers accessible to GDB or 0 to = infer + * from @gdb_core_xml_file. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top * before the insn which triggers a watchpoint rather than after= it. diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index fa3aac4f973..2d81fbfea5c 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -491,8 +491,6 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState *= env, vaddr *pc, #define S390_R13_REGNUM 15 #define S390_R14_REGNUM 16 #define S390_R15_REGNUM 17 -/* Total Core Registers. */ -#define S390_NUM_CORE_REGS 18 =20 static inline void setcc(S390CPU *cpu, uint64_t cc) { diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 1d5c1da1b24..801eba9a0b0 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -546,9 +546,12 @@ void gdb_init_cpu(CPUState *cpu) gdb_register_feature(cpu, 0, cc->gdb_read_register, cc->gdb_write_register, feature); + cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D feature->num_regs; } =20 - cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D cc->gdb_num_core_regs; + if (cc->gdb_num_core_regs) { + cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D cc->gdb_num_core_reg= s; + } } =20 void gdb_register_coprocessor(CPUState *cpu, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 650e09b29c5..0a02d16220b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2498,7 +2498,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &arm_sysemu_ops; #endif - cc->gdb_num_core_regs =3D 26; cc->gdb_arch_name =3D arm_gdb_arch_name; cc->gdb_get_dynamic_xml =3D arm_gdb_get_dynamic_xml; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8e30a7993ea..869d8dd24ee 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -793,7 +793,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, voi= d *data) =20 cc->gdb_read_register =3D aarch64_cpu_gdb_read_register; cc->gdb_write_register =3D aarch64_cpu_gdb_write_register; - cc->gdb_num_core_regs =3D 34; cc->gdb_core_xml_file =3D "aarch64-core.xml"; cc->gdb_arch_name =3D aarch64_gdb_arch_name; =20 diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 999c010dedb..4bab9e22728 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -251,7 +251,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; cc->gdb_adjust_breakpoint =3D avr_cpu_gdb_adjust_breakpoint; - cc->gdb_num_core_regs =3D 35; cc->gdb_core_xml_file =3D "avr-cpu.xml"; cc->tcg_ops =3D &avr_tcg_ops; } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 65ac9c75ad0..71678ef9c67 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -384,7 +384,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void= *data) cc->get_pc =3D hexagon_cpu_get_pc; cc->gdb_read_register =3D hexagon_gdb_read_register; cc->gdb_write_register =3D hexagon_gdb_write_register; - cc->gdb_num_core_regs =3D TOTAL_PER_THREAD_REGS; cc->gdb_stop_before_watchpoint =3D true; cc->gdb_core_xml_file =3D "hexagon-core.xml"; cc->disas_set_info =3D hexagon_cpu_disas_set_info; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 95d5f16cd5e..b14c97169cd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7969,10 +7969,8 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) cc->gdb_arch_name =3D x86_gdb_arch_name; #ifdef TARGET_X86_64 cc->gdb_core_xml_file =3D "i386-64bit.xml"; - cc->gdb_num_core_regs =3D 66; #else cc->gdb_core_xml_file =3D "i386-32bit.xml"; - cc->gdb_num_core_regs =3D 50; #endif cc->disas_set_info =3D x86_disas_set_info; =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index b26187dfdeb..6f05bf5aed7 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -849,7 +849,6 @@ static void loongarch32_cpu_class_init(ObjectClass *c, = void *data) { CPUClass *cc =3D CPU_CLASS(c); =20 - cc->gdb_num_core_regs =3D 35; cc->gdb_core_xml_file =3D "loongarch-base32.xml"; cc->gdb_arch_name =3D loongarch32_gdb_arch_name; } @@ -863,7 +862,6 @@ static void loongarch64_cpu_class_init(ObjectClass *c, = void *data) { CPUClass *cc =3D CPU_CLASS(c); =20 - cc->gdb_num_core_regs =3D 35; cc->gdb_core_xml_file =3D "loongarch-base64.xml"; cc->gdb_arch_name =3D loongarch64_gdb_arch_name; } diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 11c7e0a7902..a27194b2a59 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -564,7 +564,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 - cc->gdb_num_core_regs =3D 18; cc->tcg_ops =3D &m68k_tcg_ops; } =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 1998f69828f..9d3fbfe1592 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -428,7 +428,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); - cc->gdb_num_core_regs =3D 32 + 25; cc->gdb_core_xml_file =3D "microblaze-core.xml"; =20 cc->disas_set_info =3D mb_disas_set_info; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 673e937a5d8..a3a98230ca8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1688,7 +1688,6 @@ static void riscv_cpu_common_class_init(ObjectClass *= c, void *data) cc->get_pc =3D riscv_cpu_get_pc; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; cc->gdb_write_register =3D riscv_cpu_gdb_write_register; - cc->gdb_num_core_regs =3D 33; cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 9cc9d9d15ec..cf11b189116 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -231,7 +231,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->disas_set_info =3D rx_cpu_disas_set_info; =20 - cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "rx-core.xml"; cc->tcg_ops =3D &rx_tcg_ops; } diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 6acfa1c91b2..6fba9497295 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -362,7 +362,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) s390_cpu_class_init_sysemu(cc); #endif cc->disas_set_info =3D s390_cpu_disas_set_info; - cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; cc->gdb_core_xml_file =3D "s390x-core64.xml"; cc->gdb_arch_name =3D s390_gdb_arch_name; =20 --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155931; cv=none; d=zohomail.com; s=zohoarc; b=KQvyyvNgn8PZKRj6yv1a2NVVI5gXZurh2OqWB5IVUZrQzCQdXk4FgivbjkNcdo2WFPdCXgS0L/Sj8NIOSqhfpa8IkEKsjOq5eQshuWbo4nSZROTau2/3WDs1r+iv6mYwkSGM/oNj/8ImNkU2y2O6zgbwYdZQyuNRpF1/FFBi7PE= ARC-Message-Signature: i=1; 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Thu, 21 Dec 2023 02:46:59 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 33/40] hw/core/cpu: Remove gdb_get_dynamic_xml member Date: Thu, 21 Dec 2023 10:38:11 +0000 Message-Id: <20231221103818.1633766-34-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155931964100001 From: Akihiko Odaki This function is no longer used. Signed-off-by: Akihiko Odaki Reviewed-by: Alex Benn=C3=A9e Message-Id: <20231213-gdb-v17-9-777047380591@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- include/hw/core/cpu.h | 4 ---- target/arm/cpu.h | 6 ------ target/ppc/cpu.h | 1 - target/arm/cpu.c | 1 - target/arm/gdbstub.c | 18 ------------------ target/ppc/cpu_init.c | 3 --- target/ppc/gdbstub.c | 10 ---------- target/riscv/cpu.c | 14 -------------- 8 files changed, 57 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index a6214610603..17f99adc0f4 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -134,9 +134,6 @@ struct SysemuCPUOps; * before the insn which triggers a watchpoint rather than after= it. * @gdb_arch_name: Optional callback that returns the architecture name kn= own * to GDB. The caller must free the returned string with g_free. - * @gdb_get_dynamic_xml: Callback to return dynamically generated XML for = the - * gdb stub. Returns a pointer to the XML contents for the specified XML= file - * or NULL if the CPU doesn't have a dynamically generated content for i= t. * @disas_set_info: Setup architecture specific components of disassembly = info * @adjust_watchpoint_address: Perform a target-specific adjustment to an * address before attempting to match it against watchpoints. @@ -167,7 +164,6 @@ struct CPUClass { =20 const char *gdb_core_xml_file; const gchar * (*gdb_arch_name)(CPUState *cpu); - const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); =20 void (*disas_set_info)(CPUState *cpu, disassemble_info *info); =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b2f8ac81f06..c8e77440f0f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1182,12 +1182,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *c= pu, vaddr addr, int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 -/* Returns the dynamically generated XML for the gdb stub. - * Returns a pointer to the XML contents for the specified XML file or NULL - * if the XML name doesn't match the predefined one. - */ -const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname); - int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s); int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f87c26f98a6..9f94282e13e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1524,7 +1524,6 @@ int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t= *buf, int reg); int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg); #ifndef CONFIG_USER_ONLY hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name); #endif int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0a02d16220b..9514edaf041 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2499,7 +2499,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_arch_name =3D arm_gdb_arch_name; - cc->gdb_get_dynamic_xml =3D arm_gdb_get_dynamic_xml; cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D arm_disas_set_info; =20 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 059d84f98e5..a3bb73cfa7c 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -474,24 +474,6 @@ static GDBFeature *arm_gen_dynamic_m_secextreg_feature= (CPUState *cs, #endif #endif /* CONFIG_TCG */ =20 -const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - - if (strcmp(xmlname, "system-registers.xml") =3D=3D 0) { - return cpu->dyn_sysreg_feature.desc.xml; - } else if (strcmp(xmlname, "sve-registers.xml") =3D=3D 0) { - return cpu->dyn_svereg_feature.desc.xml; - } else if (strcmp(xmlname, "arm-m-system.xml") =3D=3D 0) { - return cpu->dyn_m_systemreg_feature.desc.xml; -#ifndef CONFIG_USER_ONLY - } else if (strcmp(xmlname, "arm-m-secext.xml") =3D=3D 0) { - return cpu->dyn_m_secextreg_feature.desc.xml; -#endif - } - return NULL; -} - void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) { CPUState *cs =3D CPU(cpu); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index a0178c3ce80..909d753b022 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7380,9 +7380,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void = *data) #endif =20 cc->gdb_num_core_regs =3D 71; -#ifndef CONFIG_USER_ONLY - cc->gdb_get_dynamic_xml =3D ppc_gdb_get_dynamic_xml; -#endif #ifdef USE_APPLE_GDB cc->gdb_read_register =3D ppc_cpu_gdb_read_register_apple; cc->gdb_write_register =3D ppc_cpu_gdb_write_register_apple; diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 8ca37b6bf95..f47878a67bd 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -342,16 +342,6 @@ static void gdb_gen_spr_feature(CPUState *cs) =20 gdb_feature_builder_end(&builder); } - -const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name) -{ - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cs); - - if (strcmp(xml_name, "power-spr.xml") =3D=3D 0) { - return pcc->gdb_spr.xml; - } - return NULL; -} #endif =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a3a98230ca8..1e3ac556b33 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1529,19 +1529,6 @@ static const gchar *riscv_gdb_arch_name(CPUState *cs) } } =20 -static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xml= name) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - - if (strcmp(xmlname, "riscv-csr.xml") =3D=3D 0) { - return cpu->dyn_csr_feature.xml; - } else if (strcmp(xmlname, "riscv-vector.xml") =3D=3D 0) { - return cpu->dyn_vreg_feature.xml; - } - - return NULL; -} - #ifndef CONFIG_USER_ONLY static int64_t riscv_get_arch_id(CPUState *cs) { @@ -1695,7 +1682,6 @@ static void riscv_cpu_common_class_init(ObjectClass *= c, void *data) cc->get_arch_id =3D riscv_get_arch_id; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; - cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; =20 object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, cpu_set_mvendorid, NULL, NULL); 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 34/40] gdbstub: Add members to identify registers to GDBFeature Date: Thu, 21 Dec 2023 10:38:12 +0000 Message-Id: <20231221103818.1633766-35-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703156203427100003 From: Akihiko Odaki These members will be used to help plugins to identify registers. The added members in instances of GDBFeature dynamically generated by CPUs will be filled in later changes. Signed-off-by: Akihiko Odaki Message-Id: <20231213-gdb-v17-10-777047380591@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- include/exec/gdbstub.h | 3 +++ gdbstub/gdbstub.c | 12 +++++++++--- target/riscv/gdbstub.c | 4 +--- scripts/feature_to_c.py | 14 +++++++++++++- 4 files changed, 26 insertions(+), 7 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index 82a8afa237f..da9ddfe54c5 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -13,12 +13,15 @@ typedef struct GDBFeature { const char *xmlname; const char *xml; + const char *name; + const char * const *regs; int num_regs; } GDBFeature; =20 typedef struct GDBFeatureBuilder { GDBFeature *feature; GPtrArray *xml; + GPtrArray *regs; int base_reg; } GDBFeatureBuilder; =20 diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 801eba9a0b0..420ab2a3766 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -419,9 +419,10 @@ void gdb_feature_builder_init(GDBFeatureBuilder *build= er, GDBFeature *feature, builder->feature =3D feature; builder->xml =3D g_ptr_array_new(); g_ptr_array_add(builder->xml, header); + builder->regs =3D g_ptr_array_new(); builder->base_reg =3D base_reg; feature->xmlname =3D xmlname; - feature->num_regs =3D 0; + feature->name =3D name; } =20 void gdb_feature_builder_append_tag(const GDBFeatureBuilder *builder, @@ -440,10 +441,12 @@ void gdb_feature_builder_append_reg(const GDBFeatureB= uilder *builder, const char *type, const char *group) { - if (builder->feature->num_regs < regnum) { - builder->feature->num_regs =3D regnum; + if (builder->regs->len <=3D regnum) { + g_ptr_array_set_size(builder->regs, regnum + 1); } =20 + builder->regs->pdata[regnum] =3D (gpointer *)name; + if (group) { gdb_feature_builder_append_tag( builder, @@ -469,6 +472,9 @@ void gdb_feature_builder_end(const GDBFeatureBuilder *b= uilder) } =20 g_ptr_array_free(builder->xml, TRUE); + + builder->feature->num_regs =3D builder->regs->len; + builder->feature->regs =3D (void *)g_ptr_array_free(builder->regs, FAL= SE); } =20 const GDBFeature *gdb_find_static_feature(const char *xmlname) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 68d0fdc1fd6..d9b52ffd09b 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -266,11 +266,9 @@ static GDBFeature *riscv_gen_dynamic_csr_feature(CPUSt= ate *cs, int base_reg) } predicate =3D csr_ops[i].predicate; if (predicate && (predicate(env, i) =3D=3D RISCV_EXCP_NONE)) { - g_autofree char *dynamic_name =3D NULL; name =3D csr_ops[i].name; if (!name) { - dynamic_name =3D g_strdup_printf("csr%03x", i); - name =3D dynamic_name; + name =3D g_strdup_printf("csr%03x", i); } =20 gdb_feature_builder_append_reg(&builder, name, bitsize, i, diff --git a/scripts/feature_to_c.py b/scripts/feature_to_c.py index e04d6b2df7f..807af0e685c 100644 --- a/scripts/feature_to_c.py +++ b/scripts/feature_to_c.py @@ -50,7 +50,9 @@ def writeliteral(indent, bytes): sys.stderr.write(f'unexpected start tag: {element.tag}\n') exit(1) =20 + feature_name =3D element.attrib['name'] regnum =3D 0 + regnames =3D [] regnums =3D [] tags =3D ['feature'] for event, element in events: @@ -67,6 +69,7 @@ def writeliteral(indent, bytes): if 'regnum' in element.attrib: regnum =3D int(element.attrib['regnum']) =20 + regnames.append(element.attrib['name']) regnums.append(regnum) regnum +=3D 1 =20 @@ -85,6 +88,15 @@ def writeliteral(indent, bytes): writeliteral(8, bytes(os.path.basename(input), 'utf-8')) sys.stdout.write(',\n') writeliteral(8, read) - sys.stdout.write(f',\n {num_regs},\n }},\n') + sys.stdout.write(',\n') + writeliteral(8, bytes(feature_name, 'utf-8')) + sys.stdout.write(',\n (const char * const []) {\n') + + for index, regname in enumerate(regnames): + sys.stdout.write(f' [{regnums[index] - base_reg}] =3D\n= ') + writeliteral(16, bytes(regname, 'utf-8')) + sys.stdout.write(',\n') + + sys.stdout.write(f' }},\n {num_regs},\n }},\n') =20 sys.stdout.write(' { NULL }\n};\n') --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 35/40] plugins: Use different helpers when reading registers Date: Thu, 21 Dec 2023 10:38:13 +0000 Message-Id: <20231221103818.1633766-36-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155781059100001 From: Akihiko Odaki This avoids optimizations incompatible when reading registers. Signed-off-by: Akihiko Odaki Message-Id: <20231213-gdb-v17-12-777047380591@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- accel/tcg/plugin-helpers.h | 3 ++- include/qemu/plugin.h | 1 + accel/tcg/plugin-gen.c | 43 ++++++++++++++++++++++++++++++++++---- plugins/api.c | 12 +++++++++-- 4 files changed, 52 insertions(+), 7 deletions(-) diff --git a/accel/tcg/plugin-helpers.h b/accel/tcg/plugin-helpers.h index 8e685e06545..11796436f35 100644 --- a/accel/tcg/plugin-helpers.h +++ b/accel/tcg/plugin-helpers.h @@ -1,4 +1,5 @@ #ifdef CONFIG_PLUGIN -DEF_HELPER_FLAGS_2(plugin_vcpu_udata_cb, TCG_CALL_NO_RWG | TCG_CALL_PLUGIN= , void, i32, ptr) +DEF_HELPER_FLAGS_2(plugin_vcpu_udata_cb_no_wg, TCG_CALL_NO_WG | TCG_CALL_P= LUGIN, void, i32, ptr) +DEF_HELPER_FLAGS_2(plugin_vcpu_udata_cb_no_rwg, TCG_CALL_NO_RWG | TCG_CALL= _PLUGIN, void, i32, ptr) DEF_HELPER_FLAGS_4(plugin_vcpu_mem_cb, TCG_CALL_NO_RWG | TCG_CALL_PLUGIN, = void, i32, i32, i64, ptr) #endif diff --git a/include/qemu/plugin.h b/include/qemu/plugin.h index 7fdc3a4849f..b0c5ac68293 100644 --- a/include/qemu/plugin.h +++ b/include/qemu/plugin.h @@ -73,6 +73,7 @@ enum plugin_dyn_cb_type { =20 enum plugin_dyn_cb_subtype { PLUGIN_CB_REGULAR, + PLUGIN_CB_REGULAR_R, PLUGIN_CB_INLINE, PLUGIN_N_CB_SUBTYPES, }; diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 78b331b2510..b37ce7683e6 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -79,6 +79,7 @@ enum plugin_gen_from { =20 enum plugin_gen_cb { PLUGIN_GEN_CB_UDATA, + PLUGIN_GEN_CB_UDATA_R, PLUGIN_GEN_CB_INLINE, PLUGIN_GEN_CB_MEM, PLUGIN_GEN_ENABLE_MEM_HELPER, @@ -90,7 +91,10 @@ enum plugin_gen_cb { * These helpers are stubs that get dynamically switched out for calls * direct to the plugin if they are subscribed to. */ -void HELPER(plugin_vcpu_udata_cb)(uint32_t cpu_index, void *udata) +void HELPER(plugin_vcpu_udata_cb_no_wg)(uint32_t cpu_index, void *udata) +{ } + +void HELPER(plugin_vcpu_udata_cb_no_rwg)(uint32_t cpu_index, void *udata) { } =20 void HELPER(plugin_vcpu_mem_cb)(unsigned int vcpu_index, @@ -98,7 +102,7 @@ void HELPER(plugin_vcpu_mem_cb)(unsigned int vcpu_index, void *userdata) { } =20 -static void gen_empty_udata_cb(void) +static void gen_empty_udata_cb(void (*gen_helper)(TCGv_i32, TCGv_ptr)) { TCGv_i32 cpu_index =3D tcg_temp_ebb_new_i32(); TCGv_ptr udata =3D tcg_temp_ebb_new_ptr(); @@ -106,12 +110,22 @@ static void gen_empty_udata_cb(void) tcg_gen_movi_ptr(udata, 0); tcg_gen_ld_i32(cpu_index, tcg_env, -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)= ); - gen_helper_plugin_vcpu_udata_cb(cpu_index, udata); + gen_helper(cpu_index, udata); =20 tcg_temp_free_ptr(udata); tcg_temp_free_i32(cpu_index); } =20 +static void gen_empty_udata_cb_no_wg(void) +{ + gen_empty_udata_cb(gen_helper_plugin_vcpu_udata_cb_no_wg); +} + +static void gen_empty_udata_cb_no_rwg(void) +{ + gen_empty_udata_cb(gen_helper_plugin_vcpu_udata_cb_no_rwg); +} + /* * For now we only support addi_i64. * When we support more ops, we can generate one empty inline cb for each. @@ -192,7 +206,8 @@ static void plugin_gen_empty_callback(enum plugin_gen_f= rom from) gen_empty_mem_helper); /* fall through */ case PLUGIN_GEN_FROM_TB: - gen_wrapped(from, PLUGIN_GEN_CB_UDATA, gen_empty_udata_cb); + gen_wrapped(from, PLUGIN_GEN_CB_UDATA, gen_empty_udata_cb_no_rwg); + gen_wrapped(from, PLUGIN_GEN_CB_UDATA_R, gen_empty_udata_cb_no_wg); gen_wrapped(from, PLUGIN_GEN_CB_INLINE, gen_empty_inline_cb); break; default: @@ -588,6 +603,12 @@ static void plugin_gen_tb_udata(const struct qemu_plug= in_tb *ptb, inject_udata_cb(ptb->cbs[PLUGIN_CB_REGULAR], begin_op); } =20 +static void plugin_gen_tb_udata_r(const struct qemu_plugin_tb *ptb, + TCGOp *begin_op) +{ + inject_udata_cb(ptb->cbs[PLUGIN_CB_REGULAR_R], begin_op); +} + static void plugin_gen_tb_inline(const struct qemu_plugin_tb *ptb, TCGOp *begin_op) { @@ -602,6 +623,14 @@ static void plugin_gen_insn_udata(const struct qemu_pl= ugin_tb *ptb, inject_udata_cb(insn->cbs[PLUGIN_CB_INSN][PLUGIN_CB_REGULAR], begin_op= ); } =20 +static void plugin_gen_insn_udata_r(const struct qemu_plugin_tb *ptb, + TCGOp *begin_op, int insn_idx) +{ + struct qemu_plugin_insn *insn =3D g_ptr_array_index(ptb->insns, insn_i= dx); + + inject_udata_cb(insn->cbs[PLUGIN_CB_INSN][PLUGIN_CB_REGULAR_R], begin_= op); +} + static void plugin_gen_insn_inline(const struct qemu_plugin_tb *ptb, TCGOp *begin_op, int insn_idx) { @@ -721,6 +750,9 @@ static void plugin_gen_inject(struct qemu_plugin_tb *pl= ugin_tb) case PLUGIN_GEN_CB_UDATA: plugin_gen_tb_udata(plugin_tb, op); break; + case PLUGIN_GEN_CB_UDATA_R: + plugin_gen_tb_udata_r(plugin_tb, op); + break; case PLUGIN_GEN_CB_INLINE: plugin_gen_tb_inline(plugin_tb, op); break; @@ -737,6 +769,9 @@ static void plugin_gen_inject(struct qemu_plugin_tb *pl= ugin_tb) case PLUGIN_GEN_CB_UDATA: plugin_gen_insn_udata(plugin_tb, op, insn_idx); break; + case PLUGIN_GEN_CB_UDATA_R: + plugin_gen_insn_udata_r(plugin_tb, op, insn_idx); + break; case PLUGIN_GEN_CB_INLINE: plugin_gen_insn_inline(plugin_tb, op, insn_idx); break; diff --git a/plugins/api.c b/plugins/api.c index 5521b0ad36c..ac39cdea0b3 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -89,7 +89,11 @@ void qemu_plugin_register_vcpu_tb_exec_cb(struct qemu_pl= ugin_tb *tb, void *udata) { if (!tb->mem_only) { - plugin_register_dyn_cb__udata(&tb->cbs[PLUGIN_CB_REGULAR], + int index =3D flags =3D=3D QEMU_PLUGIN_CB_R_REGS || + flags =3D=3D QEMU_PLUGIN_CB_RW_REGS ? + PLUGIN_CB_REGULAR_R : PLUGIN_CB_REGULAR; + + plugin_register_dyn_cb__udata(&tb->cbs[index], cb, flags, udata); } } @@ -109,7 +113,11 @@ void qemu_plugin_register_vcpu_insn_exec_cb(struct qem= u_plugin_insn *insn, void *udata) { if (!insn->mem_only) { - plugin_register_dyn_cb__udata(&insn->cbs[PLUGIN_CB_INSN][PLUGIN_CB= _REGULAR], + int index =3D flags =3D=3D QEMU_PLUGIN_CB_R_REGS || + flags =3D=3D QEMU_PLUGIN_CB_RW_REGS ? + PLUGIN_CB_REGULAR_R : PLUGIN_CB_REGULAR; + + plugin_register_dyn_cb__udata(&insn->cbs[PLUGIN_CB_INSN][index], cb, flags, udata); } } --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155526; cv=none; d=zohomail.com; s=zohoarc; b=cCjVuXWi4qhk2fjRpumWv5fdcdBbSqAzZ8nwpDM++YGm2gtaVEP9DnUO3/x7X0zDHF330AWbtDs//XvjZ6gEFOFUYTIiUlLL8pquf6GcV8jVVsBydEGo41O7awfMomZnrZfH9lA8iZ6jh1sTXj29+bZxAerVpP5XGHlD04ifjMo= ARC-Message-Signature: i=1; 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Thu, 21 Dec 2023 02:38:36 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 36/40] gdbstub: expose api to find registers Date: Thu, 21 Dec 2023 10:38:14 +0000 Message-Id: <20231221103818.1633766-37-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155527726100001 Expose an internal API to QEMU to return all the registers for a vCPU. The list containing the details required to called gdb_read_register(). Based-on: <20231025093128.33116-15-akihiko.odaki@daynix.com> Cc: Akihiko Odaki Signed-off-by: Alex Benn=C3=A9e --- v2 - just make gdb_get_register_list return everything for a vCPU vAJB: This principle difference is the find registers is a single call which can return a) multiple registers and b) is agnostic to the gdb feature. This is because I haven't so far found any duplicate registers in the system so I thing the regname by itself should be enough. However I do expose the gdb feature name in case the caller wants to do some additional filtering. --- include/exec/gdbstub.h | 47 +++++++++++++++++++++++++++++++++++ gdbstub/gdbstub.c | 56 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 102 insertions(+), 1 deletion(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index da9ddfe54c5..7bddea8259e 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -111,6 +111,53 @@ void gdb_feature_builder_end(const GDBFeatureBuilder *= builder); */ const GDBFeature *gdb_find_static_feature(const char *xmlname); =20 +/** + * gdb_find_feature() - Find a feature associated with a CPU. + * @cpu: The CPU associated with the feature. + * @name: The feature's name. + * + * Return: The feature's number. + */ +int gdb_find_feature(CPUState *cpu, const char *name); + +/** + * gdb_find_feature_register() - Find a register associated with a CPU. + * @cpu: The CPU associated with the register. + * @feature: The feature's number returned by gdb_find_feature(). + * @name: The register's name. + * + * Return: The register's number. + */ +int gdb_find_feature_register(CPUState *cpu, int feature, const char *name= ); + +/** + * gdb_read_register() - Read a register associated with a CPU. + * @cpu: The CPU associated with the register. + * @buf: The buffer that the read register will be appended to. + * @reg: The register's number returned by gdb_find_feature_register(). + * + * Return: The number of read bytes. + */ +int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); + +/** + * typedef GDBRegDesc - a register description from gdbstub + */ +typedef struct { + int gdb_reg; + const char *name; + const char *feature_name; +} GDBRegDesc; + +/** + * gdb_get_register_list() - Return list of all registers for CPU + * @cpu: The CPU being searched + * + * Returns a GArray of GDBRegDesc, caller frees array but not the + * const strings. + */ +GArray *gdb_get_register_list(CPUState *cpu); + void gdb_set_stop_cpu(CPUState *cpu); =20 /* in gdbstub-xml.c, generated by scripts/feature_to_c.py */ diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 420ab2a3766..b0230138246 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -490,7 +490,61 @@ const GDBFeature *gdb_find_static_feature(const char *= xmlname) g_assert_not_reached(); } =20 -static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) +int gdb_find_feature(CPUState *cpu, const char *name) +{ + GDBRegisterState *r; + + for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { + r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); + if (!strcmp(name, r->feature->name)) { + return i; + } + } + + return -1; +} + +int gdb_find_feature_register(CPUState *cpu, int feature, const char *name) +{ + GDBRegisterState *r; + + r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, feature); + + for (int i =3D 0; i < r->feature->num_regs; i++) { + if (r->feature->regs[i] && !strcmp(name, r->feature->regs[i])) { + return r->base_reg + i; + } + } + + return -1; +} + +GArray *gdb_get_register_list(CPUState *cpu) +{ + GArray *results =3D g_array_new(true, true, sizeof(GDBRegDesc)); + + /* registers are only available once the CPU is initialised */ + if (!cpu->gdb_regs) { + return results; + } + + for (int f =3D 0; f < cpu->gdb_regs->len; f++) { + GDBRegisterState *r =3D &g_array_index(cpu->gdb_regs, GDBRegisterS= tate, f); + for (int i =3D 0; i < r->feature->num_regs; i++) { + const char *name =3D r->feature->regs[i]; + GDBRegDesc desc =3D { + r->base_reg + i, + name, + r->feature->name + }; + g_array_append_val(results, desc); + } + } + + return results; +} + +int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { CPUClass *cc =3D CPU_GET_CLASS(cpu); GDBRegisterState *r; --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155407; cv=none; d=zohomail.com; s=zohoarc; b=CtruCZTSaVf+/mAktO6lExj2fARCq5yeVOxhUNYpdmSMC2/wFaP8X76gf/dALPK2VGAaGdcu79emtTE7u+P2ZMbz1IzzJo87pWJJVqlpxlBpeQHQ3fXwdzNWn9rXsSitZnjzBPY0ce7VWpDfywFhLmn6WB2JSFofOigQb7l5WqM= ARC-Message-Signature: i=1; a=rsa-sha256; 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Thu, 21 Dec 2023 02:38:36 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 37/40] plugins: add an API to read registers Date: Thu, 21 Dec 2023 10:38:15 +0000 Message-Id: <20231221103818.1633766-38-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155409008100001 We can only request a list of registers once the vCPU has been initialised so the user needs to use either call the get function on vCPU initialisation or during the translation phase. We don't expose the reg number to the plugin instead hiding it behind an opaque handle. This allows for a bit of future proofing should the internals need to be changed while also being hashed against the CPUClass so we can handle different register sets per-vCPU in hetrogenous situations. Having an internal state within the plugins also allows us to expand the interface in future (for example providing callbacks on register change if the translator can track changes). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1706 Cc: Akihiko Odaki Based-on: <20231025093128.33116-18-akihiko.odaki@daynix.com> Signed-off-by: Alex Benn=C3=A9e --- v2 - use new get whole list api, and expose upwards vAJB: The main difference to Akikio's version is hiding the gdb register detail from the plugin for the reasons described above. --- include/qemu/qemu-plugin.h | 53 +++++++++++++++++- plugins/api.c | 102 +++++++++++++++++++++++++++++++++++ plugins/qemu-plugins.symbols | 2 + 3 files changed, 155 insertions(+), 2 deletions(-) diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h index 4daab6efd29..e3b35c6ee81 100644 --- a/include/qemu/qemu-plugin.h +++ b/include/qemu/qemu-plugin.h @@ -11,6 +11,7 @@ #ifndef QEMU_QEMU_PLUGIN_H #define QEMU_QEMU_PLUGIN_H =20 +#include #include #include #include @@ -227,8 +228,8 @@ struct qemu_plugin_insn; * @QEMU_PLUGIN_CB_R_REGS: callback reads the CPU's regs * @QEMU_PLUGIN_CB_RW_REGS: callback reads and writes the CPU's regs * - * Note: currently unused, plugins cannot read or change system - * register state. + * Note: currently QEMU_PLUGIN_CB_RW_REGS is unused, plugins cannot change + * system register state. */ enum qemu_plugin_cb_flags { QEMU_PLUGIN_CB_NO_REGS, @@ -708,4 +709,52 @@ uint64_t qemu_plugin_end_code(void); QEMU_PLUGIN_API uint64_t qemu_plugin_entry_code(void); =20 +/** struct qemu_plugin_register - Opaque handle for a translated instructi= on */ +struct qemu_plugin_register; + +/** + * typedef qemu_plugin_reg_descriptor - register descriptions + * + * @name: register name + * @handle: opaque handle for retrieving value with qemu_plugin_read_regis= ter + * @feature: optional feature descriptor, can be NULL + */ +typedef struct { + char name[32]; + struct qemu_plugin_register *handle; + const char *feature; +} qemu_plugin_reg_descriptor; + +/** + * qemu_plugin_get_registers() - return register list for vCPU + * @vcpu_index: vcpu to query + * + * Returns a GArray of qemu_plugin_reg_descriptor or NULL. Caller + * frees the array (but not the const strings). + * + * As the register set of a given vCPU is only available once + * the vCPU is initialised if you want to monitor registers from the + * start you should call this from a qemu_plugin_register_vcpu_init_cb() + * callback. + */ +GArray * qemu_plugin_get_registers(unsigned int vcpu_index); + +/** + * qemu_plugin_read_register() - read register + * + * @vcpu: vcpu index + * @handle: a @qemu_plugin_reg_handle handle + * @buf: A GByteArray for the data owned by the plugin + * + * This function is only available in a context that register read access = is + * explicitly requested. + * + * Returns the size of the read register. The content of @buf is in target= byte + * order. On failure returns -1 + */ +int qemu_plugin_read_register(unsigned int vcpu, + struct qemu_plugin_register *handle, + GByteArray *buf); + + #endif /* QEMU_QEMU_PLUGIN_H */ diff --git a/plugins/api.c b/plugins/api.c index ac39cdea0b3..fc1f26e3440 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -8,6 +8,7 @@ * * qemu_plugin_tb * qemu_plugin_insn + * qemu_plugin_register * * Which can then be passed back into the API to do additional things. * As such all the public functions in here are exported in @@ -35,10 +36,12 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "qemu/plugin.h" #include "qemu/log.h" #include "tcg/tcg.h" #include "exec/exec-all.h" +#include "exec/gdbstub.h" #include "exec/ram_addr.h" #include "disas/disas.h" #include "plugin.h" @@ -435,3 +438,102 @@ uint64_t qemu_plugin_entry_code(void) #endif return entry; } + +/* + * Register handles + * + * The plugin infrastructure keeps hold of these internal data + * structures which are presented to plugins as opaque handles. They + * are global to the system and therefor additions to the hash table + * must be protected by the @reg_handle_lock. + * + * In order to future proof for up-coming heterogeneous work we want + * different entries for each CPU type while sharing them in the + * common case of multiple cores of the same type. + */ + +static QemuMutex reg_handle_lock; + +struct qemu_plugin_register { + const char *name; + int gdb_reg_num; +}; + +static GHashTable *reg_handles; /* hash table of PluginReg */ + +/* Generate a stable key - would xxhash be overkill? */ +static gpointer cpu_plus_reg_to_key(CPUState *cs, int gdb_regnum) +{ + uintptr_t key =3D (uintptr_t) cs->cc; + key ^=3D gdb_regnum; + return GUINT_TO_POINTER(key); +} + +/* + * Create register handles. + * + * We need to create a handle for each register so the plugin + * infrastructure can call gdbstub to read a register. We also + * construct a result array with those handles and some ancillary data + * the plugin might find useful. + */ + +static GArray * create_register_handles(CPUState *cs, GArray *gdbstub_regs= ) { + GArray *find_data =3D g_array_new(true, true, sizeof(qemu_plugin_reg_d= escriptor)); + + WITH_QEMU_LOCK_GUARD(®_handle_lock) { + + if (!reg_handles) { + reg_handles =3D g_hash_table_new(g_direct_hash, g_direct_equal= ); + } + + for (int i=3D0; i < gdbstub_regs->len; i++) { + GDBRegDesc *grd =3D &g_array_index(gdbstub_regs, GDBRegDesc, i= ); + gpointer key =3D cpu_plus_reg_to_key(cs, grd->gdb_reg); + struct qemu_plugin_register *val =3D g_hash_table_lookup(reg_h= andles, key); + + /* Doesn't exist, create one */ + if (!val) { + val =3D g_new0(struct qemu_plugin_register, 1); + val->gdb_reg_num =3D grd->gdb_reg; + val->name =3D grd->name; + + g_hash_table_insert(reg_handles, key, val); + } + + /* Create a record for the plugin */ + qemu_plugin_reg_descriptor desc =3D { + .handle =3D val, + .feature =3D g_intern_string(grd->feature_name) + }; + g_strlcpy(desc.name, val->name, sizeof(desc.name)); + g_array_append_val(find_data, desc); + } + } + + return find_data; +} + +GArray * qemu_plugin_get_registers(unsigned int vcpu) +{ + CPUState *cs =3D qemu_get_cpu(vcpu); + if (cs) { + g_autoptr(GArray) regs =3D gdb_get_register_list(cs); + return regs->len ? create_register_handles(cs, regs) : NULL; + } else { + return NULL; + } +} + +int qemu_plugin_read_register(unsigned int vcpu, struct qemu_plugin_regist= er *reg, GByteArray *buf) +{ + CPUState *cs =3D qemu_get_cpu(vcpu); + /* assert with debugging on? */ + return gdb_read_register(cs, buf, reg->gdb_reg_num); +} + +static void __attribute__((__constructor__)) qemu_api_init(void) +{ + qemu_mutex_init(®_handle_lock); + +} diff --git a/plugins/qemu-plugins.symbols b/plugins/qemu-plugins.symbols index 71f6c90549d..6963585c1ea 100644 --- a/plugins/qemu-plugins.symbols +++ b/plugins/qemu-plugins.symbols @@ -3,6 +3,7 @@ qemu_plugin_end_code; qemu_plugin_entry_code; qemu_plugin_get_hwaddr; + qemu_plugin_get_registers; qemu_plugin_hwaddr_device_name; qemu_plugin_hwaddr_is_io; qemu_plugin_hwaddr_phys_addr; @@ -20,6 +21,7 @@ qemu_plugin_n_vcpus; qemu_plugin_outs; qemu_plugin_path_to_binary; + qemu_plugin_read_register; qemu_plugin_register_atexit_cb; qemu_plugin_register_flush_cb; qemu_plugin_register_vcpu_exit_cb; --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155308; cv=none; d=zohomail.com; s=zohoarc; b=I0cmQh7o4OZPuClVpsRxr/Ef8/gwfxowqOXwrorAhBylnws4P2qnWs2mUpQX+x8/Ci6xuf1JotIbgdBhRKTnLNjSM05NyG9SczkV9ToaAZEu0LvJBq9WNyzMPdimnS9gD44Sv5waluyViJVRBphICibmAUWImSkFcWGezbrzVhQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Thu, 21 Dec 2023 02:38:38 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng Subject: [PATCH 38/40] contrib/plugins: fix imatch Date: Thu, 21 Dec 2023 10:38:16 +0000 Message-Id: <20231221103818.1633766-39-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155310394100003 We can't directly save the ephemeral imatch from argv as that memory will get recycled. Signed-off-by: Alex Benn=C3=A9e --- contrib/plugins/execlog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c index 82dc2f584e2..f262e5555eb 100644 --- a/contrib/plugins/execlog.c +++ b/contrib/plugins/execlog.c @@ -199,7 +199,7 @@ static void parse_insn_match(char *match) if (!imatches) { imatches =3D g_ptr_array_new(); } - g_ptr_array_add(imatches, match); + g_ptr_array_add(imatches, g_strdup(match)); } =20 static void parse_vaddr_match(char *match) --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703155502; cv=none; d=zohomail.com; s=zohoarc; b=QMBABnmQUOgj0ajFNddBcNhiNesRWuOW0br1QMociPVQvkDRHRTkzDzquGq6NzA7g/96qUT0Mb5N9ydcDonI5cPFW1Q+R0dkGCzhMCRiPkR16ox+EKfOkAxrzV+1NWPMKVvSO3eNGHZEqxoyFGiQFyfyn3wBobcFpXXL5pQ1BbY= ARC-Message-Signature: i=1; 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Thu, 21 Dec 2023 02:38:36 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng , Akihiko Odaki Subject: [PATCH 39/40] contrib/plugins: extend execlog to track register changes Date: Thu, 21 Dec 2023 10:38:17 +0000 Message-Id: <20231221103818.1633766-40-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155503634100007 With the new plugin register API we can now track changes to register values. Currently the implementation is fairly dumb which will slow down if a large number of register values are being tracked. This could be improved by only instrumenting instructions which mention registers we are interested in tracking. Example usage: ./qemu-aarch64 -D plugin.log -d plugin \ -cpu max,sve256=3Don \ -plugin contrib/plugins/libexeclog.so,reg=3Dsp,reg=3Dz\* \ ./tests/tcg/aarch64-linux-user/sha512-sve will display in the execlog any changes to the stack pointer (sp) and the SVE Z registers. Signed-off-by: Alex Benn=C3=A9e Cc: Akihiko Odaki Based-On: <20231025093128.33116-19-akihiko.odaki@daynix.com> --- v2 - we now do the glob-like search in the plugin itself. - fix some erroneous cpus->cpu vAJB: Changes for the new API with a simpler glob based "reg" specifier which can be specified multiple times. --- docs/devel/tcg-plugins.rst | 9 +- contrib/plugins/execlog.c | 189 ++++++++++++++++++++++++++++--------- 2 files changed, 153 insertions(+), 45 deletions(-) diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst index 81dcd43a612..3a0962723d7 100644 --- a/docs/devel/tcg-plugins.rst +++ b/docs/devel/tcg-plugins.rst @@ -497,6 +497,14 @@ arguments if required:: $ qemu-system-arm $(QEMU_ARGS) \ -plugin ./contrib/plugins/libexeclog.so,ifilter=3Dst1w,afilter=3D0x400= 01808 -d plugin =20 +This plugin can also dump registers when they change value. Specify the na= me of the +registers with multiple ``reg`` options. You can also use glob style match= ing if you wish:: + + $ qemu-system-arm $(QEMU_ARGS) \ + -plugin ./contrib/plugins/libexeclog.so,reg=3D\*_el2,reg=3Dsp -d plugin + +Be aware that each additional register to check will slow down execution q= uite considerably. + - contrib/plugins/cache.c =20 Cache modelling plugin that measures the performance of a given L1 cache @@ -583,4 +591,3 @@ The following API is generated from the inline document= ation in include the full kernel-doc annotations. =20 .. kernel-doc:: include/qemu/qemu-plugin.h - diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c index f262e5555eb..74fbf7c0e60 100644 --- a/contrib/plugins/execlog.c +++ b/contrib/plugins/execlog.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2021, Alexandre Iooss * - * Log instruction execution with memory access. + * Log instruction execution with memory access and register changes * * License: GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. @@ -15,30 +15,29 @@ =20 #include =20 +typedef struct { + struct qemu_plugin_register *handle; + GByteArray *last; + GByteArray *new; + const char *name; +} Register; + +typedef struct CPU { + /* Store last executed instruction on each vCPU as a GString */ + GString *last_exec; + /* Ptr array of Register */ + GPtrArray *registers; +} CPU; + QEMU_PLUGIN_EXPORT int qemu_plugin_version =3D QEMU_PLUGIN_VERSION; =20 -/* Store last executed instruction on each vCPU as a GString */ -static GPtrArray *last_exec; +static CPU *cpus; +static int num_cpus; static GRWLock expand_array_lock; =20 static GPtrArray *imatches; static GArray *amatches; - -/* - * Expand last_exec array. - * - * As we could have multiple threads trying to do this we need to - * serialise the expansion under a lock. - */ -static void expand_last_exec(int cpu_index) -{ - g_rw_lock_writer_lock(&expand_array_lock); - while (cpu_index >=3D last_exec->len) { - GString *s =3D g_string_new(NULL); - g_ptr_array_add(last_exec, s); - } - g_rw_lock_writer_unlock(&expand_array_lock); -} +static GPtrArray *rmatches; =20 /** * Add memory read or write information to current instruction log @@ -50,8 +49,8 @@ static void vcpu_mem(unsigned int cpu_index, qemu_plugin_= meminfo_t info, =20 /* Find vCPU in array */ g_rw_lock_reader_lock(&expand_array_lock); - g_assert(cpu_index < last_exec->len); - s =3D g_ptr_array_index(last_exec, cpu_index); + g_assert(cpu_index < num_cpus); + s =3D cpus[cpu_index].last_exec; g_rw_lock_reader_unlock(&expand_array_lock); =20 /* Indicate type of memory access */ @@ -77,28 +76,46 @@ static void vcpu_mem(unsigned int cpu_index, qemu_plugi= n_meminfo_t info, */ static void vcpu_insn_exec(unsigned int cpu_index, void *udata) { - GString *s; + CPU *cpu; =20 - /* Find or create vCPU in array */ g_rw_lock_reader_lock(&expand_array_lock); - if (cpu_index >=3D last_exec->len) { - g_rw_lock_reader_unlock(&expand_array_lock); - expand_last_exec(cpu_index); - g_rw_lock_reader_lock(&expand_array_lock); - } - s =3D g_ptr_array_index(last_exec, cpu_index); + g_assert(cpu_index < num_cpus); + cpu =3D &cpus[cpu_index]; g_rw_lock_reader_unlock(&expand_array_lock); =20 /* Print previous instruction in cache */ - if (s->len) { - qemu_plugin_outs(s->str); + if (cpu->last_exec->len) { + if (cpu->registers) { + for (int n =3D 0; n < cpu->registers->len; n++) { + Register *reg =3D cpu->registers->pdata[n]; + int sz; + + g_byte_array_set_size(reg->new, 0); + sz =3D qemu_plugin_read_register(cpu_index, reg->handle, r= eg->new); + g_assert(sz =3D=3D reg->last->len); + + if (memcmp(reg->last->data, reg->new->data, sz)) { + GByteArray *temp =3D reg->last; + g_string_append_printf(cpu->last_exec, ", %s -> ", reg= ->name); + /* TODO: handle BE properly */ + for (int i =3D sz; i >=3D 0; i--) { + g_string_append_printf(cpu->last_exec, "%02x", + reg->new->data[i]); + } + reg->last =3D reg->new; + reg->new =3D temp; + } + } + } + + qemu_plugin_outs(cpu->last_exec->str); qemu_plugin_outs("\n"); } =20 /* Store new instruction in cache */ /* vcpu_mem will add memory access information to last_exec */ - g_string_printf(s, "%u, ", cpu_index); - g_string_append(s, (char *)udata); + g_string_printf(cpus[cpu_index].last_exec, "%u, ", cpu_index); + g_string_append(cpus[cpu_index].last_exec, (char *)udata); } =20 /** @@ -167,8 +184,10 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct = qemu_plugin_tb *tb) QEMU_PLUGIN_MEM_RW, NULL); =20 /* Register callback on instruction */ - qemu_plugin_register_vcpu_insn_exec_cb(insn, vcpu_insn_exec, - QEMU_PLUGIN_CB_NO_REGS,= output); + qemu_plugin_register_vcpu_insn_exec_cb( + insn, vcpu_insn_exec, + rmatches ? QEMU_PLUGIN_CB_R_REGS : QEMU_PLUGIN_CB_NO_REGS, + output); =20 /* reset skip */ skip =3D (imatches || amatches); @@ -177,17 +196,86 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct= qemu_plugin_tb *tb) } } =20 +static Register *init_vcpu_register(int vcpu_index, + qemu_plugin_reg_descriptor *desc) +{ + Register *reg =3D g_new0(Register, 1); + int r; + + reg->handle =3D desc->handle; + reg->name =3D g_strdup(desc->name); + reg->last =3D g_byte_array_new(); + reg->new =3D g_byte_array_new(); + + /* read the initial value */ + r =3D qemu_plugin_read_register(vcpu_index, reg->handle, reg->last); + g_assert(r > 0); + return reg; +} + +static registers_init(int vcpu_index) +{ + GPtrArray *registers =3D g_ptr_array_new(); + g_autoptr(GArray) reg_list =3D qemu_plugin_get_registers(vcpu_index); + + if (reg_list && reg_list->len) { + /* + * Go through each register in the complete list and + * see if we want to track it. + */ + for (int r =3D 0; r < reg_list->len; r++) { + qemu_plugin_reg_descriptor *rd =3D &g_array_index( + reg_list, qemu_plugin_reg_descriptor, r); + for (int p =3D 0; p < rmatches->len; p++) { + g_autoptr(GPatternSpec) pat =3D g_pattern_spec_new(rmatche= s->pdata[p]); + if (g_pattern_match_string(pat, rd->name)) { + Register *reg =3D init_vcpu_register(vcpu_index, rd); + g_ptr_array_add(registers, reg); + } + } + } + } + cpus[num_cpus].registers =3D registers; +} + +/* + * Initialise a new vcpu/thread with: + * - last_exec tracking data + * - list of tracked registers + * - initial value of registers + * + * As we could have multiple threads trying to do this we need to + * serialise the expansion under a lock. + */ +static void vcpu_init(qemu_plugin_id_t id, unsigned int vcpu_index) +{ + g_rw_lock_writer_lock(&expand_array_lock); + + if (vcpu_index >=3D num_cpus) { + cpus =3D g_realloc_n(cpus, vcpu_index + 1, sizeof(*cpus)); + while (vcpu_index >=3D num_cpus) { + cpus[num_cpus].last_exec =3D g_string_new(NULL); + + /* Any registers to track? */ + if (rmatches && rmatches->len) { + registers_init(vcpu_index); + } + num_cpus++; + } + } + + g_rw_lock_writer_unlock(&expand_array_lock); +} + /** * On plugin exit, print last instruction in cache */ static void plugin_exit(qemu_plugin_id_t id, void *p) { guint i; - GString *s; - for (i =3D 0; i < last_exec->len; i++) { - s =3D g_ptr_array_index(last_exec, i); - if (s->str) { - qemu_plugin_outs(s->str); + for (i =3D 0; i < num_cpus; i++) { + if (cpus[i].last_exec->str) { + qemu_plugin_outs(cpus[i].last_exec->str); qemu_plugin_outs("\n"); } } @@ -212,6 +300,18 @@ static void parse_vaddr_match(char *match) g_array_append_val(amatches, v); } =20 +/* + * We have to wait until vCPUs are started before we can check the + * patterns find anything. + */ +static void add_regpat(char *regpat) +{ + if (!rmatches) { + rmatches =3D g_ptr_array_new(); + } + g_ptr_array_add(rmatches, g_strdup(regpat)); +} + /** * Install the plugin */ @@ -224,9 +324,7 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin_= id_t id, * we don't know the size before emulation. */ if (info->system_emulation) { - last_exec =3D g_ptr_array_sized_new(info->system.max_vcpus); - } else { - last_exec =3D g_ptr_array_new(); + cpus =3D g_new(CPU, info->system.max_vcpus); } =20 for (int i =3D 0; i < argc; i++) { @@ -236,13 +334,16 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugi= n_id_t id, parse_insn_match(tokens[1]); } else if (g_strcmp0(tokens[0], "afilter") =3D=3D 0) { parse_vaddr_match(tokens[1]); + } else if (g_strcmp0(tokens[0], "reg") =3D=3D 0) { + add_regpat(tokens[1]); } else { fprintf(stderr, "option parsing failed: %s\n", opt); return -1; } } =20 - /* Register translation block and exit callbacks */ + /* Register init, translation block and exit callbacks */ + qemu_plugin_register_vcpu_init_cb(id, vcpu_init); qemu_plugin_register_vcpu_tb_trans_cb(id, vcpu_tb_trans); qemu_plugin_register_atexit_cb(id, plugin_exit, NULL); =20 --=20 2.39.2 From nobody Tue Nov 26 22:32:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=wPcwMe/aQZUfTScU91eR7ZQQA1t73rNFBA5pycMFHXM=; b=WMNGUwWLstYgqwCV8m2RcozmJI8ZG2VqMRFq9yiDDhfS8EwH5jrazHGsYu0iAVP4Lg 9HtlblUMIfxYIym8whnQ/Hh8zGeBEZQJch7cs+aGZoanyCm26ZX7FxI+1f+h7RMMVmpy ld/hK5UNevXa1AdS0A3HLSoToUjQBSc1ZO1S+bz3cPGitETZ+Q6dE0w+7HFjlz2nMdkx +JgyIGaAgmxZD70XrG1CO/rzOjdas821kI6vBjgRew+a1mmf342jC3NPvLw9lwOvrtz6 7TVKJSEv6/8aUSSXLKgYPQHNVfHhDaj+8YV3hbKNGpgLZ87HNmoH3dnG/3+sYDZDrd06 Obfw== X-Gm-Message-State: AOJu0YzATifor682htTklUOSCp6OgDl6/fePNJwNp0JYU8yUjxKZ0MjB 6hhxfvP5x434RDzumLaCJeGgEw== X-Google-Smtp-Source: AGHT+IE8546czz735AiZejPhKxdXzg31gVzf4zfjyYmEvLR2oBlGdoqshy94sfwDCknOEIUfoDGEIA== X-Received: by 2002:adf:fd87:0:b0:336:817f:4033 with SMTP id d7-20020adffd87000000b00336817f4033mr709218wrr.92.1703155118551; Thu, 21 Dec 2023 02:38:38 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , John Snow , Aurelien Jarno , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , Brian Cain , Laurent Vivier , Palmer Dabbelt , Cleber Rosa , David Hildenbrand , Beraldo Leal , Pierrick Bouvier , Weiwei Li , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paul Durrant , qemu-s390x@nongnu.org, David Woodhouse , Liu Zhiwei , Ilya Leoshkevich , Wainer dos Santos Moschetta , Michael Rolnik , Alistair Francis , Daniel Henrique Barboza , Laurent Vivier , kvm@vger.kernel.org, =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Alexandre Iooss , Thomas Huth , Peter Maydell , qemu-ppc@nongnu.org, Paolo Bonzini , Marcel Apfelbaum , Nicholas Piggin , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Song Gao , Yoshinori Sato , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Mahmoud Mandour , Bin Meng Subject: [PATCH 40/40] contrib/plugins: optimise the register value tracking Date: Thu, 21 Dec 2023 10:38:18 +0000 Message-Id: <20231221103818.1633766-41-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231221103818.1633766-1-alex.bennee@linaro.org> References: <20231221103818.1633766-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703155330535100001 This adds an additional flag which attempts to optimise the register tracking by only instrumenting instructions which are likely to change its value. This relies on the disassembler showing up the register names in disassembly so is only enabled when asked for. Signed-off-by: Alex Benn=C3=A9e --- docs/devel/tcg-plugins.rst | 10 +- contrib/plugins/execlog.c | 189 ++++++++++++++++++++++++++++++------- 2 files changed, 165 insertions(+), 34 deletions(-) diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst index 3a0962723d7..fa7421279f5 100644 --- a/docs/devel/tcg-plugins.rst +++ b/docs/devel/tcg-plugins.rst @@ -503,7 +503,15 @@ registers with multiple ``reg`` options. You can also = use glob style matching if $ qemu-system-arm $(QEMU_ARGS) \ -plugin ./contrib/plugins/libexeclog.so,reg=3D\*_el2,reg=3Dsp -d plugin =20 -Be aware that each additional register to check will slow down execution q= uite considerably. +Be aware that each additional register to check will slow down +execution quite considerably. You can optimise the number of register +checks done by using the rdisas option. This will only instrument +instructions that mention the registers in question in disassembly. +This is not foolproof as some instructions implicitly change +instructions. You can use the ifilter to catch these cases: + + $ qemu-system-arm $(QEMU_ARGS) \ + -plugin ./contrib/plugins/libexeclog.so,ifilter=3Dmsr,ifilter=3Dblr,re= g=3Dx30,reg=3D\*_el1,rdisas=3Don =20 - contrib/plugins/cache.c =20 diff --git a/contrib/plugins/execlog.c b/contrib/plugins/execlog.c index 74fbf7c0e60..f88e5acab6c 100644 --- a/contrib/plugins/execlog.c +++ b/contrib/plugins/execlog.c @@ -27,6 +27,7 @@ typedef struct CPU { GString *last_exec; /* Ptr array of Register */ GPtrArray *registers; + int index; } CPU; =20 QEMU_PLUGIN_EXPORT int qemu_plugin_version =3D QEMU_PLUGIN_VERSION; @@ -38,6 +39,9 @@ static GRWLock expand_array_lock; static GPtrArray *imatches; static GArray *amatches; static GPtrArray *rmatches; +static bool disas_assist; +static GMutex add_reg_name_lock; +static GPtrArray *all_reg_names; =20 /** * Add memory read or write information to current instruction log @@ -72,9 +76,14 @@ static void vcpu_mem(unsigned int cpu_index, qemu_plugin= _meminfo_t info, } =20 /** - * Log instruction execution + * Log instruction execution, outputting the last one. + * + * vcpu_insn_exec() is a copy and paste of vcpu_insn_exec_with_regs() + * without the checking of register values when we've attempted to + * optimise with disas_assist. */ -static void vcpu_insn_exec(unsigned int cpu_index, void *udata) + +static CPU *get_cpu(int cpu_index) { CPU *cpu; =20 @@ -83,39 +92,87 @@ static void vcpu_insn_exec(unsigned int cpu_index, void= *udata) cpu =3D &cpus[cpu_index]; g_rw_lock_reader_unlock(&expand_array_lock); =20 + return cpu; +} + +static void insn_check_regs(CPU *cpu) { + for (int n =3D 0; n < cpu->registers->len; n++) { + Register *reg =3D cpu->registers->pdata[n]; + int sz; + + g_byte_array_set_size(reg->new, 0); + sz =3D qemu_plugin_read_register(cpu->index, reg->handle, reg->new= ); + g_assert(sz =3D=3D reg->last->len); + + if (memcmp(reg->last->data, reg->new->data, sz)) { + GByteArray *temp =3D reg->last; + g_string_append_printf(cpu->last_exec, ", %s -> ", reg->name); + /* TODO: handle BE properly */ + for (int i =3D sz; i >=3D 0; i--) { + g_string_append_printf(cpu->last_exec, "%02x", + reg->new->data[i]); + } + reg->last =3D reg->new; + reg->new =3D temp; + } + } +} + +/* Log last instruction while checking registers */ +static void vcpu_insn_exec_with_regs(unsigned int cpu_index, void *udata) +{ + CPU *cpu =3D get_cpu(cpu_index); + /* Print previous instruction in cache */ if (cpu->last_exec->len) { if (cpu->registers) { - for (int n =3D 0; n < cpu->registers->len; n++) { - Register *reg =3D cpu->registers->pdata[n]; - int sz; - - g_byte_array_set_size(reg->new, 0); - sz =3D qemu_plugin_read_register(cpu_index, reg->handle, r= eg->new); - g_assert(sz =3D=3D reg->last->len); - - if (memcmp(reg->last->data, reg->new->data, sz)) { - GByteArray *temp =3D reg->last; - g_string_append_printf(cpu->last_exec, ", %s -> ", reg= ->name); - /* TODO: handle BE properly */ - for (int i =3D sz; i >=3D 0; i--) { - g_string_append_printf(cpu->last_exec, "%02x", - reg->new->data[i]); - } - reg->last =3D reg->new; - reg->new =3D temp; - } - } + insn_check_regs(cpu); + } + + qemu_plugin_outs(cpu->last_exec->str); + qemu_plugin_outs("\n"); + } + + /* Store new instruction in cache */ + /* vcpu_mem will add memory access information to last_exec */ + g_string_printf(cpu->last_exec, "%u, ", cpu_index); + g_string_append(cpu->last_exec, (char *)udata); +} + +/* Log last instruction while checking registers, ignore next */ +static void vcpu_insn_exec_only_regs(unsigned int cpu_index, void *udata) +{ + CPU *cpu =3D get_cpu(cpu_index); + + /* Print previous instruction in cache */ + if (cpu->last_exec->len) { + if (cpu->registers) { + insn_check_regs(cpu); } =20 qemu_plugin_outs(cpu->last_exec->str); qemu_plugin_outs("\n"); } =20 + /* reset */ + cpu->last_exec->len =3D 0; +} + +/* Log last instruction without checking regs, setup next */ +static void vcpu_insn_exec(unsigned int cpu_index, void *udata) +{ + CPU *cpu =3D get_cpu(cpu_index); + + /* Print previous instruction in cache */ + if (cpu->last_exec->len) { + qemu_plugin_outs(cpu->last_exec->str); + qemu_plugin_outs("\n"); + } + /* Store new instruction in cache */ /* vcpu_mem will add memory access information to last_exec */ - g_string_printf(cpus[cpu_index].last_exec, "%u, ", cpu_index); - g_string_append(cpus[cpu_index].last_exec, (char *)udata); + g_string_printf(cpu->last_exec, "%u, ", cpu_index); + g_string_append(cpu->last_exec, (char *)udata); } =20 /** @@ -128,6 +185,8 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct q= emu_plugin_tb *tb) { struct qemu_plugin_insn *insn; bool skip =3D (imatches || amatches); + bool check_regs_this =3D rmatches; + bool check_regs_next =3D false; =20 size_t n =3D qemu_plugin_tb_n_insns(tb); for (size_t i =3D 0; i < n; i++) { @@ -148,7 +207,8 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct q= emu_plugin_tb *tb) /* * If we are filtering we better check out if we have any * hits. The skip "latches" so we can track memory accesses - * after the instruction we care about. + * after the instruction we care about. Also enable register + * checking on the next instruction. */ if (skip && imatches) { int j; @@ -156,6 +216,7 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct q= emu_plugin_tb *tb) char *m =3D g_ptr_array_index(imatches, j); if (g_str_has_prefix(insn_disas, m)) { skip =3D false; + check_regs_next =3D rmatches; } } } @@ -170,8 +231,38 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct = qemu_plugin_tb *tb) } } =20 + /* + * Check the disassembly to see if a register we care about + * will be affected by this instruction. This relies on the + * dissembler doing something sensible for the registers we + * care about. + */ + if (disas_assist && rmatches) { + check_regs_next =3D false; + gchar *args =3D g_strstr_len(insn_disas, -1, " "); + for (int n =3D 0; n < all_reg_names->len; n++) { + gchar *reg =3D g_ptr_array_index(all_reg_names, n); + if (g_strrstr(args, reg)) { + check_regs_next =3D true; + skip =3D false; + } + } + } + + /* + * We now have 3 choices: + * + * Log this instruction normally + * Log this instruction checking for register changes + * Don't log this instruction but check for register changes from = the last one + */ + if (skip) { - g_free(insn_disas); + if (check_regs_this) { + qemu_plugin_register_vcpu_insn_exec_cb(insn, + vcpu_insn_exec_only= _regs, + QEMU_PLUGIN_CB_R_RE= GS, NULL); + } } else { uint32_t insn_opcode; insn_opcode =3D *((uint32_t *)qemu_plugin_insn_data(insn)); @@ -184,15 +275,28 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct= qemu_plugin_tb *tb) QEMU_PLUGIN_MEM_RW, NULL); =20 /* Register callback on instruction */ - qemu_plugin_register_vcpu_insn_exec_cb( - insn, vcpu_insn_exec, - rmatches ? QEMU_PLUGIN_CB_R_REGS : QEMU_PLUGIN_CB_NO_REGS, - output); + if (check_regs_this) { + qemu_plugin_register_vcpu_insn_exec_cb( + insn, vcpu_insn_exec_with_regs, + QEMU_PLUGIN_CB_R_REGS, + output); + } else { + qemu_plugin_register_vcpu_insn_exec_cb( + insn, vcpu_insn_exec, + QEMU_PLUGIN_CB_NO_REGS, + output); + } =20 /* reset skip */ skip =3D (imatches || amatches); } =20 + /* set regs for next */ + if (disas_assist && rmatches) { + check_regs_this =3D check_regs_next; + } + + g_free(insn_disas); } } =20 @@ -200,10 +304,11 @@ static Register *init_vcpu_register(int vcpu_index, qemu_plugin_reg_descriptor *desc) { Register *reg =3D g_new0(Register, 1); + g_autofree gchar *lower =3D g_utf8_strdown(desc->name, -1); int r; =20 reg->handle =3D desc->handle; - reg->name =3D g_strdup(desc->name); + reg->name =3D g_intern_string(lower); reg->last =3D g_byte_array_new(); reg->new =3D g_byte_array_new(); =20 @@ -213,7 +318,7 @@ static Register *init_vcpu_register(int vcpu_index, return reg; } =20 -static registers_init(int vcpu_index) +static void registers_init(int vcpu_index) { GPtrArray *registers =3D g_ptr_array_new(); g_autoptr(GArray) reg_list =3D qemu_plugin_get_registers(vcpu_index); @@ -228,9 +333,20 @@ static registers_init(int vcpu_index) reg_list, qemu_plugin_reg_descriptor, r); for (int p =3D 0; p < rmatches->len; p++) { g_autoptr(GPatternSpec) pat =3D g_pattern_spec_new(rmatche= s->pdata[p]); - if (g_pattern_match_string(pat, rd->name)) { + g_autofree gchar *rd_lower =3D g_utf8_strdown(rd->name, -1= ); + if (g_pattern_match_string(pat, rd->name) || + g_pattern_match_string(pat, rd_lower)) { Register *reg =3D init_vcpu_register(vcpu_index, rd); g_ptr_array_add(registers, reg); + + /* we need a list of regnames at TB translation time */ + if (disas_assist) { + g_mutex_lock(&add_reg_name_lock); + if (!g_ptr_array_find(all_reg_names, reg->name, NU= LL)) { + g_ptr_array_add(all_reg_names, reg->name); + } + g_mutex_unlock(&add_reg_name_lock); + } } } } @@ -254,6 +370,7 @@ static void vcpu_init(qemu_plugin_id_t id, unsigned int= vcpu_index) if (vcpu_index >=3D num_cpus) { cpus =3D g_realloc_n(cpus, vcpu_index + 1, sizeof(*cpus)); while (vcpu_index >=3D num_cpus) { + cpus[num_cpus].index =3D vcpu_index; cpus[num_cpus].last_exec =3D g_string_new(NULL); =20 /* Any registers to track? */ @@ -336,6 +453,12 @@ QEMU_PLUGIN_EXPORT int qemu_plugin_install(qemu_plugin= _id_t id, parse_vaddr_match(tokens[1]); } else if (g_strcmp0(tokens[0], "reg") =3D=3D 0) { add_regpat(tokens[1]); + } else if (g_strcmp0(tokens[0], "rdisas") =3D=3D 0) { + if (!qemu_plugin_bool_parse(tokens[0], tokens[1], &disas_assis= t)) { + fprintf(stderr, "boolean argument parsing failed: %s\n", o= pt); + return -1; + } + all_reg_names =3D g_ptr_array_new(); } else { fprintf(stderr, "option parsing failed: %s\n", opt); return -1; --=20 2.39.2