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([172.58.139.164]) by smtp.gmail.com with ESMTPSA id n8-20020a05620a294800b0078116d55191sm360808qkp.130.2023.12.20.19.17.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 19:17:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703128638; x=1703733438; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QCu52KW/EDOsijWBXsGWXcmu8Q0OiP0WdLJKxsvxad0=; b=ZhIhUCQhKB9I+Lrmx7d4udyaH6Y84lON4KaCCyl3TyZbj2KrDjgq5BFKNHz+1m0Ro+ bZJ5ld9rhLiA26PYja/hvD+Qq0m5s0F8IrcpEpV4bhe3EaSH5sXyoK3e1ixjvtFLTEuQ 15lGuPYotSQp5woyb1pHCqalvxjh9bOHTKJd8jxfRRpQrJQqBokcxdVoln0tE019NWUV DJhzbo4//EZigsUpyP/18ZtMDlOZHJGzs/c1TygcaWYNEio6YIdvQzllum5rwrJiYsKA HXXtAf7e1ypIw8N+0t/PpUJn8xN3AxcA472E4mNgIP0hqe1ZtuThmOIYQr68sHHdQzJU ckMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703128638; x=1703733438; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QCu52KW/EDOsijWBXsGWXcmu8Q0OiP0WdLJKxsvxad0=; b=wC8r6sMQyzn7XQVcNsxlxK2Zdd00WjKO/ZHjKaOl6E4YbxeydV901W+2NKaLS1aFs7 I3vDw3r/IfnUKtDkDDTChg8ePsRr87VdiYQQz5e83Uo1nil24xWvrLbdJIqJE4SfAwwh u41TsT0NjliScDnTtyLeuRFx3gwKQ/effXdRSYFRO1+ZhLqPkf3UMcWcxxRHtcNL5YeV HD/FRldvQGs+ICsjW9LFM71AzWLy0HL6zr667cnfYni7tEugxPjqSqp9cGnR+0kw1Jv0 Go/z5OChMRMAIxDj65ru9XQ69q5aZR8uQMQ0SAgQFSR+Gw9BMplTQqy4m3X5wKYtLtJs Prjg== X-Gm-Message-State: AOJu0YwrvLt3d7GftP1MG13bdcUJ1K2xflBm4UoplevXSeIDsAzeZdA7 y/vkM/nDotqkxGUh2syEWswzOx/FQPF4Rv3p/KxIcmRM X-Google-Smtp-Source: AGHT+IEuEixtJ2a5jbFw2Y3UTK0vi/wi3STndqZ6SM06DjNiVfRzawda7vOaPEZ5eJFrAVYEmg98wQ== X-Received: by 2002:a05:620a:674:b0:781:1362:c89 with SMTP id a20-20020a05620a067400b0078113620c89mr1695017qkh.18.1703128637947; Wed, 20 Dec 2023 19:17:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 02/71] target/arm: Constify VMState in machine.c Date: Thu, 21 Dec 2023 14:15:43 +1100 Message-Id: <20231221031652.119827-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231221031652.119827-1-richard.henderson@linaro.org> References: <20231221031652.119827-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::732; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x732.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703128691393100001 Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/machine.c | 54 ++++++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index 9e20b41189..542be14bec 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -49,7 +49,7 @@ static const VMStateDescription vmstate_vfp =3D { .version_id =3D 3, .minimum_version_id =3D 3, .needed =3D vfp_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { /* For compatibility, store Qn out of Zn here. */ VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2), VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2), @@ -115,7 +115,7 @@ static const VMStateDescription vmstate_iwmmxt =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D iwmmxt_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), VMSTATE_END_OF_LIST() @@ -140,7 +140,7 @@ static const VMStateDescription vmstate_zreg_hi_reg =3D= { .name =3D "cpu/sve/zreg_hi", .version_id =3D 1, .minimum_version_id =3D 1, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), VMSTATE_END_OF_LIST() } @@ -150,7 +150,7 @@ static const VMStateDescription vmstate_preg_reg =3D { .name =3D "cpu/sve/preg", .version_id =3D 1, .minimum_version_id =3D 1, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), VMSTATE_END_OF_LIST() } @@ -161,7 +161,7 @@ static const VMStateDescription vmstate_sve =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D sve_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, vmstate_zreg_hi_reg, ARMVectorReg), VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, @@ -174,7 +174,7 @@ static const VMStateDescription vmstate_vreg =3D { .name =3D "vreg", .version_id =3D 1, .minimum_version_id =3D 1, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT64_ARRAY(d, ARMVectorReg, ARM_MAX_VQ * 2), VMSTATE_END_OF_LIST() } @@ -196,7 +196,7 @@ static const VMStateDescription vmstate_za =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D za_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_STRUCT_ARRAY(env.zarray, ARMCPU, ARM_MAX_VQ * 16, 0, vmstate_vreg, ARMVectorReg), VMSTATE_END_OF_LIST() @@ -217,7 +217,7 @@ static const VMStateDescription vmstate_serror =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D serror_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT8(env.serror.pending, ARMCPU), VMSTATE_UINT8(env.serror.has_esr, ARMCPU), VMSTATE_UINT64(env.serror.esr, ARMCPU), @@ -235,7 +235,7 @@ static const VMStateDescription vmstate_irq_line_state = =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D irq_line_state_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32(env.irq_line_state, ARMCPU), VMSTATE_END_OF_LIST() } @@ -254,7 +254,7 @@ static const VMStateDescription vmstate_m_faultmask_pri= mask =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D m_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() @@ -289,7 +289,7 @@ static const VMStateDescription vmstate_m_csselr =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D m_csselr_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS), VMSTATE_VALIDATE("CSSELR is valid", csselr_vmstate_validate), VMSTATE_END_OF_LIST() @@ -301,7 +301,7 @@ static const VMStateDescription vmstate_m_scr =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D m_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() } @@ -312,7 +312,7 @@ static const VMStateDescription vmstate_m_other_sp =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D m_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32(env.v7m.other_sp, ARMCPU), VMSTATE_END_OF_LIST() } @@ -331,7 +331,7 @@ static const VMStateDescription vmstate_m_v8m =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D m_v8m_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS), VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS), VMSTATE_END_OF_LIST() @@ -343,7 +343,7 @@ static const VMStateDescription vmstate_m_fp =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D vfp_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS), VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS), VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS), @@ -365,7 +365,7 @@ static const VMStateDescription vmstate_m_mve =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D mve_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32(env.v7m.vpr, ARMCPU), VMSTATE_UINT32(env.v7m.ltpsize, ARMCPU), VMSTATE_END_OF_LIST() @@ -377,7 +377,7 @@ static const VMStateDescription vmstate_m =3D { .version_id =3D 4, .minimum_version_id =3D 4, .needed =3D m_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), @@ -391,7 +391,7 @@ static const VMStateDescription vmstate_m =3D { VMSTATE_INT32(env.v7m.exception, ARMCPU), VMSTATE_END_OF_LIST() }, - .subsections =3D (const VMStateDescription*[]) { + .subsections =3D (const VMStateDescription * const []) { &vmstate_m_faultmask_primask, &vmstate_m_csselr, &vmstate_m_scr, @@ -416,7 +416,7 @@ static const VMStateDescription vmstate_thumb2ee =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D thumb2ee_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32(env.teecr, ARMCPU), VMSTATE_UINT32(env.teehbr, ARMCPU), VMSTATE_END_OF_LIST() @@ -445,7 +445,7 @@ static const VMStateDescription vmstate_pmsav7 =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D pmsav7_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, vmstate_info_uint32, uint32_t), VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, @@ -474,7 +474,7 @@ static const VMStateDescription vmstate_pmsav7_rnr =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D pmsav7_rnr_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() } @@ -504,7 +504,7 @@ static const VMStateDescription vmstate_pmsav8r =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D pmsav8r_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_VARRAY_UINT32(env.pmsav8.hprbar, ARMCPU, pmsav8r_hdregion, 0, vmstate_info_uint32, uint32_t= ), VMSTATE_VARRAY_UINT32(env.pmsav8.hprlar, ARMCPU, @@ -518,7 +518,7 @@ static const VMStateDescription vmstate_pmsav8 =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D pmsav8_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dr= egion, 0, vmstate_info_uint32, uint32_t), VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dr= egion, @@ -527,7 +527,7 @@ static const VMStateDescription vmstate_pmsav8 =3D { VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() }, - .subsections =3D (const VMStateDescription * []) { + .subsections =3D (const VMStateDescription * const []) { &vmstate_pmsav8r, NULL } @@ -560,7 +560,7 @@ static const VMStateDescription vmstate_m_security =3D { .version_id =3D 1, .minimum_version_id =3D 1, .needed =3D m_security_needed, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32(env.v7m.secure, ARMCPU), VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU), VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU), @@ -888,7 +888,7 @@ const VMStateDescription vmstate_arm_cpu =3D { .post_save =3D cpu_post_save, .pre_load =3D cpu_pre_load, .post_load =3D cpu_post_load, - .fields =3D (VMStateField[]) { + .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), VMSTATE_UINT64(env.pc, ARMCPU), @@ -937,7 +937,7 @@ const VMStateDescription vmstate_arm_cpu =3D { }, VMSTATE_END_OF_LIST() }, - .subsections =3D (const VMStateDescription*[]) { + .subsections =3D (const VMStateDescription * const []) { &vmstate_vfp, &vmstate_iwmmxt, &vmstate_m, --=20 2.34.1