From nobody Wed Nov 27 00:43:00 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=ilande.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703078292698577.040256804432; Wed, 20 Dec 2023 05:18:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFwS2-0007ql-C5; Wed, 20 Dec 2023 08:17:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFwRi-0007oH-Kr for qemu-devel@nongnu.org; Wed, 20 Dec 2023 08:17:10 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFwRf-0002MN-Vo for qemu-devel@nongnu.org; Wed, 20 Dec 2023 08:17:10 -0500 Received: from host86-147-134-9.range86-147.btcentralplus.com ([86.147.134.9] helo=localhost.localdomain) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rFwRH-0001qt-DN; Wed, 20 Dec 2023 13:16:43 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:To:From:Sender:Reply-To:Cc: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=HTGeNDp6XMMBKf/2pbtpwhQy6zMd8BzI4nhaucjvvGA=; b=FRhC/v+MjoToCWLTKXe9IPIIGj lKO5UfG1YXw5jcEdzB6e+dithsnHyrgE5keV0I6HAJJ913DYAQZJG/SM0lbfrNyObEr/CwmMn66fr 1LHU2lrBooSakDD+UokoGkXOtja6ZsYwcHqLj/rtTXzrM0gLk43PiLHZmeQgwsdglzY1J4CuKuvdh lqTrw4+/5ypxJdFwJkNTKkpbJzOoB7FH77r/CN9SKymKz+zukAmMVsbDfYwjid5G2FI/LnEZ5TsZu uN+jjjJsiBDlofJZu39hIQ/nlmE+jSTobZd5hERi2hdisf2M9MsaOlocCmPmhSLb/oD9BpRPBzIw1 bLiw7JADfCaCcfPJIy2SCWFmps108a30AQzBdUs1HKGhPGiG5s3H6jEgN2IOoxd8EPyb06T7r6meY uFXymvTyN5uXfyHFqSAfwJ+RnKN8k10EmsYtKXB3wbvnKEFVc2mjG+oJP0WqL8qWKES9tiMAWy76f mrHObzRPY/Fq34EqRXhTep4S5wAMER+/SBITCGd8aqYcrKHUrkqakLVWI6NNd+KWvu11wJbKeiHBh sDhs3iq+rAL0yG98fI0Gw7XGlFFmFMjYgFCAiOiTighsDJZDYRtUeIBVm5SBw3kwqZ9vNuNL1cgB7 VANOerFD9BIKT3zzs2mqfBO8Naqajx86Qq2t6lonk=; From: Mark Cave-Ayland To: huth@tuxfamily.org, qemu-devel@nongnu.org Date: Wed, 20 Dec 2023 13:16:35 +0000 Message-Id: <20231220131641.592826-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231220131641.592826-1-mark.cave-ayland@ilande.co.uk> References: <20231220131641.592826-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.147.134.9 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 05/11] next-cube.c: update and improve dma_ops X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1703078294380100003 Content-Type: text/plain; charset="utf-8" Rename dma_ops to next_dma_ops and the read/write functions to next_dma_rea= d() and next_dma_write() respectively, mark next_dma_ops as DEVICE_BIG_ENDIAN a= nd also improve the consistency of the val variable in next_dma_read() and next_dma_write(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Thomas Huth --- hw/m68k/next-cube.c | 100 ++++++++++++++++++++++++++++---------------- 1 file changed, 63 insertions(+), 37 deletions(-) diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index 8ed9bac26d..be4091ffd7 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -491,59 +491,63 @@ static const MemoryRegionOps next_scr_ops =3D { #define NEXTDMA_NEXT_INIT 0x4200 #define NEXTDMA_SIZE 0x4204 =20 -static void dma_writel(void *opaque, hwaddr addr, uint64_t value, - unsigned int size) +static void next_dma_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) { NeXTState *next_state =3D NEXT_MACHINE(opaque); =20 switch (addr) { case NEXTDMA_ENRX(NEXTDMA_CSR): - if (value & DMA_DEV2M) { + if (val & DMA_DEV2M) { next_state->dma[NEXTDMA_ENRX].csr |=3D DMA_DEV2M; } =20 - if (value & DMA_SETENABLE) { + if (val & DMA_SETENABLE) { /* DPRINTF("SCSI DMA ENABLE\n"); */ next_state->dma[NEXTDMA_ENRX].csr |=3D DMA_ENABLE; } - if (value & DMA_SETSUPDATE) { + if (val & DMA_SETSUPDATE) { next_state->dma[NEXTDMA_ENRX].csr |=3D DMA_SUPDATE; } - if (value & DMA_CLRCOMPLETE) { + if (val & DMA_CLRCOMPLETE) { next_state->dma[NEXTDMA_ENRX].csr &=3D ~DMA_COMPLETE; } =20 - if (value & DMA_RESET) { + if (val & DMA_RESET) { next_state->dma[NEXTDMA_ENRX].csr &=3D ~(DMA_COMPLETE | DMA_SU= PDATE | DMA_ENABLE | DMA_DEV2M); } /* DPRINTF("RXCSR \tWrite: %x\n",value); */ break; + case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): - next_state->dma[NEXTDMA_ENRX].next_initbuf =3D value; + next_state->dma[NEXTDMA_ENRX].next_initbuf =3D val; break; + case NEXTDMA_ENRX(NEXTDMA_NEXT): - next_state->dma[NEXTDMA_ENRX].next =3D value; + next_state->dma[NEXTDMA_ENRX].next =3D val; break; + case NEXTDMA_ENRX(NEXTDMA_LIMIT): - next_state->dma[NEXTDMA_ENRX].limit =3D value; + next_state->dma[NEXTDMA_ENRX].limit =3D val; break; + case NEXTDMA_SCSI(NEXTDMA_CSR): - if (value & DMA_DEV2M) { + if (val & DMA_DEV2M) { next_state->dma[NEXTDMA_SCSI].csr |=3D DMA_DEV2M; } - if (value & DMA_SETENABLE) { + if (val & DMA_SETENABLE) { /* DPRINTF("SCSI DMA ENABLE\n"); */ next_state->dma[NEXTDMA_SCSI].csr |=3D DMA_ENABLE; } - if (value & DMA_SETSUPDATE) { + if (val & DMA_SETSUPDATE) { next_state->dma[NEXTDMA_SCSI].csr |=3D DMA_SUPDATE; } - if (value & DMA_CLRCOMPLETE) { + if (val & DMA_CLRCOMPLETE) { next_state->dma[NEXTDMA_SCSI].csr &=3D ~DMA_COMPLETE; } =20 - if (value & DMA_RESET) { + if (val & DMA_RESET) { next_state->dma[NEXTDMA_SCSI].csr &=3D ~(DMA_COMPLETE | DMA_SU= PDATE | DMA_ENABLE | DMA_DEV2M); /* DPRINTF("SCSI DMA RESET\n"); */ @@ -552,23 +556,23 @@ static void dma_writel(void *opaque, hwaddr addr, uin= t64_t value, break; =20 case NEXTDMA_SCSI(NEXTDMA_NEXT): - next_state->dma[NEXTDMA_SCSI].next =3D value; + next_state->dma[NEXTDMA_SCSI].next =3D val; break; =20 case NEXTDMA_SCSI(NEXTDMA_LIMIT): - next_state->dma[NEXTDMA_SCSI].limit =3D value; + next_state->dma[NEXTDMA_SCSI].limit =3D val; break; =20 case NEXTDMA_SCSI(NEXTDMA_START): - next_state->dma[NEXTDMA_SCSI].start =3D value; + next_state->dma[NEXTDMA_SCSI].start =3D val; break; =20 case NEXTDMA_SCSI(NEXTDMA_STOP): - next_state->dma[NEXTDMA_SCSI].stop =3D value; + next_state->dma[NEXTDMA_SCSI].stop =3D val; break; =20 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): - next_state->dma[NEXTDMA_SCSI].next_initbuf =3D value; + next_state->dma[NEXTDMA_SCSI].next_initbuf =3D val; break; =20 default: @@ -576,52 +580,73 @@ static void dma_writel(void *opaque, hwaddr addr, uin= t64_t value, } } =20 -static uint64_t dma_readl(void *opaque, hwaddr addr, unsigned int size) +static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size) { NeXTState *next_state =3D NEXT_MACHINE(opaque); + uint64_t val; =20 switch (addr) { case NEXTDMA_SCSI(NEXTDMA_CSR): DPRINTF("SCSI DMA CSR READ\n"); - return next_state->dma[NEXTDMA_SCSI].csr; + val =3D next_state->dma[NEXTDMA_SCSI].csr; + break; + case NEXTDMA_ENRX(NEXTDMA_CSR): - return next_state->dma[NEXTDMA_ENRX].csr; + val =3D next_state->dma[NEXTDMA_ENRX].csr; + break; + case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): - return next_state->dma[NEXTDMA_ENRX].next_initbuf; + val =3D next_state->dma[NEXTDMA_ENRX].next_initbuf; + break; + case NEXTDMA_ENRX(NEXTDMA_NEXT): - return next_state->dma[NEXTDMA_ENRX].next; + val =3D next_state->dma[NEXTDMA_ENRX].next; + break; + case NEXTDMA_ENRX(NEXTDMA_LIMIT): - return next_state->dma[NEXTDMA_ENRX].limit; + val =3D next_state->dma[NEXTDMA_ENRX].limit; + break; =20 case NEXTDMA_SCSI(NEXTDMA_NEXT): - return next_state->dma[NEXTDMA_SCSI].next; + val =3D next_state->dma[NEXTDMA_SCSI].next; + break; + case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): - return next_state->dma[NEXTDMA_SCSI].next_initbuf; + val =3D next_state->dma[NEXTDMA_SCSI].next_initbuf; + break; + case NEXTDMA_SCSI(NEXTDMA_LIMIT): - return next_state->dma[NEXTDMA_SCSI].limit; + val =3D next_state->dma[NEXTDMA_SCSI].limit; + break; + case NEXTDMA_SCSI(NEXTDMA_START): - return next_state->dma[NEXTDMA_SCSI].start; + val =3D next_state->dma[NEXTDMA_SCSI].start; + break; + case NEXTDMA_SCSI(NEXTDMA_STOP): - return next_state->dma[NEXTDMA_SCSI].stop; + val =3D next_state->dma[NEXTDMA_SCSI].stop; + break; =20 default: DPRINTF("DMA read @ %x\n", (unsigned int)addr); - return 0; + val =3D 0; } =20 /* * once the csr's are done, subtract 0x3FEC from the addr, and that wi= ll * normalize the upper registers */ + + return val; } =20 -static const MemoryRegionOps dma_ops =3D { - .read =3D dma_readl, - .write =3D dma_writel, +static const MemoryRegionOps next_dma_ops =3D { + .read =3D next_dma_read, + .write =3D next_dma_write, .impl.min_access_size =3D 4, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_BIG_ENDIAN, }; =20 static void next_irq(void *opaque, int number, int level) @@ -1017,7 +1042,8 @@ static void next_cube_init(MachineState *machine) next_scsi_init(pcdev, cpu); =20 /* DMA */ - memory_region_init_io(dmamem, NULL, &dma_ops, machine, "next.dma", 0x5= 000); + memory_region_init_io(dmamem, NULL, &next_dma_ops, machine, "next.dma", + 0x5000); memory_region_add_subregion(sysmem, 0x02000000, dmamem); } =20 --=20 2.39.2