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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2001:4860:4864:20::2c; envelope-from=ah@immunant.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 20 Dec 2023 06:47:14 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @immunant-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1703072888810100003 From: Arve Hj=C3=B8nnev=C3=A5g Implement aliased registers so group 1 interrupts can be used in secure mode. GICC_AEOIR is only implemented as a direct alias to GICC_EOIR for now as gic_complete_irq does not currently check if the cpu is in secure mode. Upstreamed from https://r.android.com/705890 and https://r.android.com/859189. Signed-off-by: Arve Hj=C3=B8nnev=C3=A5g Signed-off-by: Matthew Maurer Signed-off-by: Andrei Homescu --- hw/intc/arm_gic.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 074cf50af2..d0e267a4b2 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -854,7 +854,8 @@ static void gic_deactivate_irq(GICState *s, int cpu, in= t irq, MemTxAttrs attrs) gic_clear_active(s, irq, cpu); } =20 -static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs att= rs) +static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs att= rs, + bool ns_irq) { int cm =3D 1 << cpu; int group; @@ -922,7 +923,7 @@ static void gic_complete_irq(GICState *s, int cpu, int = irq, MemTxAttrs attrs) =20 group =3D gic_has_groups(s) && gic_test_group(s, irq, cpu); =20 - if (gic_cpu_ns_access(s, cpu, attrs) && !group) { + if (ns_irq && !group) { DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); return; } @@ -1647,6 +1648,22 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu= , int offset, *data =3D s->abpr[cpu]; } break; + case 0x20: /* Aliased Interrupt Acknowledge */ + if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { + *data =3D 0; + } else { + attrs.secure =3D false; + *data =3D gic_acknowledge_irq(s, cpu, attrs); + } + break; + case 0x28: /* Aliased Highest Priority Pending Interrupt */ + if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { + *data =3D 0; + } else { + attrs.secure =3D false; + *data =3D gic_get_current_pending_irq(s, cpu, attrs); + } + break; case 0xd0: case 0xd4: case 0xd8: case 0xdc: { int regno =3D (offset - 0xd0) / 4; @@ -1724,7 +1741,15 @@ static MemTxResult gic_cpu_write(GICState *s, int cp= u, int offset, } break; case 0x10: /* End Of Interrupt */ - gic_complete_irq(s, cpu, value & 0x3ff, attrs); + gic_complete_irq(s, cpu, value & 0x3ff, attrs, + gic_cpu_ns_access(s, cpu, attrs)); + return MEMTX_OK; + case 0x24: /* Aliased End Of Interrupt */ + if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { + /* unimplemented, or NS access: RAZ/WI */ + } else { + gic_complete_irq(s, cpu, value & 0x3ff, attrs, true); + } return MEMTX_OK; case 0x1c: /* Aliased Binary Point */ if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { --=20 2.42.1