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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013190; x=1703617990; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=9bxYcAuKeHOY0Scr+m8bY+3d+8njdh2moV1wFNg9V4M=; b=G9+cmKJnTPTvWWU1BGKxNO/iDlPans1ZKI5YTEd827CdvOQcxcWB8Sqabg8BDkxLiH McPfiAtgW3Xbtsxx33XWz+lelsuRms4OYbvuAdphyBc2eLEPg4Y0FCfZKe+Gz7D5gSOV Ol1e+eTn+mhEvJQIN15EhhUI4ntKxkb/P9eGdwczx/uoU/3DMg1B1t8GQ4bGFyYJmJMC NmU69iZemqHoe59OVCEd/Wv3V5fJdi6cZNpWwgOksvo3D8wf7GvsrV4BLpvNdOOv+k79 CCQJgdzt4VWypjdw461TTKCbCYkp/q/Xt3aARJVTwYojiHLc+WOHHtVtOJ34dSwhFzw2 NxeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013190; x=1703617990; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9bxYcAuKeHOY0Scr+m8bY+3d+8njdh2moV1wFNg9V4M=; b=gEkYHgYd1GBywAWu5gOsEzknlh7IoEBUB8l8gTrJK85UWj91RsTcolsZqlE767TFus T4khHS/KW0v0hjKQwwc3Nn9YPN9gfY0vHU4wYfjs8bnrdPWPBovmuP1z+F1dEcjOniQV V9REjBRH374Fr4FONV87xt4FavbvzrVOUfeB7/sSguHXnZEBo8EgJBF0YW6LMElrfaCo hFugrVWppg73BZity951CuS7rXAnPro2O8i0jX6V2sIj3xEjk/L9CUobLW1Bi9gw0xto XpLnuHms0eirrEVwUsjo7f7Dofs+5rmaPqu+d0IkTJJ+ZgcDwcwCG2oSZ5JC+w2m0X1o MuZw== X-Gm-Message-State: AOJu0YzqkD/jrnaLbrvn5U/TaNjYG/jUDjfqDm9wGd2cf0Z29g89sZ47 wiyAzwGRLaL3MVFlVheD5F8TwwKgu004UbEWrrY= X-Google-Smtp-Source: AGHT+IFTC7juGA2NZsy89Uc2lAI7RtTBODUQa+XrR4JZF28gGKayhMbmarOiodDEmR7NglV9nVR4OQ== X-Received: by 2002:a5d:5411:0:b0:336:686c:c60d with SMTP id g17-20020a5d5411000000b00336686cc60dmr2177066wrv.115.1703013189980; Tue, 19 Dec 2023 11:13:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/43] accel/kvm: Make kvm_has_guest_debug static Date: Tue, 19 Dec 2023 19:12:25 +0000 Message-Id: <20231219191307.2895919-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013484642100001 From: Richard Henderson This variable is not used or declared outside kvm-all.c. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- accel/kvm/kvm-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index e39a810a4e9..f138e7fefe7 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -98,7 +98,7 @@ bool kvm_allowed; bool kvm_readonly_mem_allowed; bool kvm_vm_attributes_allowed; bool kvm_msi_use_devid; -bool kvm_has_guest_debug; +static bool kvm_has_guest_debug; static int kvm_sstep_flags; static bool kvm_immediate_exit; static hwaddr kvm_max_slot_size =3D ~0; --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013396; cv=none; d=zohomail.com; s=zohoarc; b=Vdj6dlhnchIkxSm9bggTbmc0vDaGZyVb53nwyeka/6HcCcB7vBv1x45GvqwDISIfoeCh0ikCRL4fwv6D03b3Md5Na/E9ZtDW4sMeAwdePbpd2LFmJKLN+R2SzLSQGjJQpSWw2hhzlz0NptPJtWE3jnfsMbTrMsVbRkwh3QBasCM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013396; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=F3jDm6hsuPn369Wfm7LfYD3ZrqbNS5l6yUoiu2wnKtg=; b=LnxviXxHcRlt/qJI1r7xKBMiczzSYfZlx8AAayG6QykrfWr86RVnhnVdLiGAPJUtTZvCAmbgQOhd2439NfWACyDaAc026R9Jnwv2lL7U/7+sX5UBGHb0aJGjg7jn8/CJFW+mXz1dfRgfMZqVG0EDJykMhfrQ2xLmOOOc8KpDsQU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013396888459.0891397765597; Tue, 19 Dec 2023 11:16:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWn-0001mY-Bu; Tue, 19 Dec 2023 14:13:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWl-0001k5-4L for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:15 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWj-0001lK-23 for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:14 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-40c3fe6c08fso56500835e9.1 for ; Tue, 19 Dec 2023 11:13:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013190; x=1703617990; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=F3jDm6hsuPn369Wfm7LfYD3ZrqbNS5l6yUoiu2wnKtg=; b=ORXSRtICHeMcAZA+QFJd47mFqT0mF/ElJBSUq1tt7IvcRVphjewYCmWgudwVFL5Nen Q4/GSZdBsvEX7cDyN2qaI6P8tn2WWsXj7EJwF3+UDCIRn27KVblZl2tBD8PslA0dJGXy 8NE9KN4qqWZqY1hctAbBtIpqx4p7xAHoqwM1TufplDrF2CP7JwWpPeriTQ+fpdOf+D2R gttyeLaKK2s0DWjktCBiUbuQPBc5X2cYHUkE2fjlYpa3syGEQxjpP8npC9/USlDRK6Se CA65XKljL8xFNsiNuM3NVjgGA3AS1JFxkveVyvF7/txoQnaSo7dBMFk3Gv8GJ/61AkAW RmFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013190; x=1703617990; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F3jDm6hsuPn369Wfm7LfYD3ZrqbNS5l6yUoiu2wnKtg=; b=s7bWSB1pVVbc2XrDPNO2yYkE+hBlcvMFjdqkHgwy18itaiVuV4SnA/jX8uUW9v+Qo3 vFC5I70NSqNb6kc9TYj8ZQvULBFN/v7pXF9wSk/SIgx1Av2K097jBKYb7W421GdMUycd lFkke42sttNhptqJLIs8gCWedF1IN1EcVIbIR8rXq7TrmGKem/PTPm/1zbjDiVaFbGVk 2q43BTAXJqH5vxeCLnJKJ0+4IKbK5rT2ILKtBBmNh99yQLk4/W8jP4THeiqNYNK/Da18 6n0nm3zk7WinT2ketda6nLFfsbouG6O3W0mdMhKuYDShLbMJQ5QGQX+nyAkOLJqjsBFi BlrQ== X-Gm-Message-State: AOJu0YxiU8HPxAr2OaDXE9xcy0Hy2ELMY73Y86PeuDjPUzk5G4EJ+2b9 xRYcVJxwvdoKQknzpGfj+U2cyjRyaXIsFgdayqg= X-Google-Smtp-Source: AGHT+IGDqMgdXc3M+uIw8511sqYOy8r0wMPutaNm+Iy8KzcULfpBbfuk0X+vV/YOSIXavIIGeNa31w== X-Received: by 2002:a05:600c:2802:b0:40b:5e59:99b6 with SMTP id m2-20020a05600c280200b0040b5e5999b6mr6808312wmb.214.1703013190477; Tue, 19 Dec 2023 11:13:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/43] target/arm: kvm64: remove a redundant KVM_CAP_SET_GUEST_DEBUG probe Date: Tue, 19 Dec 2023 19:12:26 +0000 Message-Id: <20231219191307.2895919-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013397664100001 From: Chao Du The KVM_CAP_SET_GUEST_DEBUG is probed during kvm_init(). gdbserver will fail to start if the CAP is not supported. So no need to make another probe here, like other targets. Signed-off-by: Chao Du Reviewed-by: Richard Henderson Message-Id: <20231025070726.22689-1-duchao@eswincomputing.com> Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 3c175c93a7a..b8bb25a1eaa 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -32,13 +32,9 @@ #include "hw/acpi/acpi.h" #include "hw/acpi/ghes.h" =20 -static bool have_guest_debug; =20 void kvm_arm_init_debug(KVMState *s) { - have_guest_debug =3D kvm_check_extension(s, - KVM_CAP_SET_GUEST_DEBUG); - max_hw_wps =3D kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); hw_watchpoints =3D g_array_sized_new(true, true, sizeof(HWWatchpoint), max_hw_wps); @@ -1141,33 +1137,23 @@ static const uint32_t brk_insn =3D 0xd4200000; =20 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) { - if (have_guest_debug) { - if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4,= 0) || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { - return -EINVAL; - } - return 0; - } else { - error_report("guest debug not supported on this kernel"); + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) = || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { return -EINVAL; } + return 0; } =20 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) { static uint32_t brk; =20 - if (have_guest_debug) { - if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || - brk !=3D brk_insn || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4,= 1)) { - return -EINVAL; - } - return 0; - } else { - error_report("guest debug not supported on this kernel"); + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || + brk !=3D brk_insn || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1))= { return -EINVAL; } + return 0; } =20 /* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013413; cv=none; d=zohomail.com; s=zohoarc; b=jVJLOsBqu7CN2V8Kj6nxkjEKS4CMeZLSYVOk8C3m+NCGIdYZn8NLo7tWjuvOcdOwdVnfKoASmmNi0gA6Q0iJCnWiR7WJhI3Bgw9aSQ/f46tL9otQJiwAYhuwhvBRj3DPok6MBJ1d+VIYtg96qHTPUl7UHmHooFFhnJuT9UXPB1s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013413; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Jvn/OVUOD0Xhju1C/N/gil1Qe6DSfBId9X5CN10lS/s=; b=YpgCvKq4LzhlNeSkKqumsgdM0DzoMl3yxamx4DSYKeABn9Hfz5ZPXMMe/tEjnEAYzQoTcUUIMB52rZ6UaxQDuxF6LCqfLiOdY2AYl1LbEWLiiCO/nR999FAzrZXgluS1nQpEAoc3b2n+Aw9cszsza9/D51JOItZ387DXetDYqbU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013413373904.7791668407368; Tue, 19 Dec 2023 11:16:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWm-0001kv-IM; Tue, 19 Dec 2023 14:13:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWl-0001k3-0f for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:15 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWi-0001lO-DP for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:14 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-40c38de1ee4so49389915e9.0 for ; Tue, 19 Dec 2023 11:13:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013413833100001 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 8 -------- target/arm/kvm.c | 8 +++++++- target/arm/kvm64.c | 12 ------------ 3 files changed, 7 insertions(+), 21 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 051a0da41c4..fe6d824a52c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -18,14 +18,6 @@ #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) =20 -/** - * kvm_arm_init_debug() - initialize guest debug capabilities - * @s: KVMState - * - * Should be called only once before using guest debug capabilities. - */ -void kvm_arm_init_debug(KVMState *s); - /** * kvm_arm_vcpu_init: * @cs: CPUState diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 7903e2ddde1..b4836da6b25 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -308,7 +308,13 @@ int kvm_arch_init(MachineState *ms, KVMState *s) } } =20 - kvm_arm_init_debug(s); + max_hw_wps =3D kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); + hw_watchpoints =3D g_array_sized_new(true, true, + sizeof(HWWatchpoint), max_hw_wps); + + max_hw_bps =3D kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS); + hw_breakpoints =3D g_array_sized_new(true, true, + sizeof(HWBreakpoint), max_hw_bps); =20 return ret; } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index b8bb25a1eaa..40f459b7862 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -33,18 +33,6 @@ #include "hw/acpi/ghes.h" =20 =20 -void kvm_arm_init_debug(KVMState *s) -{ - max_hw_wps =3D kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_WPS); - hw_watchpoints =3D g_array_sized_new(true, true, - sizeof(HWWatchpoint), max_hw_wps); - - max_hw_bps =3D kvm_check_extension(s, KVM_CAP_GUEST_DEBUG_HW_BPS); - hw_breakpoints =3D g_array_sized_new(true, true, - sizeof(HWBreakpoint), max_hw_bps); - return; -} - int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) { switch (type) { --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013462; cv=none; d=zohomail.com; s=zohoarc; b=aWfG3nw6fNTJjQEYNxsk00fzOwuJWUjxAHyNkIZe1Qkvm7YUZNQdIalOgsOF913yPKvUSz/ossQHULQvTA9xpj5tvxALrZNNYqNMewgJLAhp0lHBWJFBJxr1R2fr9wc8QypTFPMt0apso0OU/rsVj+/7Pv8KgzQocR9g8k/KcMA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013462; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013463898100001 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 10 -------- target/arm/kvm.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 49 ------------------------------------- 3 files changed, 57 insertions(+), 59 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index fe6d824a52c..bb284a47de3 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -472,14 +472,4 @@ bool kvm_arm_hw_debug_active(CPUState *cs); struct kvm_guest_debug_arch; void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); =20 -/** - * kvm_arm_verify_ext_dabt_pending: - * @cs: CPUState - * - * Verify the fault status code wrt the Ext DABT injection - * - * Returns: true if the fault status code is as expected, false otherwise - */ -bool kvm_arm_verify_ext_dabt_pending(CPUState *cs); - #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b4836da6b25..696bc63e863 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -793,6 +793,63 @@ int kvm_get_vcpu_events(ARMCPU *cpu) return 0; } =20 +#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) +#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) + +/* + * ESR_EL1 + * ISS encoding + * AARCH64: DFSC, bits [5:0] + * AARCH32: + * TTBCR.EAE =3D=3D 0 + * FS[4] - DFSR[10] + * FS[3:0] - DFSR[3:0] + * TTBCR.EAE =3D=3D 1 + * FS, bits [5:0] + */ +#define ESR_DFSC(aarch64, lpae, v) \ + ((aarch64 || (lpae)) ? ((v) & 0x3F) \ + : (((v) >> 6) | ((v) & 0x1F))) + +#define ESR_DFSC_EXTABT(aarch64, lpae) \ + ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) + +/** + * kvm_arm_verify_ext_dabt_pending: + * @cs: CPUState + * + * Verify the fault status code wrt the Ext DABT injection + * + * Returns: true if the fault status code is as expected, false otherwise + */ +static bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) +{ + uint64_t dfsr_val; + + if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + int aarch64_mode =3D arm_feature(env, ARM_FEATURE_AARCH64); + int lpae =3D 0; + + if (!aarch64_mode) { + uint64_t ttbcr; + + if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { + lpae =3D arm_feature(env, ARM_FEATURE_LPAE) + && (ttbcr & TTBCR_EAE); + } + } + /* + * The verification here is based on the DFSC bits + * of the ESR_EL1 reg only + */ + return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) =3D=3D + ESR_DFSC_EXTABT(aarch64_mode, lpae)); + } + return false; +} + void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) { ARMCPU *cpu =3D ARM_CPU(cs); diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 40f459b7862..7d937e25390 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1213,52 +1213,3 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_d= ebug_exit_arch *debug_exit) =20 return false; } - -#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0) -#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2) - -/* - * ESR_EL1 - * ISS encoding - * AARCH64: DFSC, bits [5:0] - * AARCH32: - * TTBCR.EAE =3D=3D 0 - * FS[4] - DFSR[10] - * FS[3:0] - DFSR[3:0] - * TTBCR.EAE =3D=3D 1 - * FS, bits [5:0] - */ -#define ESR_DFSC(aarch64, lpae, v) \ - ((aarch64 || (lpae)) ? ((v) & 0x3F) \ - : (((v) >> 6) | ((v) & 0x1F))) - -#define ESR_DFSC_EXTABT(aarch64, lpae) \ - ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8) - -bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) -{ - uint64_t dfsr_val; - - if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - int aarch64_mode =3D arm_feature(env, ARM_FEATURE_AARCH64); - int lpae =3D 0; - - if (!aarch64_mode) { - uint64_t ttbcr; - - if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) { - lpae =3D arm_feature(env, ARM_FEATURE_LPAE) - && (ttbcr & TTBCR_EAE); - } - } - /* - * The verification here is based on the DFSC bits - * of the ESR_EL1 reg only - */ - return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) =3D=3D - ESR_DFSC_EXTABT(aarch64_mode, lpae)); - } - return false; -} --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013272; cv=none; d=zohomail.com; s=zohoarc; b=iNIzAysw40H4bah6R0r4snQQ/8xFkobBaneDRZHSlEekdfyssLVAkwHW8otVk2/lnzsNXAoiePFk13x27ZqE4niXukdZR7Q5zcDgIHXvhUrp2nyjBSUp7xrp402F6i49Zocrp6WWpGzYE0GYTVvzuIBtCern2KY3p1/yaBxVeHY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013272; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=F3MrT5q0KM6MELIuaCuVzJsIz/QtvXJBno3yclja630=; b=FfELAhJacOAkkvN/WADafaXww+2e7AR78L4urPC1hvUwDk/wmUmstar/DSrhE6sO92IF1328rOOW+5b9qcVOs74IEUO9fv2M8kltf1uUrDUbj8rolIr73FzNQYmZvRU7jchAkrXBDa3ItSXiYFg78E6jMq8LMx8Htks+VIU5QYs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013272510987.2846462023355; Tue, 19 Dec 2023 11:14:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWn-0001mS-C7; Tue, 19 Dec 2023 14:13:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWl-0001kR-Ea for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:15 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWj-0001lT-6V for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:15 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-33671384e50so1164280f8f.0 for ; Tue, 19 Dec 2023 11:13:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013273421100001 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 10 ---------- target/arm/kvm.c | 24 ++++++++++++++++++++++++ target/arm/kvm64.c | 17 ----------------- 3 files changed, 24 insertions(+), 27 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index bb284a47de3..207b7f21b0a 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -462,14 +462,4 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_deb= ug_exit_arch *debug_exit); */ bool kvm_arm_hw_debug_active(CPUState *cs); =20 -/** - * kvm_arm_copy_hw_debug_data: - * @ptr: kvm_guest_debug_arch structure - * - * Copy the architecture specific debug registers into the - * kvm_guest_debug ioctl structure. - */ -struct kvm_guest_debug_arch; -void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); - #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 696bc63e863..2898e680fc5 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1021,6 +1021,30 @@ int kvm_arch_process_async_events(CPUState *cs) return 0; } =20 +/** + * kvm_arm_copy_hw_debug_data: + * @ptr: kvm_guest_debug_arch structure + * + * Copy the architecture specific debug registers into the + * kvm_guest_debug ioctl structure. + */ +static void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr) +{ + int i; + memset(ptr, 0, sizeof(struct kvm_guest_debug_arch)); + + for (i =3D 0; i < max_hw_wps; i++) { + HWWatchpoint *wp =3D get_hw_wp(i); + ptr->dbg_wcr[i] =3D wp->wcr; + ptr->dbg_wvr[i] =3D wp->wvr; + } + for (i =3D 0; i < max_hw_bps; i++) { + HWBreakpoint *bp =3D get_hw_bp(i); + ptr->dbg_bcr[i] =3D bp->bcr; + ptr->dbg_bvr[i] =3D bp->bvr; + } +} + void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) { if (kvm_sw_breakpoints_active(cs)) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 7d937e25390..ac3120adaff 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -73,23 +73,6 @@ void kvm_arch_remove_all_hw_breakpoints(void) } } =20 -void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr) -{ - int i; - memset(ptr, 0, sizeof(struct kvm_guest_debug_arch)); - - for (i =3D 0; i < max_hw_wps; i++) { - HWWatchpoint *wp =3D get_hw_wp(i); - ptr->dbg_wcr[i] =3D wp->wcr; - ptr->dbg_wvr[i] =3D wp->wvr; - } - for (i =3D 0; i < max_hw_bps; i++) { - HWBreakpoint *bp =3D get_hw_bp(i); - ptr->dbg_bcr[i] =3D bp->bcr; - ptr->dbg_bvr[i] =3D bp->bvr; - } -} - bool kvm_arm_hw_debug_active(CPUState *cs) { return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013459976100012 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 8 -------- target/arm/kvm.c | 11 +++++++++++ target/arm/kvm64.c | 5 ----- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 207b7f21b0a..ac4856cb46e 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -454,12 +454,4 @@ static inline uint32_t kvm_arm_sve_get_vls(CPUState *c= s) */ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_= exit); =20 -/** - * kvm_arm_hw_debug_active: - * @cs: CPU State - * - * Return: TRUE if any hardware breakpoints in use. - */ -bool kvm_arm_hw_debug_active(CPUState *cs); - #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 2898e680fc5..4608bea7df4 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1021,6 +1021,17 @@ int kvm_arch_process_async_events(CPUState *cs) return 0; } =20 +/** + * kvm_arm_hw_debug_active: + * @cs: CPU State + * + * Return: TRUE if any hardware breakpoints in use. + */ +static bool kvm_arm_hw_debug_active(CPUState *cs) +{ + return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); +} + /** * kvm_arm_copy_hw_debug_data: * @ptr: kvm_guest_debug_arch structure diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index ac3120adaff..352643e0665 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -73,11 +73,6 @@ void kvm_arch_remove_all_hw_breakpoints(void) } } =20 -bool kvm_arm_hw_debug_active(CPUState *cs) -{ - return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); -} - static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *= attr, const char *name) { --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013510774100003 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 9 ------ target/arm/kvm.c | 77 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 70 ---------------------------------------- 3 files changed, 77 insertions(+), 79 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index ac4856cb46e..9fa9cb7f767 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -445,13 +445,4 @@ static inline uint32_t kvm_arm_sve_get_vls(CPUState *c= s) =20 #endif =20 -/** - * kvm_arm_handle_debug: - * @cs: CPUState - * @debug_exit: debug part of the KVM exit structure - * - * Returns: TRUE if the debug exception was handled. - */ -bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_= exit); - #endif diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 4608bea7df4..55e1b4f26e9 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -988,6 +988,83 @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint= 64_t esr_iss, return -1; } =20 +/** + * kvm_arm_handle_debug: + * @cs: CPUState + * @debug_exit: debug part of the KVM exit structure + * + * Returns: TRUE if the debug exception was handled. + * + * See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register + * + * To minimise translating between kernel and user-space the kernel + * ABI just provides user-space with the full exception syndrome + * register value to be decoded in QEMU. + */ +static bool kvm_arm_handle_debug(CPUState *cs, + struct kvm_debug_exit_arch *debug_exit) +{ + int hsr_ec =3D syn_get_ec(debug_exit->hsr); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + /* Ensure PC is synchronised */ + kvm_cpu_synchronize_state(cs); + + switch (hsr_ec) { + case EC_SOFTWARESTEP: + if (cs->singlestep_enabled) { + return true; + } else { + /* + * The kernel should have suppressed the guest's ability to + * single step at this point so something has gone wrong. + */ + error_report("%s: guest single-step while debugging unsupporte= d" + " (%"PRIx64", %"PRIx32")", + __func__, env->pc, debug_exit->hsr); + return false; + } + break; + case EC_AA64_BKPT: + if (kvm_find_sw_breakpoint(cs, env->pc)) { + return true; + } + break; + case EC_BREAKPOINT: + if (find_hw_breakpoint(cs, env->pc)) { + return true; + } + break; + case EC_WATCHPOINT: + { + CPUWatchpoint *wp =3D find_hw_watchpoint(cs, debug_exit->far); + if (wp) { + cs->watchpoint_hit =3D wp; + return true; + } + break; + } + default: + error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")", + __func__, debug_exit->hsr, env->pc); + } + + /* If we are not handling the debug exception it must belong to + * the guest. Let's re-use the existing TCG interrupt code to set + * everything up properly. + */ + cs->exception_index =3D EXCP_BKPT; + env->exception.syndrome =3D debug_exit->hsr; + env->exception.vaddress =3D debug_exit->far; + env->exception.target_el =3D 1; + qemu_mutex_lock_iothread(); + arm_cpu_do_interrupt(cs); + qemu_mutex_unlock_iothread(); + + return false; +} + int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { int ret =3D 0; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 352643e0665..6b6db9374c6 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1121,73 +1121,3 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, stru= ct kvm_sw_breakpoint *bp) } return 0; } - -/* See v8 ARM ARM D7.2.27 ESR_ELx, Exception Syndrome Register - * - * To minimise translating between kernel and user-space the kernel - * ABI just provides user-space with the full exception syndrome - * register value to be decoded in QEMU. - */ - -bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_= exit) -{ - int hsr_ec =3D syn_get_ec(debug_exit->hsr); - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* Ensure PC is synchronised */ - kvm_cpu_synchronize_state(cs); - - switch (hsr_ec) { - case EC_SOFTWARESTEP: - if (cs->singlestep_enabled) { - return true; - } else { - /* - * The kernel should have suppressed the guest's ability to - * single step at this point so something has gone wrong. - */ - error_report("%s: guest single-step while debugging unsupporte= d" - " (%"PRIx64", %"PRIx32")", - __func__, env->pc, debug_exit->hsr); - return false; - } - break; - case EC_AA64_BKPT: - if (kvm_find_sw_breakpoint(cs, env->pc)) { - return true; - } - break; - case EC_BREAKPOINT: - if (find_hw_breakpoint(cs, env->pc)) { - return true; - } - break; - case EC_WATCHPOINT: - { - CPUWatchpoint *wp =3D find_hw_watchpoint(cs, debug_exit->far); - if (wp) { - cs->watchpoint_hit =3D wp; - return true; - } - break; - } - default: - error_report("%s: unhandled debug exit (%"PRIx32", %"PRIx64")", - __func__, debug_exit->hsr, env->pc); - } - - /* If we are not handling the debug exception it must belong to - * the guest. Let's re-use the existing TCG interrupt code to set - * everything up properly. - */ - cs->exception_index =3D EXCP_BKPT; - env->exception.syndrome =3D debug_exit->hsr; - env->exception.vaddress =3D debug_exit->far; - env->exception.target_el =3D 1; - qemu_mutex_lock_iothread(); - arm_cpu_do_interrupt(cs); - qemu_mutex_unlock_iothread(); - - return false; -} --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013272; cv=none; d=zohomail.com; s=zohoarc; b=NI6Igm2VOuxKQsF/a/VJkIio/K4J6K18UK1qiI9ih6Etc+uBzTM2ffEmae9FyXYA/D/7hwGjYfUo7nMtnRn4qqfpTfrdCh+DRmii7hy/ZYrovl64Eh8Mfv7vcMDhfRsSSyuHDENtN+Ldp/42VTn/N8HKUCo+u3Nb8x8vGDyuaEQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013272; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=r1J7gC45bfq/FYNHKEltq/v3bAcoJrpQOGvO+cx208c=; b=Lz/xqSRh9hsehsZnBOglU8lXm4xNmc7ZIvHogkMVbTSu1RrWDOxWAyxMloFfJS909p3JP4fQLZVEux9uDcmVyAmkvjA42VEIIlPQQDumCPplY6n117oLcohkWvZj9ot1angvbZFief4dT4J07eNvb6LYr92d/Lmi8JV4qoHA2bU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013272533685.7598373790815; Tue, 19 Dec 2023 11:14:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWp-0001od-KO; Tue, 19 Dec 2023 14:13:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWm-0001ku-Ee for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:16 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWk-0001lu-Lx for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:16 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-33678156e27so178356f8f.1 for ; Tue, 19 Dec 2023 11:13:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013273430100002 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 16 ---------------- target/arm/kvm.c | 16 ++++++++++++++-- 2 files changed, 14 insertions(+), 18 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 9fa9cb7f767..e7c32f6ed07 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -335,22 +335,6 @@ int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); */ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); =20 -/** - * kvm_arm_get_virtual_time: - * @cs: CPUState - * - * Gets the VCPU's virtual counter and stores it in the KVM CPU state. - */ -void kvm_arm_get_virtual_time(CPUState *cs); - -/** - * kvm_arm_put_virtual_time: - * @cs: CPUState - * - * Sets the VCPU's virtual counter to the value stored in the KVM CPU stat= e. - */ -void kvm_arm_put_virtual_time(CPUState *cs); - void kvm_arm_vm_state_change(void *opaque, bool running, RunState state); =20 int kvm_arm_vgic_probe(void); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 55e1b4f26e9..84f300c602b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -704,7 +704,13 @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) return 0; } =20 -void kvm_arm_get_virtual_time(CPUState *cs) +/** + * kvm_arm_get_virtual_time: + * @cs: CPUState + * + * Gets the VCPU's virtual counter and stores it in the KVM CPU state. + */ +static void kvm_arm_get_virtual_time(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); int ret; @@ -722,7 +728,13 @@ void kvm_arm_get_virtual_time(CPUState *cs) cpu->kvm_vtime_dirty =3D true; } =20 -void kvm_arm_put_virtual_time(CPUState *cs) +/** + * kvm_arm_put_virtual_time: + * @cs: CPUState + * + * Sets the VCPU's virtual counter to the value stored in the KVM CPU stat= e. + */ +static void kvm_arm_put_virtual_time(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); int ret; --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013418; cv=none; d=zohomail.com; s=zohoarc; b=US0SRWRwjClbg36LsI4eAP9R7Khjbd+yeE3PMC/hTnIzpEkpfIhOTZ9mQ4JvbNwEB6jNRFNCwkBi5st5WvCSpn4bd7qYLlnDsQmhDKvaXBeEpPa2tr/5VJ7dTxgeAKpO1g0fVmUA8TzPQod+ocXnvbTxPy/m15aKjzMYqO0U91Y= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013194; x=1703617994; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=iHG9jQ+eiRWAlCnCIHDh9pSj/+rOdtp/Ld9fbC2kJeA=; b=A6J3UUxpGhHtzhA+/72Bf2ngmamo2FKt8HbDNTfLeT3UigJeHpUrotv180qQJyd7u1 yGFrsCAOrosURaz0s3Tt5dgKmLV3VsGSZ4CpXBRicz9O/6uYOmNi4QH7cecktWTn18O6 ZjWGLK/XCrJIBoNIH6WKSa5tF7cD3j1SyZJmxffpa9B11Hv7+tE5m6VeUZtBHVQkm1kV lbTg6YrZ/zavuuGbReFH4FiSjhlciY8v6i5kwsVvncdLpDeCBoO1KWOb9N4z3DuAmo3t XnJ33Lc+Ck+ivOejQeczfFL6yvQN1IIPbycjqArQEQ1k2I0yiZRSAQqIB8LG5E5oN5fC Z4GA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013194; x=1703617994; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iHG9jQ+eiRWAlCnCIHDh9pSj/+rOdtp/Ld9fbC2kJeA=; b=JojaU1xyFZWpk/VKRNpho/RQT1lDOParwxgOH5HH0krN+PwHfqjK5vBgdZZZxnywvQ 56dbude+NUa6hd+1w1u0ADNg00Sq/+R7qbPIbnmjxz6DvWx175eWM0LDdXwMRJopkaDD igmWwTDY21n/wxOUoTFnVPx1odYGkfWU+JsnLEBULEEfcuzBCXTVQD5nb8mTMXxN17Dl WmsV0aUEc9UWq9ofHKjCV0CqyS0ReVDw7Jth7GxvORCELRD4aiNQmAriOgBJOsx80GAo CcazTfFRMMLt4h7wVrpOImPQfb7rWq6+lQC3md3RZF8Wpsqo1tFa1ntd8+NKffpyZwZS iPLw== X-Gm-Message-State: AOJu0Ywo8IDZeiRkK/sv5dGt8DFqpgX1DX3WFvenNYdwMJvgIWYxpGtB R+2wAIZS9QVpUhmi/Ob3jHq2yjJLqcNPJXe511w= X-Google-Smtp-Source: AGHT+IHFvzaGbuXT4B4QNDWStwF8IjMNByy0zZ0tYTLzNDu0aoJouAd12HpL0xp7F+6VrlXmwq8yFg== X-Received: by 2002:a05:6000:1c6:b0:336:4297:b25d with SMTP id t6-20020a05600001c600b003364297b25dmr5597294wrx.136.1703013193787; Tue, 19 Dec 2023 11:13:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/43] target/arm/kvm: Inline kvm_arm_steal_time_supported Date: Tue, 19 Dec 2023 19:12:33 +0000 Message-Id: <20231219191307.2895919-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013419809100011 From: Richard Henderson This function is only used once, and is quite simple. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 13 ------------- target/arm/kvm64.c | 7 +------ 2 files changed, 1 insertion(+), 19 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index e7c32f6ed07..58c087207f5 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -274,14 +274,6 @@ void kvm_arm_add_vcpu_properties(Object *obj); */ void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp); =20 -/** - * kvm_arm_steal_time_supported: - * - * Returns: true if KVM can enable steal time reporting - * and false otherwise. - */ -bool kvm_arm_steal_time_supported(void); - /** * kvm_arm_aarch32_supported: * @@ -374,11 +366,6 @@ static inline bool kvm_arm_sve_supported(void) return false; } =20 -static inline bool kvm_arm_steal_time_supported(void) -{ - return false; -} - /* * These functions should never actually be called without KVM support. */ diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 6b6db9374c6..fca4864b739 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -399,7 +399,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) =20 void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) { - bool has_steal_time =3D kvm_arm_steal_time_supported(); + bool has_steal_time =3D kvm_check_extension(kvm_state, KVM_CAP_STEAL_T= IME); =20 if (cpu->kvm_steal_time =3D=3D ON_OFF_AUTO_AUTO) { if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64= )) { @@ -437,11 +437,6 @@ bool kvm_arm_sve_supported(void) return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); } =20 -bool kvm_arm_steal_time_supported(void) -{ - return kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); -} - QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN !=3D 1); =20 uint32_t kvm_arm_sve_get_vls(CPUState *cs) --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013325; cv=none; d=zohomail.com; s=zohoarc; b=B8pkfZSMwylpSjTGzUDKU1LZdrjRC1Fmj72lqIsVT0hq2rAmdmlyM/hp22GSlMe0DKB+dwtAp/2QhlqhCzhHHd4srd4PhAjNRR7NA8A1DuhDOb5CT10GNNxfAKYo7woaLLDj4NNRYKFGWPDJ70Jo9jfesRQEi6ZdcYyjscQaOrA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013325; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=tLIB590q5UqcoLo+DPfnNLtYefVrfy0YSOc9bChAWWk=; b=n2qhuhKCgkMBggMEtWrN6MyVeGnXXm6vQN5r18AY1gNUDjBXe9y78SmeC0FlV7SRM8Sn7kRSLDP3T4bPoS6r4BnppKK7/7exR+M5P23M9r2O7AVarMgPCigCnIgwMInPVqiwWCHX9RA/hn8yKvNbM6vM34RYfxtskT3GcUjN8Yc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170301332549824.74001684240079; Tue, 19 Dec 2023 11:15:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWt-0001te-AS; Tue, 19 Dec 2023 14:13:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWq-0001po-W0 for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:21 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWn-0001mF-Q5 for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:20 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3365d38dce2so3784423f8f.1 for ; Tue, 19 Dec 2023 11:13:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013327554100007 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 22 ---- target/arm/kvm.c | 265 +++++++++++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 254 ----------------------------------------- 3 files changed, 265 insertions(+), 276 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 58c087207f5..e59d713973c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -214,28 +214,6 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *= cpus_to_try, */ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); =20 -/** - * ARMHostCPUFeatures: information about the host CPU (identified - * by asking the host kernel) - */ -typedef struct ARMHostCPUFeatures { - ARMISARegisters isar; - uint64_t features; - uint32_t target; - const char *dtb_compatible; -} ARMHostCPUFeatures; - -/** - * kvm_arm_get_host_cpu_features: - * @ahcf: ARMHostCPUClass to fill in - * - * Probe the capabilities of the host kernel's preferred CPU and fill - * in the ARMHostCPUClass struct accordingly. - * - * Returns true on success and false otherwise. - */ -bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf); - /** * kvm_arm_sve_get_vls: * @cs: CPUState diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 84f300c602b..ffe0db42933 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -41,6 +41,17 @@ static bool cap_has_mp_state; static bool cap_has_inject_serror_esr; static bool cap_has_inject_ext_dabt; =20 +/** + * ARMHostCPUFeatures: information about the host CPU (identified + * by asking the host kernel) + */ +typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; + uint64_t features; + uint32_t target; + const char *dtb_compatible; +} ARMHostCPUFeatures; + static ARMHostCPUFeatures arm_host_cpu_features; =20 int kvm_arm_vcpu_init(CPUState *cs) @@ -167,6 +178,260 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray) } } =20 +static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) +{ + uint64_t ret; + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)&ret }; + int err; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + err =3D ioctl(fd, KVM_GET_ONE_REG, &idreg); + if (err < 0) { + return -1; + } + *pret =3D ret; + return 0; +} + +static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) +{ + struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; + + assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); + return ioctl(fd, KVM_GET_ONE_REG, &idreg); +} + +static bool kvm_arm_pauth_supported(void) +{ + return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && + kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); +} + +static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +{ + /* Identify the feature bits corresponding to the host CPU, and + * fill out the ARMHostCPUClass fields accordingly. To do this + * we have to create a scratch VM, create a single CPU inside it, + * and then query that CPU for the relevant ID registers. + */ + int fdarray[3]; + bool sve_supported; + bool pmu_supported =3D false; + uint64_t features =3D 0; + int err; + + /* Old kernels may not know about the PREFERRED_TARGET ioctl: however + * we know these will only support creating one kind of guest CPU, + * which is its preferred CPU type. Fortunately these old kernels + * support only a very limited number of CPUs. + */ + static const uint32_t cpus_to_try[] =3D { + KVM_ARM_TARGET_AEM_V8, + KVM_ARM_TARGET_FOUNDATION_V8, + KVM_ARM_TARGET_CORTEX_A57, + QEMU_KVM_ARM_TARGET_NONE + }; + /* + * target =3D -1 informs kvm_arm_create_scratch_host_vcpu() + * to use the preferred target + */ + struct kvm_vcpu_init init =3D { .target =3D -1, }; + + /* + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, + * which is otherwise RAZ. + */ + sve_supported =3D kvm_arm_sve_supported(); + if (sve_supported) { + init.features[0] |=3D 1 << KVM_ARM_VCPU_SVE; + } + + /* + * Ask for Pointer Authentication if supported, so that we get + * the unsanitized field values for AA64ISAR1_EL1. + */ + if (kvm_arm_pauth_supported()) { + init.features[0] |=3D (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | + 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); + } + + if (kvm_arm_pmu_supported()) { + init.features[0] |=3D 1 << KVM_ARM_VCPU_PMU_V3; + pmu_supported =3D true; + } + + if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { + return false; + } + + ahcf->target =3D init.target; + ahcf->dtb_compatible =3D "arm,arm-v8"; + + err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, + ARM64_SYS_REG(3, 0, 0, 4, 0)); + if (unlikely(err < 0)) { + /* + * Before v4.15, the kernel only exposed a limited number of system + * registers, not including any of the interesting AArch64 ID regs. + * For the most part we could leave these fields as zero with mini= mal + * effect, since this does not affect the values seen by the guest. + * + * However, it could cause problems down the line for QEMU, + * so provide a minimal v8.0 default. + * + * ??? Could read MIDR and use knowledge from cpu64.c. + * ??? Could map a page of memory into our temp guest and + * run the tiniest of hand-crafted kernels to extract + * the values seen by the guest. + * ??? Either of these sounds like too much effort just + * to work around running a modern host kernel. + */ + ahcf->isar.id_aa64pfr0 =3D 0x00000011; /* EL1&0, AArch64 only */ + err =3D 0; + } else { + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, + ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, + ARM64_SYS_REG(3, 0, 0, 4, 5)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, + ARM64_SYS_REG(3, 0, 0, 5, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, + ARM64_SYS_REG(3, 0, 0, 5, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, + ARM64_SYS_REG(3, 0, 0, 6, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, + ARM64_SYS_REG(3, 0, 0, 6, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, + ARM64_SYS_REG(3, 0, 0, 6, 2)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, + ARM64_SYS_REG(3, 0, 0, 7, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, + ARM64_SYS_REG(3, 0, 0, 7, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, + ARM64_SYS_REG(3, 0, 0, 7, 2)); + + /* + * Note that if AArch32 support is not present in the host, + * the AArch32 sysregs are present to be read, but will + * return UNKNOWN values. This is neither better nor worse + * than skipping the reads and leaving 0, as we must avoid + * considering the values in every case. + */ + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, + ARM64_SYS_REG(3, 0, 0, 1, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, + ARM64_SYS_REG(3, 0, 0, 1, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, + ARM64_SYS_REG(3, 0, 0, 1, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, + ARM64_SYS_REG(3, 0, 0, 1, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, + ARM64_SYS_REG(3, 0, 0, 1, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, + ARM64_SYS_REG(3, 0, 0, 1, 6)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, + ARM64_SYS_REG(3, 0, 0, 1, 7)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, + ARM64_SYS_REG(3, 0, 0, 2, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, + ARM64_SYS_REG(3, 0, 0, 2, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, + ARM64_SYS_REG(3, 0, 0, 2, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, + ARM64_SYS_REG(3, 0, 0, 2, 3)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, + ARM64_SYS_REG(3, 0, 0, 2, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, + ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, + ARM64_SYS_REG(3, 0, 0, 2, 6)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, + ARM64_SYS_REG(3, 0, 0, 2, 7)); + + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, + ARM64_SYS_REG(3, 0, 0, 3, 0)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, + ARM64_SYS_REG(3, 0, 0, 3, 1)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, + ARM64_SYS_REG(3, 0, 0, 3, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, + ARM64_SYS_REG(3, 0, 0, 3, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, + ARM64_SYS_REG(3, 0, 0, 3, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, + ARM64_SYS_REG(3, 0, 0, 3, 6)); + + /* + * DBGDIDR is a bit complicated because the kernel doesn't + * provide an accessor for it in 64-bit mode, which is what this + * scratch VM is in, and there's no architected "64-bit sysreg + * which reads the same as the 32-bit register" the way there is + * for other ID registers. Instead we synthesize a value from the + * AArch64 ID_AA64DFR0, the same way the kernel code in + * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. + * We only do this if the CPU supports AArch32 at EL1. + */ + if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2) { + int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); + int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); + int ctx_cmps =3D + FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); + int version =3D 6; /* ARMv8 debug architecture */ + bool has_el3 =3D + !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); + uint32_t dbgdidr =3D 0; + + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); + dbgdidr |=3D (1 << 15); /* RES1 bit */ + ahcf->isar.dbgdidr =3D dbgdidr; + } + + if (pmu_supported) { + /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 = */ + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, + ARM64_SYS_REG(3, 3, 9, 12, 0)); + } + + if (sve_supported) { + /* + * There is a range of kernels between kernel commit 73433762f= cae + * and f81cb2c3ad41 which have a bug where the kernel doesn't + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the V= M has + * enabled SVE support, which resulted in an error rather than= RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. + */ + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, + ARM64_SYS_REG(3, 0, 0, 4, 4)); + } + } + + kvm_arm_destroy_scratch_host_vcpu(fdarray); + + if (err < 0) { + return false; + } + + /* + * We can assume any KVM supporting CPU is at least a v8 + * with VFPv4+Neon; this in turn implies most of the other + * feature bits. + */ + features |=3D 1ULL << ARM_FEATURE_V8; + features |=3D 1ULL << ARM_FEATURE_NEON; + features |=3D 1ULL << ARM_FEATURE_AARCH64; + features |=3D 1ULL << ARM_FEATURE_PMU; + features |=3D 1ULL << ARM_FEATURE_GENERIC_TIMER; + + ahcf->features =3D features; + + return true; +} + void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index fca4864b739..504526b24c9 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -143,260 +143,6 @@ void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) } } =20 -static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id) -{ - uint64_t ret; - struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)&ret }; - int err; - - assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); - err =3D ioctl(fd, KVM_GET_ONE_REG, &idreg); - if (err < 0) { - return -1; - } - *pret =3D ret; - return 0; -} - -static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id) -{ - struct kvm_one_reg idreg =3D { .id =3D id, .addr =3D (uintptr_t)pret }; - - assert((id & KVM_REG_SIZE_MASK) =3D=3D KVM_REG_SIZE_U64); - return ioctl(fd, KVM_GET_ONE_REG, &idreg); -} - -static bool kvm_arm_pauth_supported(void) -{ - return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) && - kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC)); -} - -bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) -{ - /* Identify the feature bits corresponding to the host CPU, and - * fill out the ARMHostCPUClass fields accordingly. To do this - * we have to create a scratch VM, create a single CPU inside it, - * and then query that CPU for the relevant ID registers. - */ - int fdarray[3]; - bool sve_supported; - bool pmu_supported =3D false; - uint64_t features =3D 0; - int err; - - /* Old kernels may not know about the PREFERRED_TARGET ioctl: however - * we know these will only support creating one kind of guest CPU, - * which is its preferred CPU type. Fortunately these old kernels - * support only a very limited number of CPUs. - */ - static const uint32_t cpus_to_try[] =3D { - KVM_ARM_TARGET_AEM_V8, - KVM_ARM_TARGET_FOUNDATION_V8, - KVM_ARM_TARGET_CORTEX_A57, - QEMU_KVM_ARM_TARGET_NONE - }; - /* - * target =3D -1 informs kvm_arm_create_scratch_host_vcpu() - * to use the preferred target - */ - struct kvm_vcpu_init init =3D { .target =3D -1, }; - - /* - * Ask for SVE if supported, so that we can query ID_AA64ZFR0, - * which is otherwise RAZ. - */ - sve_supported =3D kvm_arm_sve_supported(); - if (sve_supported) { - init.features[0] |=3D 1 << KVM_ARM_VCPU_SVE; - } - - /* - * Ask for Pointer Authentication if supported, so that we get - * the unsanitized field values for AA64ISAR1_EL1. - */ - if (kvm_arm_pauth_supported()) { - init.features[0] |=3D (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | - 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); - } - - if (kvm_arm_pmu_supported()) { - init.features[0] |=3D 1 << KVM_ARM_VCPU_PMU_V3; - pmu_supported =3D true; - } - - if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) { - return false; - } - - ahcf->target =3D init.target; - ahcf->dtb_compatible =3D "arm,arm-v8"; - - err =3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0, - ARM64_SYS_REG(3, 0, 0, 4, 0)); - if (unlikely(err < 0)) { - /* - * Before v4.15, the kernel only exposed a limited number of system - * registers, not including any of the interesting AArch64 ID regs. - * For the most part we could leave these fields as zero with mini= mal - * effect, since this does not affect the values seen by the guest. - * - * However, it could cause problems down the line for QEMU, - * so provide a minimal v8.0 default. - * - * ??? Could read MIDR and use knowledge from cpu64.c. - * ??? Could map a page of memory into our temp guest and - * run the tiniest of hand-crafted kernels to extract - * the values seen by the guest. - * ??? Either of these sounds like too much effort just - * to work around running a modern host kernel. - */ - ahcf->isar.id_aa64pfr0 =3D 0x00000011; /* EL1&0, AArch64 only */ - err =3D 0; - } else { - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, - ARM64_SYS_REG(3, 0, 0, 4, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0, - ARM64_SYS_REG(3, 0, 0, 4, 5)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, - ARM64_SYS_REG(3, 0, 0, 5, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, - ARM64_SYS_REG(3, 0, 0, 5, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, - ARM64_SYS_REG(3, 0, 0, 6, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, - ARM64_SYS_REG(3, 0, 0, 6, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, - ARM64_SYS_REG(3, 0, 0, 6, 2)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, - ARM64_SYS_REG(3, 0, 0, 7, 0)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, - ARM64_SYS_REG(3, 0, 0, 7, 1)); - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, - ARM64_SYS_REG(3, 0, 0, 7, 2)); - - /* - * Note that if AArch32 support is not present in the host, - * the AArch32 sysregs are present to be read, but will - * return UNKNOWN values. This is neither better nor worse - * than skipping the reads and leaving 0, as we must avoid - * considering the values in every case. - */ - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, - ARM64_SYS_REG(3, 0, 0, 1, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1, - ARM64_SYS_REG(3, 0, 0, 1, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, - ARM64_SYS_REG(3, 0, 0, 1, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, - ARM64_SYS_REG(3, 0, 0, 1, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, - ARM64_SYS_REG(3, 0, 0, 1, 5)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, - ARM64_SYS_REG(3, 0, 0, 1, 6)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, - ARM64_SYS_REG(3, 0, 0, 1, 7)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, - ARM64_SYS_REG(3, 0, 0, 2, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, - ARM64_SYS_REG(3, 0, 0, 2, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2, - ARM64_SYS_REG(3, 0, 0, 2, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3, - ARM64_SYS_REG(3, 0, 0, 2, 3)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4, - ARM64_SYS_REG(3, 0, 0, 2, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, - ARM64_SYS_REG(3, 0, 0, 2, 5)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, - ARM64_SYS_REG(3, 0, 0, 2, 6)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, - ARM64_SYS_REG(3, 0, 0, 2, 7)); - - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, - ARM64_SYS_REG(3, 0, 0, 3, 0)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1, - ARM64_SYS_REG(3, 0, 0, 3, 1)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, - ARM64_SYS_REG(3, 0, 0, 3, 2)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2, - ARM64_SYS_REG(3, 0, 0, 3, 4)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1, - ARM64_SYS_REG(3, 0, 0, 3, 5)); - err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5, - ARM64_SYS_REG(3, 0, 0, 3, 6)); - - /* - * DBGDIDR is a bit complicated because the kernel doesn't - * provide an accessor for it in 64-bit mode, which is what this - * scratch VM is in, and there's no architected "64-bit sysreg - * which reads the same as the 32-bit register" the way there is - * for other ID registers. Instead we synthesize a value from the - * AArch64 ID_AA64DFR0, the same way the kernel code in - * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. - * We only do this if the CPU supports AArch32 at EL1. - */ - if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2) { - int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); - int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); - int ctx_cmps =3D - FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); - int version =3D 6; /* ARMv8 debug architecture */ - bool has_el3 =3D - !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); - uint32_t dbgdidr =3D 0; - - dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); - dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); - dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); - dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); - dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); - dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); - dbgdidr |=3D (1 << 15); /* RES1 bit */ - ahcf->isar.dbgdidr =3D dbgdidr; - } - - if (pmu_supported) { - /* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 = */ - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, - ARM64_SYS_REG(3, 3, 9, 12, 0)); - } - - if (sve_supported) { - /* - * There is a range of kernels between kernel commit 73433762f= cae - * and f81cb2c3ad41 which have a bug where the kernel doesn't - * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the V= M has - * enabled SVE support, which resulted in an error rather than= RAZ. - * So only read the register if we set KVM_ARM_VCPU_SVE above. - */ - err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, - ARM64_SYS_REG(3, 0, 0, 4, 4)); - } - } - - kvm_arm_destroy_scratch_host_vcpu(fdarray); - - if (err < 0) { - return false; - } - - /* - * We can assume any KVM supporting CPU is at least a v8 - * with VFPv4+Neon; this in turn implies most of the other - * feature bits. - */ - features |=3D 1ULL << ARM_FEATURE_V8; - features |=3D 1ULL << ARM_FEATURE_NEON; - features |=3D 1ULL << ARM_FEATURE_AARCH64; - features |=3D 1ULL << ARM_FEATURE_PMU; - features |=3D 1ULL << ARM_FEATURE_GENERIC_TIMER; - - ahcf->features =3D features; - - return true; -} - void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) { bool has_steal_time =3D kvm_check_extension(kvm_state, KVM_CAP_STEAL_T= IME); --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013332; cv=none; d=zohomail.com; s=zohoarc; b=gtyL9fjSOuQ6TIKiuZvUMo0knIx/BNDTZ19Pu5Mxg38UBuGeLf0C1K/4JOFRAFbBiU9N1cA9DkJ5R6KAzHD2w/+6ux3CTe3ojkxfnqIEbbif6kUiAkIhNaxRwTcKu4RXIQ/B2G7ANrizPket2sMwB3BENFfov4jEPUhx+Gcrm8s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013332; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=8U4Zs7qJxd6knz6FwIYeN/wpMsd6G/tgH0Hh4NzLuf8=; b=m8BXRxw4oy0XoDu1l/yITYQzL2/Il/hCSUawiIZncYFl/TnjANqm1YzXvxa6e1jDASNw4fFis4qAqYBL/81Y2HeXmZOnEQ2lsdqSyRpvgnP2BlOveP7FGIy4LCjJls6PHzizmUz2mo0U0D1ULCjWF+TRRyGKLqYbGFlORttjqbI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013332457875.7631682230725; Tue, 19 Dec 2023 11:15:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWr-0001qP-6o; Tue, 19 Dec 2023 14:13:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWn-0001mm-RI for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:17 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWm-0001mV-4T for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:17 -0500 Received: by mail-wr1-x435.google.com with SMTP id ffacd0b85a97d-3365752934bso3970994f8f.2 for ; Tue, 19 Dec 2023 11:13:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013195; x=1703617995; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=8U4Zs7qJxd6knz6FwIYeN/wpMsd6G/tgH0Hh4NzLuf8=; b=hFRYK+EZzJlMEj1vJrSHIrtegxjCqDKtl6c0uvqwddXz/q1ktdKV8VWbH3Ip3vC15d uGV8lVfcoeG4O66uVIiyyYXjdEmA64db/JRidmZ5PZzlrpSnCvQ5MFYEkJGOaCLwcPHG Gqz6t6K6y9qz4DIdiIxOdtuayLO600pLzjNCMTt3arFxr67++8VLAK8eTVbBSuZQi8aY syvUIAXsM7Yb5Eqk/xnxMyxDSumTnq/4oCkZ+6BT6LJqbDuu1FD6emHkkZZYMpIybmD0 N9TptXU+xeOmtQ8/8EZtnDTlHMZ9ad/qLLSGIsQseGJA+RGZu73x0ikdE+LRsy0kVJ0V 7KUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013195; x=1703617995; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8U4Zs7qJxd6knz6FwIYeN/wpMsd6G/tgH0Hh4NzLuf8=; b=XkzaPZFgN2lY+S2qwPDbpRruXB7SwIWoZCZR41eOqCYVy5orWPXgHfsNq8K4rh9oUa +JKZy/TrWMn02yYvffiOp2nTow28yu/aF6dGHXxxBcZh2heAkwKGxM2+J1BmzVXzMbFc V74s9NQPWnk8g152eEKUsxWGoPpg0lH6az534otr+auu/3VFnQsJKUyMkYAJEcDH3GFF ktcDBs8PKnm/RLV0A5t/PZmzrHyrl9L/fasOBf+ZhJaIGnJg8oR8Fza3a1C02dhono5P IeVFJj4NoXLD4Kaypm98sbq5pVvCWRE3ZyXfJ8n3sMYh7MDQDMfEawr4RWA5QKeLjbyE ihsw== X-Gm-Message-State: AOJu0Yy1g7f8qJmfhRxRJH8/FamPCrXkDb1QgvpVc+1F016bz5Z7V9tR 8d9oQQ8y3FYXpYcP+aRyTaPi/v/gqbEI1eN+H1U= X-Google-Smtp-Source: AGHT+IH1/cCtSrt/d+C0VIqOntWMnfw5yxhYE4kNINzg+jk1tFk4qMwl8c8YTfYhk+axkaG+yExtOg== X-Received: by 2002:a5d:4c4a:0:b0:336:7793:6ab2 with SMTP id n10-20020a5d4c4a000000b0033677936ab2mr297538wrt.143.1703013194661; Tue, 19 Dec 2023 11:13:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/43] target/arm/kvm: Use a switch for kvm_arm_cpreg_level Date: Tue, 19 Dec 2023 19:12:35 +0000 Message-Id: <20231219191307.2895919-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013333456100005 From: Richard Henderson Use a switch instead of a linear search through data. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 32 +++++++++----------------------- 1 file changed, 9 insertions(+), 23 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 504526b24c9..61fb9dbde0e 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -361,32 +361,18 @@ bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) } } =20 -typedef struct CPRegStateLevel { - uint64_t regidx; - int level; -} CPRegStateLevel; - -/* All system registers not listed in the following table are assumed to be - * of the level KVM_PUT_RUNTIME_STATE. If a register should be written less - * often, you must add it to this table with a state of either - * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. - */ -static const CPRegStateLevel non_runtime_cpregs[] =3D { - { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE }, - { KVM_REG_ARM_PTIMER_CNT, KVM_PUT_FULL_STATE }, -}; - int kvm_arm_cpreg_level(uint64_t regidx) { - int i; - - for (i =3D 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) { - const CPRegStateLevel *l =3D &non_runtime_cpregs[i]; - if (l->regidx =3D=3D regidx) { - return l->level; - } + /* + * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. + * If a register should be written less often, you must add it here + * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. + */ + switch (regidx) { + case KVM_REG_ARM_TIMER_CNT: + case KVM_REG_ARM_PTIMER_CNT: + return KVM_PUT_FULL_STATE; } - return KVM_PUT_RUNTIME_STATE; } =20 --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013552; cv=none; d=zohomail.com; s=zohoarc; b=bONXcsIJvTCMU0QSawghaE26g82VLfsehv713/afjgw1Q6PurZwQq00TBlgLly81p8sRA5RxgUZIqBTxnOnwxsZUqNFmzJe3IfteTBCozslgiupDkVZm1lotpXGkjq+8KGmyskCxKeLltyqDtQF2jImQeXjDKDRkEgxJDBO/WJU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013552; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DVfybjnXHAr4/V+3lIJ59fueYndSiVdNpHGHcmYVDg8=; b=TBx0/+/lVHmJbzCEO4In6aTpZiqi1U9jQ3HuOD9ZxXdo5HrsKGxi6b8rHsWpW0daou1OIs94eDvF9wIi3IUs6DqzHrlkZ2KxBMnJZ9yfsutQ0xMqTUsBba+Gn/Ia1I7u0g9RCqyQTULahw3xcyOcRfxwBgPhguKCEmfnqQYMYig= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013552954444.26500522390427; Tue, 19 Dec 2023 11:19:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWs-0001tH-BU; Tue, 19 Dec 2023 14:13:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWp-0001oS-3P for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:19 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWn-0001me-Dp for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:18 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-40c2bb872e2so56131095e9.3 for ; Tue, 19 Dec 2023 11:13:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013195; x=1703617995; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DVfybjnXHAr4/V+3lIJ59fueYndSiVdNpHGHcmYVDg8=; b=NVHbqSqQ1yjGgRAgwvsIeaYyrQR4hjWsMna0yYbWCFopYFWmn9OFanluPKo3AKS7LO 3td7NwJ4jwuR5GNJli5ovPJELgTwBrzq2Yir6lRFc1oP9pfuN9SeaseL63gNpRc0hMGq 2Rw41t2a01S0U3x+uVqCS6OYSicYBipxNMzVQcaWg5cRFpa/zQm1ucFqoCtwxj34/4sb PdTWtOvQSI96+O+xp+CIarVmyRQU8QCgjZJ6kRILp7YSejA5WAbEfFkCxadu6yALy52d 8+wQ/W4wxFtvPE7Rp1AV/h8M+Od2IbfeW94mq1nT7+sCmu59/v40lRY92f/xyr5y5/18 EpSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013195; x=1703617995; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DVfybjnXHAr4/V+3lIJ59fueYndSiVdNpHGHcmYVDg8=; b=iC/TKz4T44JRGCevDNQB16vlDFJgzHIenCN72LpuUjAFqwWO86FFgVssNOcSwEIPI6 OduiU6klcrwBz6J7FtRT/4R+vDWMAVdrgwOnG4h+C+zug4Ykg1R01181faAFqk8GhFmQ XUdpfgfaZ5kdft01UUMk9yGPbmuPdgHBInZ2Lpzg4391P32LSQygSHnF8BL1Z1kuvyQo Uv09QPFVYRefW9oDOcJO8V/NHLP+Hael3NdyT1dPMhdZE4mo4xvow/1msoLZ5gVnzhMq sgVSlXkeVmxY8TcGUdq5ymA8YL0fHn7lozr2kWu0sfXPtOU9orGzS1dEm4RRJXkGy5qc pDRA== X-Gm-Message-State: AOJu0Yx2l+dZeDSBUmWwzMkVy8NMsAlBq0W1gu5bBTo9bVGmJoR1Iofq vxrGRm0eAWV4X+USVBptfgvIqPoa73PKtWTI4mE= X-Google-Smtp-Source: AGHT+IFVWFG9+0vDERMRUWb/dIgkuf6FvVWzqcCize+W73dPTLroIamKGCOZ3kddeWTw8wxLtI9q+Q== X-Received: by 2002:a05:600c:ac6:b0:40c:310b:b694 with SMTP id c6-20020a05600c0ac600b0040c310bb694mr4338989wmr.333.1703013195040; Tue, 19 Dec 2023 11:13:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/43] target/arm/kvm: Move kvm_arm_cpreg_level and unexport Date: Tue, 19 Dec 2023 19:12:36 +0000 Message-Id: <20231219191307.2895919-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013554904100003 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 9 --------- target/arm/kvm.c | 22 ++++++++++++++++++++++ target/arm/kvm64.c | 15 --------------- 3 files changed, 22 insertions(+), 24 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index e59d713973c..2755ee83666 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -87,15 +87,6 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu); */ bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx); =20 -/** - * kvm_arm_cpreg_level: - * @regidx: KVM register index - * - * Return the level of this coprocessor/system register. Return value is - * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STAT= E. - */ -int kvm_arm_cpreg_level(uint64_t regidx); - /** * write_list_to_kvmstate: * @cpu: ARMCPU diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ffe0db42933..dadc3fd7552 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -817,6 +817,28 @@ out: return ret; } =20 +/** + * kvm_arm_cpreg_level: + * @regidx: KVM register index + * + * Return the level of this coprocessor/system register. Return value is + * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STAT= E. + */ +static int kvm_arm_cpreg_level(uint64_t regidx) +{ + /* + * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. + * If a register should be written less often, you must add it here + * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. + */ + switch (regidx) { + case KVM_REG_ARM_TIMER_CNT: + case KVM_REG_ARM_PTIMER_CNT: + return KVM_PUT_FULL_STATE; + } + return KVM_PUT_RUNTIME_STATE; +} + bool write_kvmstate_to_list(ARMCPU *cpu) { CPUState *cs =3D CPU(cpu); diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 61fb9dbde0e..a184cca4dc8 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -361,21 +361,6 @@ bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) } } =20 -int kvm_arm_cpreg_level(uint64_t regidx) -{ - /* - * All system registers are assumed to be level KVM_PUT_RUNTIME_STATE. - * If a register should be written less often, you must add it here - * with a state of either KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE. - */ - switch (regidx) { - case KVM_REG_ARM_TIMER_CNT: - case KVM_REG_ARM_PTIMER_CNT: - return KVM_PUT_FULL_STATE; - } - return KVM_PUT_RUNTIME_STATE; -} - /* Callers must hold the iothread mutex lock */ static void kvm_inject_arm_sea(CPUState *c) { --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013575; cv=none; d=zohomail.com; s=zohoarc; b=RZWrTfdbCSRCigTd7TFuYoO6c7qhGFqszt2K6wzLc3NILPu8TmZboeDmgr8/Az8OcKvUiswsNrARJhoZ1Tr6m8bAUDr6Dnu9I5dLAXwSAvgAdKzs0KElZoSuE0G/AyGQuOjX2fZ6o2EFy0NffDPbJboP3FdEnPcP8t3okPVDuEw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013575; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ejx0o35FpPOYFf9Do/QdMe6kWwuD6p6Hfkcy2GrwUgw=; b=CuTByZTY5RoTpV9rB5hAR9izFrO8T/liKlTyB5PdOKnCxEQdP+YP/NbpcsUmdVNEBJbgSB5WY6dRDEfDCK3aajLsQRsCwEvd5X+OWR8tpQzh2QV849nweF5NrcHV72mA//Pj7ea+LxKEB7MtcdL2lQXhQituHGb1qjvpYeRMGX0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013575838533.3040120002288; Tue, 19 Dec 2023 11:19:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWs-0001sw-4E; Tue, 19 Dec 2023 14:13:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWp-0001oe-Js for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:19 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWn-0001mk-Rl for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:19 -0500 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-3366e78d872so2078437f8f.3 for ; Tue, 19 Dec 2023 11:13:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013195; x=1703617995; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ejx0o35FpPOYFf9Do/QdMe6kWwuD6p6Hfkcy2GrwUgw=; b=GY2orO2KI3BUi4q1ZASWoaHPIDc0bBYAeAaECnUdYinNx4glZYCY5gsayjMxbWw9WN cKwfcpXYZ83QZUedysBscGKyNPf+wVqJBatQ/PsZOLS+9+6ZZjBheknX8qpLQcZ/SzrC Emu2O0Ti/BAH9JcR0MVR23tGHrKlal3yGXZcMcZM+ZYWTY9KOqTc6NblorMPa1xEscKX 26qprddahm1aFywbIMGDLMFFietGM56mq3e8nyuGFeWtfa+WB4RV/cpcpM93dSAn1/QF O0vzq73eBuju+aOIa5Am7furj6MrKEM3B3q+sW5CaqFgUjiTBXF4X7XoSKI2hgsuMC63 kRng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013195; x=1703617995; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013576969100001 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 [PMM: merged two duplicate comments, as suggested by Gavin] Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 10 ---------- target/arm/kvm.c | 19 +++++++++++++++++++ target/arm/kvm64.c | 15 --------------- 3 files changed, 19 insertions(+), 25 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 2755ee83666..1043123cc7a 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -77,16 +77,6 @@ void kvm_arm_register_device(MemoryRegion *mr, uint64_t = devid, uint64_t group, */ int kvm_arm_init_cpreg_list(ARMCPU *cpu); =20 -/** - * kvm_arm_reg_syncs_via_cpreg_list: - * @regidx: KVM register index - * - * Return true if this KVM register should be synchronized via the - * cpreg list of arbitrary system registers, false if it is synchronized - * by hand using code in kvm_arch_get/put_registers(). - */ -bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx); - /** * write_list_to_kvmstate: * @cpu: ARMCPU diff --git a/target/arm/kvm.c b/target/arm/kvm.c index dadc3fd7552..05e06f1008b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -740,6 +740,25 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, ui= nt64_t regidx) return &cpu->cpreg_values[res - cpu->cpreg_indexes]; } =20 +/** + * kvm_arm_reg_syncs_via_cpreg_list: + * @regidx: KVM register index + * + * Return true if this KVM register should be synchronized via the + * cpreg list of arbitrary system registers, false if it is synchronized + * by hand using code in kvm_arch_get/put_registers(). + */ +static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) +{ + switch (regidx & KVM_REG_ARM_COPROC_MASK) { + case KVM_REG_ARM_CORE: + case KVM_REG_ARM64_SVE: + return false; + default: + return true; + } +} + /* Initialize the ARMCPU cpreg list according to the kernel's * definition of what CPU registers it knows about (and throw away * the previous TCG-created cpreg list). diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index a184cca4dc8..52c0a6d3af5 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -346,21 +346,6 @@ int kvm_arch_destroy_vcpu(CPUState *cs) return 0; } =20 -bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx) -{ - /* Return true if the regidx is a register we should synchronize - * via the cpreg_tuples array (ie is not a core or sve reg that - * we sync by hand in kvm_arch_get/put_registers()) - */ - switch (regidx & KVM_REG_ARM_COPROC_MASK) { - case KVM_REG_ARM_CORE: - case KVM_REG_ARM64_SVE: - return false; - default: - return true; - } -} - /* Callers must hold the iothread mutex lock */ static void kvm_inject_arm_sea(CPUState *c) { --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013196; x=1703617996; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Vp9XJAjKcxMmxu0j7HQPaxuHAjl344JRRVzGYFjAl1o=; b=dG5NOtlF4nfes31+i9N62cIPTO+GbJQBpnMS9CxflWOnzwb2viXTlI+I6NRvFvSLQf TVDx5aMjFNhDhK5O+r9syyKXkeIXaezwE9ROqGhMF4CEiQEFZpbl4R8iPH5AyRl1heN6 4idRmvfBZnyJ/FUbYpbvuPUYer2pgN8uHWQwHsyjWEKrYtijeI/tSy8EwF0HEv7sma0k Eakz8GzKF1U5ixNg+p+GFEdv+dYgyaZmqDPiUAfhn4NMfxjtkA4EhKXGhx/C/xTXDLEl XO+yt3UnJ0B7/N3tFWcX90aYT2tZj7CGCkRprIO9CwhmRgl+7aqLg7qHih+89MmZ9jmt QYkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013196; x=1703617996; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vp9XJAjKcxMmxu0j7HQPaxuHAjl344JRRVzGYFjAl1o=; b=PTowTTcVvnilvI0evk1uINbOdFmx/tjc+2HgfcstaF38s6dKm1L0RlIV4kmaNuozri H82Ac6biILOJsswC7PqtzGKqO57MjGncAihMX50rRirbpdktIsKwTwnbpA0y7IWeOctA UCx9ZiUPyypWuNyi9HCOUZakmBLrZEd183cekJeDgaPgImyLYhRYQMqlmF0WZ7gqrMgu 39LEKh1uMMYAxIV/JclXU5F2KTqVVWeh5kLgnEy2PaYBBEUxBdFshY/Zy7CilDG571Hf dkLakp1LdbcSw6HkS2IR6+9tj+DxGpv2dZSsNMtb5ScGyKDxGOH4g7uLnXaUz8+tUxbQ lHIw== X-Gm-Message-State: AOJu0Yx7vCR5INtUhfOh8RVM7itn8JbRAxlVUoEdJ0YfYaQObLHAQRmo gLDpZNefdc/pCindHbW9kEFLhmVDTHNe3hCiLZo= X-Google-Smtp-Source: AGHT+IEjXPxeUO4BILPVQP5erEVg4uYyHyeN5T5jT5mtCbBbpw1LLTWUwuS6hvh9LbAONtsSyEN/Sw== X-Received: by 2002:a05:600c:4587:b0:40c:6e0b:69d3 with SMTP id r7-20020a05600c458700b0040c6e0b69d3mr3607434wmo.1.1703013196195; Tue, 19 Dec 2023 11:13:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/43] target/arm/kvm: Merge kvm64.c into kvm.c Date: Tue, 19 Dec 2023 19:12:38 +0000 Message-Id: <20231219191307.2895919-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013733654100005 From: Richard Henderson Since kvm32.c was removed, there is no need to keep them separate. This will allow more symbols to be unexported. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 [PMM: retain copyright lines from kvm64.c in kvm.c] Signed-off-by: Peter Maydell --- target/arm/kvm.c | 791 +++++++++++++++++++++++++++++++++++++++ target/arm/kvm64.c | 820 ----------------------------------------- target/arm/meson.build | 2 +- 3 files changed, 792 insertions(+), 821 deletions(-) delete mode 100644 target/arm/kvm64.c diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 05e06f1008b..ab797409f13 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -2,6 +2,8 @@ * ARM implementation of KVM hooks * * Copyright Christoffer Dall 2009-2010 + * Copyright Mian-M. Hamayun 2013, Virtual Open Systems + * Copyright Alex Benn=C3=A9e 2014, Linaro * * This work is licensed under the terms of the GNU GPL, version 2 or late= r. * See the COPYING file in the top-level directory. @@ -19,6 +21,7 @@ #include "qom/object.h" #include "qapi/error.h" #include "sysemu/sysemu.h" +#include "sysemu/runstate.h" #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "kvm_arm.h" @@ -28,10 +31,13 @@ #include "hw/pci/pci.h" #include "exec/memattrs.h" #include "exec/address-spaces.h" +#include "exec/gdbstub.h" #include "hw/boards.h" #include "hw/irq.h" #include "qapi/visitor.h" #include "qemu/log.h" +#include "hw/acpi/acpi.h" +#include "hw/acpi/ghes.h" =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO @@ -1610,3 +1616,788 @@ void kvm_arch_accel_class_init(ObjectClass *oc) object_class_property_set_description(oc, "eager-split-size", "Eager Page Split chunk size for hugepages. (default: 0, disabled)= "); } + +int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) +{ + switch (type) { + case GDB_BREAKPOINT_HW: + return insert_hw_breakpoint(addr); + break; + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_ACCESS: + return insert_hw_watchpoint(addr, len, type); + default: + return -ENOSYS; + } +} + +int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) +{ + switch (type) { + case GDB_BREAKPOINT_HW: + return delete_hw_breakpoint(addr); + case GDB_WATCHPOINT_READ: + case GDB_WATCHPOINT_WRITE: + case GDB_WATCHPOINT_ACCESS: + return delete_hw_watchpoint(addr, len, type); + default: + return -ENOSYS; + } +} + +void kvm_arch_remove_all_hw_breakpoints(void) +{ + if (cur_hw_wps > 0) { + g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); + } + if (cur_hw_bps > 0) { + g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); + } +} + +static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *= attr, + const char *name) +{ + int err; + + err =3D kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); + if (err !=3D 0) { + error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); + return false; + } + + err =3D kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); + if (err !=3D 0) { + error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); + return false; + } + + return true; +} + +void kvm_arm_pmu_init(CPUState *cs) +{ + struct kvm_device_attr attr =3D { + .group =3D KVM_ARM_VCPU_PMU_V3_CTRL, + .attr =3D KVM_ARM_VCPU_PMU_V3_INIT, + }; + + if (!ARM_CPU(cs)->has_pmu) { + return; + } + if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { + error_report("failed to init PMU"); + abort(); + } +} + +void kvm_arm_pmu_set_irq(CPUState *cs, int irq) +{ + struct kvm_device_attr attr =3D { + .group =3D KVM_ARM_VCPU_PMU_V3_CTRL, + .addr =3D (intptr_t)&irq, + .attr =3D KVM_ARM_VCPU_PMU_V3_IRQ, + }; + + if (!ARM_CPU(cs)->has_pmu) { + return; + } + if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { + error_report("failed to set irq for PMU"); + abort(); + } +} + +void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) +{ + struct kvm_device_attr attr =3D { + .group =3D KVM_ARM_VCPU_PVTIME_CTRL, + .attr =3D KVM_ARM_VCPU_PVTIME_IPA, + .addr =3D (uint64_t)&ipa, + }; + + if (ARM_CPU(cs)->kvm_steal_time =3D=3D ON_OFF_AUTO_OFF) { + return; + } + if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) { + error_report("failed to init PVTIME IPA"); + abort(); + } +} + +void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) +{ + bool has_steal_time =3D kvm_check_extension(kvm_state, KVM_CAP_STEAL_T= IME); + + if (cpu->kvm_steal_time =3D=3D ON_OFF_AUTO_AUTO) { + if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64= )) { + cpu->kvm_steal_time =3D ON_OFF_AUTO_OFF; + } else { + cpu->kvm_steal_time =3D ON_OFF_AUTO_ON; + } + } else if (cpu->kvm_steal_time =3D=3D ON_OFF_AUTO_ON) { + if (!has_steal_time) { + error_setg(errp, "'kvm-steal-time' cannot be enabled " + "on this host"); + return; + } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + /* + * DEN0057A chapter 2 says "This specification only covers + * systems in which the Execution state of the hypervisor + * as well as EL1 of virtual machines is AArch64.". And, + * to ensure that, the smc/hvc calls are only specified as + * smc64/hvc64. + */ + error_setg(errp, "'kvm-steal-time' cannot be enabled " + "for AArch32 guests"); + return; + } + } +} + +bool kvm_arm_aarch32_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); +} + +bool kvm_arm_sve_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); +} + +QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN !=3D 1); + +uint32_t kvm_arm_sve_get_vls(CPUState *cs) +{ + /* Only call this function if kvm_arm_sve_supported() returns true. */ + static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; + static bool probed; + uint32_t vq =3D 0; + int i; + + /* + * KVM ensures all host CPUs support the same set of vector lengths. + * So we only need to create the scratch VCPUs once and then cache + * the results. + */ + if (!probed) { + struct kvm_vcpu_init init =3D { + .target =3D -1, + .features[0] =3D (1 << KVM_ARM_VCPU_SVE), + }; + struct kvm_one_reg reg =3D { + .id =3D KVM_REG_ARM64_SVE_VLS, + .addr =3D (uint64_t)&vls[0], + }; + int fdarray[3], ret; + + probed =3D true; + + if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) { + error_report("failed to create scratch VCPU with SVE enabled"); + abort(); + } + ret =3D ioctl(fdarray[2], KVM_GET_ONE_REG, ®); + kvm_arm_destroy_scratch_host_vcpu(fdarray); + if (ret) { + error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s", + strerror(errno)); + abort(); + } + + for (i =3D KVM_ARM64_SVE_VLS_WORDS - 1; i >=3D 0; --i) { + if (vls[i]) { + vq =3D 64 - clz64(vls[i]) + i * 64; + break; + } + } + if (vq > ARM_MAX_VQ) { + warn_report("KVM supports vector lengths larger than " + "QEMU can enable"); + vls[0] &=3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); + } + } + + return vls[0]; +} + +static int kvm_arm_sve_set_vls(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D { cpu->sve_vq.map }; + + assert(cpu->sve_max_vq <=3D KVM_ARM64_SVE_VQ_MAX); + + return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]); +} + +#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 + +int kvm_arch_init_vcpu(CPUState *cs) +{ + int ret; + uint64_t mpidr; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint64_t psciver; + + if (cpu->kvm_target =3D=3D QEMU_KVM_ARM_TARGET_NONE || + !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { + error_report("KVM is not supported for this guest CPU type"); + return -EINVAL; + } + + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); + + /* Determine init features for this CPU */ + memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); + if (cs->start_powered_off) { + cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_POWER_OFF; + } + if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { + cpu->psci_version =3D QEMU_PSCI_VERSION_0_2; + cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_PSCI_0_2; + } + if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_EL1_32BIT; + } + if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { + cpu->has_pmu =3D false; + } + if (cpu->has_pmu) { + cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_PMU_V3; + } else { + env->features &=3D ~(1ULL << ARM_FEATURE_PMU); + } + if (cpu_isar_feature(aa64_sve, cpu)) { + assert(kvm_arm_sve_supported()); + cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_SVE; + } + if (cpu_isar_feature(aa64_pauth, cpu)) { + cpu->kvm_init_features[0] |=3D (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | + 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); + } + + /* Do KVM_ARM_VCPU_INIT ioctl */ + ret =3D kvm_arm_vcpu_init(cs); + if (ret) { + return ret; + } + + if (cpu_isar_feature(aa64_sve, cpu)) { + ret =3D kvm_arm_sve_set_vls(cs); + if (ret) { + return ret; + } + ret =3D kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE); + if (ret) { + return ret; + } + } + + /* + * KVM reports the exact PSCI version it is implementing via a + * special sysreg. If it is present, use its contents to determine + * what to report to the guest in the dtb (it is the PSCI version, + * in the same 15-bits major 16-bits minor format that PSCI_VERSION + * returns). + */ + if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { + cpu->psci_version =3D psciver; + } + + /* + * When KVM is in use, PSCI is emulated in-kernel and not by qemu. + * Currently KVM has its own idea about MPIDR assignment, so we + * override our defaults with what we get from KVM. + */ + ret =3D kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); + if (ret) { + return ret; + } + cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; + + /* Check whether user space can specify guest syndrome value */ + kvm_arm_init_serror_injection(cs); + + return kvm_arm_init_cpreg_list(cpu); +} + +int kvm_arch_destroy_vcpu(CPUState *cs) +{ + return 0; +} + +/* Callers must hold the iothread mutex lock */ +static void kvm_inject_arm_sea(CPUState *c) +{ + ARMCPU *cpu =3D ARM_CPU(c); + CPUARMState *env =3D &cpu->env; + uint32_t esr; + bool same_el; + + c->exception_index =3D EXCP_DATA_ABORT; + env->exception.target_el =3D 1; + + /* + * Set the DFSC to synchronous external abort and set FnV to not valid, + * this will tell guest the FAR_ELx is UNKNOWN for this abort. + */ + same_el =3D arm_current_el(env) =3D=3D env->exception.target_el; + esr =3D syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); + + env->exception.syndrome =3D esr; + + arm_cpu_do_interrupt(c); +} + +#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ + KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) + +#define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \ + KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) + +#define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ + KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) + +static int kvm_arch_put_fpsimd(CPUState *cs) +{ + CPUARMState *env =3D &ARM_CPU(cs)->env; + int i, ret; + + for (i =3D 0; i < 32; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); +#if HOST_BIG_ENDIAN + uint64_t fp_val[2] =3D { q[1], q[0] }; + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), + fp_val); +#else + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), q); +#endif + if (ret) { + return ret; + } + } + + return 0; +} + +/* + * KVM SVE registers come in slices where ZREGs have a slice size of 2048 = bits + * and PREGS and the FFR have a slice size of 256 bits. However we simply = hard + * code the slice index to zero for now as it's unlikely we'll need more t= han + * one slice for quite some time. + */ +static int kvm_arch_put_sve(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint64_t tmp[ARM_MAX_VQ * 2]; + uint64_t *r; + int n, ret; + + for (n =3D 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { + r =3D sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * = 2); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); + if (ret) { + return ret; + } + } + + for (n =3D 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { + r =3D sve_bswap64(tmp, r =3D &env->vfp.pregs[n].p[0], + DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); + if (ret) { + return ret; + } + } + + r =3D sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], + DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); + if (ret) { + return ret; + } + + return 0; +} + +int kvm_arch_put_registers(CPUState *cs, int level) +{ + uint64_t val; + uint32_t fpr; + int i, ret; + unsigned int el; + + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + /* If we are in AArch32 mode then we need to copy the AArch32 regs to = the + * AArch64 registers before pushing them out to 64-bit KVM. + */ + if (!is_a64(env)) { + aarch64_sync_32_to_64(env); + } + + for (i =3D 0; i < 31; i++) { + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), + &env->xregs[i]); + if (ret) { + return ret; + } + } + + /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the + * QEMU side we keep the current SP in xregs[31] as well. + */ + aarch64_save_sp(env, 1); + + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); + if (ret) { + return ret; + } + + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); + if (ret) { + return ret; + } + + /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ + if (is_a64(env)) { + val =3D pstate_read(env); + } else { + val =3D cpsr_read(env); + } + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); + if (ret) { + return ret; + } + + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); + if (ret) { + return ret; + } + + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]= ); + if (ret) { + return ret; + } + + /* Saved Program State Registers + * + * Before we restore from the banked_spsr[] array we need to + * ensure that any modifications to env->spsr are correctly + * reflected in the banks. + */ + el =3D arm_current_el(env); + if (el > 0 && !is_a64(env)) { + i =3D bank_number(env->uncached_cpsr & CPSR_M); + env->banked_spsr[i] =3D env->spsr; + } + + /* KVM 0-4 map to QEMU banks 1-5 */ + for (i =3D 0; i < KVM_NR_SPSR; i++) { + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), + &env->banked_spsr[i + 1]); + if (ret) { + return ret; + } + } + + if (cpu_isar_feature(aa64_sve, cpu)) { + ret =3D kvm_arch_put_sve(cs); + } else { + ret =3D kvm_arch_put_fpsimd(cs); + } + if (ret) { + return ret; + } + + fpr =3D vfp_get_fpsr(env); + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); + if (ret) { + return ret; + } + + fpr =3D vfp_get_fpcr(env); + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); + if (ret) { + return ret; + } + + write_cpustate_to_list(cpu, true); + + if (!write_list_to_kvmstate(cpu, level)) { + return -EINVAL; + } + + /* + * Setting VCPU events should be triggered after syncing the registers + * to avoid overwriting potential changes made by KVM upon calling + * KVM_SET_VCPU_EVENTS ioctl + */ + ret =3D kvm_put_vcpu_events(cpu); + if (ret) { + return ret; + } + + kvm_arm_sync_mpstate_to_kvm(cpu); + + return ret; +} + +static int kvm_arch_get_fpsimd(CPUState *cs) +{ + CPUARMState *env =3D &ARM_CPU(cs)->env; + int i, ret; + + for (i =3D 0; i < 32; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), q); + if (ret) { + return ret; + } else { +#if HOST_BIG_ENDIAN + uint64_t t; + t =3D q[0], q[0] =3D q[1], q[1] =3D t; +#endif + } + } + + return 0; +} + +/* + * KVM SVE registers come in slices where ZREGs have a slice size of 2048 = bits + * and PREGS and the FFR have a slice size of 256 bits. However we simply = hard + * code the slice index to zero for now as it's unlikely we'll need more t= han + * one slice for quite some time. + */ +static int kvm_arch_get_sve(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint64_t *r; + int n, ret; + + for (n =3D 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { + r =3D &env->vfp.zregs[n].d[0]; + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); + if (ret) { + return ret; + } + sve_bswap64(r, r, cpu->sve_max_vq * 2); + } + + for (n =3D 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { + r =3D &env->vfp.pregs[n].p[0]; + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); + if (ret) { + return ret; + } + sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); + } + + r =3D &env->vfp.pregs[FFR_PRED_NUM].p[0]; + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); + if (ret) { + return ret; + } + sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); + + return 0; +} + +int kvm_arch_get_registers(CPUState *cs) +{ + uint64_t val; + unsigned int el; + uint32_t fpr; + int i, ret; + + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + for (i =3D 0; i < 31; i++) { + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), + &env->xregs[i]); + if (ret) { + return ret; + } + } + + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); + if (ret) { + return ret; + } + + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); + if (ret) { + return ret; + } + + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); + if (ret) { + return ret; + } + + env->aarch64 =3D ((val & PSTATE_nRW) =3D=3D 0); + if (is_a64(env)) { + pstate_write(env, val); + } else { + cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); + } + + /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the + * QEMU side we keep the current SP in xregs[31] as well. + */ + aarch64_restore_sp(env, 1); + + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); + if (ret) { + return ret; + } + + /* If we are in AArch32 mode then we need to sync the AArch32 regs wit= h the + * incoming AArch64 regs received from 64-bit KVM. + * We must perform this after all of the registers have been acquired = from + * the kernel. + */ + if (!is_a64(env)) { + aarch64_sync_64_to_32(env); + } + + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]= ); + if (ret) { + return ret; + } + + /* Fetch the SPSR registers + * + * KVM SPSRs 0-4 map to QEMU banks 1-5 + */ + for (i =3D 0; i < KVM_NR_SPSR; i++) { + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), + &env->banked_spsr[i + 1]); + if (ret) { + return ret; + } + } + + el =3D arm_current_el(env); + if (el > 0 && !is_a64(env)) { + i =3D bank_number(env->uncached_cpsr & CPSR_M); + env->spsr =3D env->banked_spsr[i]; + } + + if (cpu_isar_feature(aa64_sve, cpu)) { + ret =3D kvm_arch_get_sve(cs); + } else { + ret =3D kvm_arch_get_fpsimd(cs); + } + if (ret) { + return ret; + } + + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); + if (ret) { + return ret; + } + vfp_set_fpsr(env, fpr); + + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); + if (ret) { + return ret; + } + vfp_set_fpcr(env, fpr); + + ret =3D kvm_get_vcpu_events(cpu); + if (ret) { + return ret; + } + + if (!write_kvmstate_to_list(cpu)) { + return -EINVAL; + } + /* Note that it's OK to have registers which aren't in CPUState, + * so we can ignore a failure return here. + */ + write_list_to_cpustate(cpu); + + kvm_arm_sync_mpstate_to_qemu(cpu); + + /* TODO: other registers */ + return ret; +} + +void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) +{ + ram_addr_t ram_addr; + hwaddr paddr; + + assert(code =3D=3D BUS_MCEERR_AR || code =3D=3D BUS_MCEERR_AO); + + if (acpi_ghes_present() && addr) { + ram_addr =3D qemu_ram_addr_from_host(addr); + if (ram_addr !=3D RAM_ADDR_INVALID && + kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)= ) { + kvm_hwpoison_page_add(ram_addr); + /* + * If this is a BUS_MCEERR_AR, we know we have been called + * synchronously from the vCPU thread, so we can easily + * synchronize the state and inject an error. + * + * TODO: we currently don't tell the guest at all about + * BUS_MCEERR_AO. In that case we might either be being + * called synchronously from the vCPU thread, or a bit + * later from the main thread, so doing the injection of + * the error would be more complicated. + */ + if (code =3D=3D BUS_MCEERR_AR) { + kvm_cpu_synchronize_state(c); + if (!acpi_ghes_record_errors(ACPI_HEST_SRC_ID_SEA, paddr))= { + kvm_inject_arm_sea(c); + } else { + error_report("failed to record the error"); + abort(); + } + } + return; + } + if (code =3D=3D BUS_MCEERR_AO) { + error_report("Hardware memory error at addr %p for memory used= by " + "QEMU itself instead of guest system!", addr); + } + } + + if (code =3D=3D BUS_MCEERR_AR) { + error_report("Hardware memory error!"); + exit(1); + } +} + +/* C6.6.29 BRK instruction */ +static const uint32_t brk_insn =3D 0xd4200000; + +int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) +{ + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) = || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { + return -EINVAL; + } + return 0; +} + +int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) +{ + static uint32_t brk; + + if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || + brk !=3D brk_insn || + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1))= { + return -EINVAL; + } + return 0; +} diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c deleted file mode 100644 index 52c0a6d3af5..00000000000 --- a/target/arm/kvm64.c +++ /dev/null @@ -1,820 +0,0 @@ -/* - * ARM implementation of KVM hooks, 64 bit specific code - * - * Copyright Mian-M. Hamayun 2013, Virtual Open Systems - * Copyright Alex Benn=C3=A9e 2014, Linaro - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ - -#include "qemu/osdep.h" -#include -#include - -#include -#include - -#include "qapi/error.h" -#include "cpu.h" -#include "qemu/timer.h" -#include "qemu/error-report.h" -#include "qemu/host-utils.h" -#include "qemu/main-loop.h" -#include "exec/gdbstub.h" -#include "sysemu/runstate.h" -#include "sysemu/kvm.h" -#include "sysemu/kvm_int.h" -#include "kvm_arm.h" -#include "internals.h" -#include "cpu-features.h" -#include "hw/acpi/acpi.h" -#include "hw/acpi/ghes.h" - - -int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type) -{ - switch (type) { - case GDB_BREAKPOINT_HW: - return insert_hw_breakpoint(addr); - break; - case GDB_WATCHPOINT_READ: - case GDB_WATCHPOINT_WRITE: - case GDB_WATCHPOINT_ACCESS: - return insert_hw_watchpoint(addr, len, type); - default: - return -ENOSYS; - } -} - -int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type) -{ - switch (type) { - case GDB_BREAKPOINT_HW: - return delete_hw_breakpoint(addr); - case GDB_WATCHPOINT_READ: - case GDB_WATCHPOINT_WRITE: - case GDB_WATCHPOINT_ACCESS: - return delete_hw_watchpoint(addr, len, type); - default: - return -ENOSYS; - } -} - - -void kvm_arch_remove_all_hw_breakpoints(void) -{ - if (cur_hw_wps > 0) { - g_array_remove_range(hw_watchpoints, 0, cur_hw_wps); - } - if (cur_hw_bps > 0) { - g_array_remove_range(hw_breakpoints, 0, cur_hw_bps); - } -} - -static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *= attr, - const char *name) -{ - int err; - - err =3D kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); - if (err !=3D 0) { - error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); - return false; - } - - err =3D kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); - if (err !=3D 0) { - error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); - return false; - } - - return true; -} - -void kvm_arm_pmu_init(CPUState *cs) -{ - struct kvm_device_attr attr =3D { - .group =3D KVM_ARM_VCPU_PMU_V3_CTRL, - .attr =3D KVM_ARM_VCPU_PMU_V3_INIT, - }; - - if (!ARM_CPU(cs)->has_pmu) { - return; - } - if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { - error_report("failed to init PMU"); - abort(); - } -} - -void kvm_arm_pmu_set_irq(CPUState *cs, int irq) -{ - struct kvm_device_attr attr =3D { - .group =3D KVM_ARM_VCPU_PMU_V3_CTRL, - .addr =3D (intptr_t)&irq, - .attr =3D KVM_ARM_VCPU_PMU_V3_IRQ, - }; - - if (!ARM_CPU(cs)->has_pmu) { - return; - } - if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { - error_report("failed to set irq for PMU"); - abort(); - } -} - -void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) -{ - struct kvm_device_attr attr =3D { - .group =3D KVM_ARM_VCPU_PVTIME_CTRL, - .attr =3D KVM_ARM_VCPU_PVTIME_IPA, - .addr =3D (uint64_t)&ipa, - }; - - if (ARM_CPU(cs)->kvm_steal_time =3D=3D ON_OFF_AUTO_OFF) { - return; - } - if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) { - error_report("failed to init PVTIME IPA"); - abort(); - } -} - -void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp) -{ - bool has_steal_time =3D kvm_check_extension(kvm_state, KVM_CAP_STEAL_T= IME); - - if (cpu->kvm_steal_time =3D=3D ON_OFF_AUTO_AUTO) { - if (!has_steal_time || !arm_feature(&cpu->env, ARM_FEATURE_AARCH64= )) { - cpu->kvm_steal_time =3D ON_OFF_AUTO_OFF; - } else { - cpu->kvm_steal_time =3D ON_OFF_AUTO_ON; - } - } else if (cpu->kvm_steal_time =3D=3D ON_OFF_AUTO_ON) { - if (!has_steal_time) { - error_setg(errp, "'kvm-steal-time' cannot be enabled " - "on this host"); - return; - } else if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - /* - * DEN0057A chapter 2 says "This specification only covers - * systems in which the Execution state of the hypervisor - * as well as EL1 of virtual machines is AArch64.". And, - * to ensure that, the smc/hvc calls are only specified as - * smc64/hvc64. - */ - error_setg(errp, "'kvm-steal-time' cannot be enabled " - "for AArch32 guests"); - return; - } - } -} - -bool kvm_arm_aarch32_supported(void) -{ - return kvm_check_extension(kvm_state, KVM_CAP_ARM_EL1_32BIT); -} - -bool kvm_arm_sve_supported(void) -{ - return kvm_check_extension(kvm_state, KVM_CAP_ARM_SVE); -} - -QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN !=3D 1); - -uint32_t kvm_arm_sve_get_vls(CPUState *cs) -{ - /* Only call this function if kvm_arm_sve_supported() returns true. */ - static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; - static bool probed; - uint32_t vq =3D 0; - int i; - - /* - * KVM ensures all host CPUs support the same set of vector lengths. - * So we only need to create the scratch VCPUs once and then cache - * the results. - */ - if (!probed) { - struct kvm_vcpu_init init =3D { - .target =3D -1, - .features[0] =3D (1 << KVM_ARM_VCPU_SVE), - }; - struct kvm_one_reg reg =3D { - .id =3D KVM_REG_ARM64_SVE_VLS, - .addr =3D (uint64_t)&vls[0], - }; - int fdarray[3], ret; - - probed =3D true; - - if (!kvm_arm_create_scratch_host_vcpu(NULL, fdarray, &init)) { - error_report("failed to create scratch VCPU with SVE enabled"); - abort(); - } - ret =3D ioctl(fdarray[2], KVM_GET_ONE_REG, ®); - kvm_arm_destroy_scratch_host_vcpu(fdarray); - if (ret) { - error_report("failed to get KVM_REG_ARM64_SVE_VLS: %s", - strerror(errno)); - abort(); - } - - for (i =3D KVM_ARM64_SVE_VLS_WORDS - 1; i >=3D 0; --i) { - if (vls[i]) { - vq =3D 64 - clz64(vls[i]) + i * 64; - break; - } - } - if (vq > ARM_MAX_VQ) { - warn_report("KVM supports vector lengths larger than " - "QEMU can enable"); - vls[0] &=3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); - } - } - - return vls[0]; -} - -static int kvm_arm_sve_set_vls(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D { cpu->sve_vq.map }; - - assert(cpu->sve_max_vq <=3D KVM_ARM64_SVE_VQ_MAX); - - return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]); -} - -#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 - -int kvm_arch_init_vcpu(CPUState *cs) -{ - int ret; - uint64_t mpidr; - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint64_t psciver; - - if (cpu->kvm_target =3D=3D QEMU_KVM_ARM_TARGET_NONE || - !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) { - error_report("KVM is not supported for this guest CPU type"); - return -EINVAL; - } - - qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); - - /* Determine init features for this CPU */ - memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); - if (cs->start_powered_off) { - cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_POWER_OFF; - } - if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) { - cpu->psci_version =3D QEMU_PSCI_VERSION_0_2; - cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_PSCI_0_2; - } - if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_EL1_32BIT; - } - if (!kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PMU_V3)) { - cpu->has_pmu =3D false; - } - if (cpu->has_pmu) { - cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_PMU_V3; - } else { - env->features &=3D ~(1ULL << ARM_FEATURE_PMU); - } - if (cpu_isar_feature(aa64_sve, cpu)) { - assert(kvm_arm_sve_supported()); - cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_SVE; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - cpu->kvm_init_features[0] |=3D (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | - 1 << KVM_ARM_VCPU_PTRAUTH_GENERIC); - } - - /* Do KVM_ARM_VCPU_INIT ioctl */ - ret =3D kvm_arm_vcpu_init(cs); - if (ret) { - return ret; - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - ret =3D kvm_arm_sve_set_vls(cs); - if (ret) { - return ret; - } - ret =3D kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE); - if (ret) { - return ret; - } - } - - /* - * KVM reports the exact PSCI version it is implementing via a - * special sysreg. If it is present, use its contents to determine - * what to report to the guest in the dtb (it is the PSCI version, - * in the same 15-bits major 16-bits minor format that PSCI_VERSION - * returns). - */ - if (!kvm_get_one_reg(cs, KVM_REG_ARM_PSCI_VERSION, &psciver)) { - cpu->psci_version =3D psciver; - } - - /* - * When KVM is in use, PSCI is emulated in-kernel and not by qemu. - * Currently KVM has its own idea about MPIDR assignment, so we - * override our defaults with what we get from KVM. - */ - ret =3D kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); - if (ret) { - return ret; - } - cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; - - /* Check whether user space can specify guest syndrome value */ - kvm_arm_init_serror_injection(cs); - - return kvm_arm_init_cpreg_list(cpu); -} - -int kvm_arch_destroy_vcpu(CPUState *cs) -{ - return 0; -} - -/* Callers must hold the iothread mutex lock */ -static void kvm_inject_arm_sea(CPUState *c) -{ - ARMCPU *cpu =3D ARM_CPU(c); - CPUARMState *env =3D &cpu->env; - uint32_t esr; - bool same_el; - - c->exception_index =3D EXCP_DATA_ABORT; - env->exception.target_el =3D 1; - - /* - * Set the DFSC to synchronous external abort and set FnV to not valid, - * this will tell guest the FAR_ELx is UNKNOWN for this abort. - */ - same_el =3D arm_current_el(env) =3D=3D env->exception.target_el; - esr =3D syn_data_abort_no_iss(same_el, 1, 0, 0, 0, 0, 0x10); - - env->exception.syndrome =3D esr; - - arm_cpu_do_interrupt(c); -} - -#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \ - KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) - -#define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \ - KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) - -#define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \ - KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x)) - -static int kvm_arch_put_fpsimd(CPUState *cs) -{ - CPUARMState *env =3D &ARM_CPU(cs)->env; - int i, ret; - - for (i =3D 0; i < 32; i++) { - uint64_t *q =3D aa64_vfp_qreg(env, i); -#if HOST_BIG_ENDIAN - uint64_t fp_val[2] =3D { q[1], q[0] }; - ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), - fp_val); -#else - ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), q); -#endif - if (ret) { - return ret; - } - } - - return 0; -} - -/* - * KVM SVE registers come in slices where ZREGs have a slice size of 2048 = bits - * and PREGS and the FFR have a slice size of 256 bits. However we simply = hard - * code the slice index to zero for now as it's unlikely we'll need more t= han - * one slice for quite some time. - */ -static int kvm_arch_put_sve(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint64_t tmp[ARM_MAX_VQ * 2]; - uint64_t *r; - int n, ret; - - for (n =3D 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { - r =3D sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * = 2); - ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); - if (ret) { - return ret; - } - } - - for (n =3D 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { - r =3D sve_bswap64(tmp, r =3D &env->vfp.pregs[n].p[0], - DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); - if (ret) { - return ret; - } - } - - r =3D sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], - DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); - if (ret) { - return ret; - } - - return 0; -} - -int kvm_arch_put_registers(CPUState *cs, int level) -{ - uint64_t val; - uint32_t fpr; - int i, ret; - unsigned int el; - - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* If we are in AArch32 mode then we need to copy the AArch32 regs to = the - * AArch64 registers before pushing them out to 64-bit KVM. - */ - if (!is_a64(env)) { - aarch64_sync_32_to_64(env); - } - - for (i =3D 0; i < 31; i++) { - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), - &env->xregs[i]); - if (ret) { - return ret; - } - } - - /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the - * QEMU side we keep the current SP in xregs[31] as well. - */ - aarch64_save_sp(env, 1); - - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); - if (ret) { - return ret; - } - - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); - if (ret) { - return ret; - } - - /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */ - if (is_a64(env)) { - val =3D pstate_read(env); - } else { - val =3D cpsr_read(env); - } - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); - if (ret) { - return ret; - } - - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); - if (ret) { - return ret; - } - - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]= ); - if (ret) { - return ret; - } - - /* Saved Program State Registers - * - * Before we restore from the banked_spsr[] array we need to - * ensure that any modifications to env->spsr are correctly - * reflected in the banks. - */ - el =3D arm_current_el(env); - if (el > 0 && !is_a64(env)) { - i =3D bank_number(env->uncached_cpsr & CPSR_M); - env->banked_spsr[i] =3D env->spsr; - } - - /* KVM 0-4 map to QEMU banks 1-5 */ - for (i =3D 0; i < KVM_NR_SPSR; i++) { - ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), - &env->banked_spsr[i + 1]); - if (ret) { - return ret; - } - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - ret =3D kvm_arch_put_sve(cs); - } else { - ret =3D kvm_arch_put_fpsimd(cs); - } - if (ret) { - return ret; - } - - fpr =3D vfp_get_fpsr(env); - ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); - if (ret) { - return ret; - } - - fpr =3D vfp_get_fpcr(env); - ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); - if (ret) { - return ret; - } - - write_cpustate_to_list(cpu, true); - - if (!write_list_to_kvmstate(cpu, level)) { - return -EINVAL; - } - - /* - * Setting VCPU events should be triggered after syncing the registers - * to avoid overwriting potential changes made by KVM upon calling - * KVM_SET_VCPU_EVENTS ioctl - */ - ret =3D kvm_put_vcpu_events(cpu); - if (ret) { - return ret; - } - - kvm_arm_sync_mpstate_to_kvm(cpu); - - return ret; -} - -static int kvm_arch_get_fpsimd(CPUState *cs) -{ - CPUARMState *env =3D &ARM_CPU(cs)->env; - int i, ret; - - for (i =3D 0; i < 32; i++) { - uint64_t *q =3D aa64_vfp_qreg(env, i); - ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), q); - if (ret) { - return ret; - } else { -#if HOST_BIG_ENDIAN - uint64_t t; - t =3D q[0], q[0] =3D q[1], q[1] =3D t; -#endif - } - } - - return 0; -} - -/* - * KVM SVE registers come in slices where ZREGs have a slice size of 2048 = bits - * and PREGS and the FFR have a slice size of 256 bits. However we simply = hard - * code the slice index to zero for now as it's unlikely we'll need more t= han - * one slice for quite some time. - */ -static int kvm_arch_get_sve(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint64_t *r; - int n, ret; - - for (n =3D 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { - r =3D &env->vfp.zregs[n].d[0]; - ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); - if (ret) { - return ret; - } - sve_bswap64(r, r, cpu->sve_max_vq * 2); - } - - for (n =3D 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { - r =3D &env->vfp.pregs[n].p[0]; - ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); - if (ret) { - return ret; - } - sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - } - - r =3D &env->vfp.pregs[FFR_PRED_NUM].p[0]; - ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); - if (ret) { - return ret; - } - sve_bswap64(r, r, DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - - return 0; -} - -int kvm_arch_get_registers(CPUState *cs) -{ - uint64_t val; - unsigned int el; - uint32_t fpr; - int i, ret; - - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - for (i =3D 0; i < 31; i++) { - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), - &env->xregs[i]); - if (ret) { - return ret; - } - } - - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); - if (ret) { - return ret; - } - - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); - if (ret) { - return ret; - } - - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); - if (ret) { - return ret; - } - - env->aarch64 =3D ((val & PSTATE_nRW) =3D=3D 0); - if (is_a64(env)) { - pstate_write(env, val); - } else { - cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); - } - - /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the - * QEMU side we keep the current SP in xregs[31] as well. - */ - aarch64_restore_sp(env, 1); - - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); - if (ret) { - return ret; - } - - /* If we are in AArch32 mode then we need to sync the AArch32 regs wit= h the - * incoming AArch64 regs received from 64-bit KVM. - * We must perform this after all of the registers have been acquired = from - * the kernel. - */ - if (!is_a64(env)) { - aarch64_sync_64_to_32(env); - } - - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]= ); - if (ret) { - return ret; - } - - /* Fetch the SPSR registers - * - * KVM SPSRs 0-4 map to QEMU banks 1-5 - */ - for (i =3D 0; i < KVM_NR_SPSR; i++) { - ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), - &env->banked_spsr[i + 1]); - if (ret) { - return ret; - } - } - - el =3D arm_current_el(env); - if (el > 0 && !is_a64(env)) { - i =3D bank_number(env->uncached_cpsr & CPSR_M); - env->spsr =3D env->banked_spsr[i]; - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - ret =3D kvm_arch_get_sve(cs); - } else { - ret =3D kvm_arch_get_fpsimd(cs); - } - if (ret) { - return ret; - } - - ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); - if (ret) { - return ret; - } - vfp_set_fpsr(env, fpr); - - ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); - if (ret) { - return ret; - } - vfp_set_fpcr(env, fpr); - - ret =3D kvm_get_vcpu_events(cpu); - if (ret) { - return ret; - } - - if (!write_kvmstate_to_list(cpu)) { - return -EINVAL; - } - /* Note that it's OK to have registers which aren't in CPUState, - * so we can ignore a failure return here. - */ - write_list_to_cpustate(cpu); - - kvm_arm_sync_mpstate_to_qemu(cpu); - - /* TODO: other registers */ - return ret; -} - -void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) -{ - ram_addr_t ram_addr; - hwaddr paddr; - - assert(code =3D=3D BUS_MCEERR_AR || code =3D=3D BUS_MCEERR_AO); - - if (acpi_ghes_present() && addr) { - ram_addr =3D qemu_ram_addr_from_host(addr); - if (ram_addr !=3D RAM_ADDR_INVALID && - kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)= ) { - kvm_hwpoison_page_add(ram_addr); - /* - * If this is a BUS_MCEERR_AR, we know we have been called - * synchronously from the vCPU thread, so we can easily - * synchronize the state and inject an error. - * - * TODO: we currently don't tell the guest at all about - * BUS_MCEERR_AO. In that case we might either be being - * called synchronously from the vCPU thread, or a bit - * later from the main thread, so doing the injection of - * the error would be more complicated. - */ - if (code =3D=3D BUS_MCEERR_AR) { - kvm_cpu_synchronize_state(c); - if (!acpi_ghes_record_errors(ACPI_HEST_SRC_ID_SEA, paddr))= { - kvm_inject_arm_sea(c); - } else { - error_report("failed to record the error"); - abort(); - } - } - return; - } - if (code =3D=3D BUS_MCEERR_AO) { - error_report("Hardware memory error at addr %p for memory used= by " - "QEMU itself instead of guest system!", addr); - } - } - - if (code =3D=3D BUS_MCEERR_AR) { - error_report("Hardware memory error!"); - exit(1); - } -} - -/* C6.6.29 BRK instruction */ -static const uint32_t brk_insn =3D 0xd4200000; - -int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) -{ - if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 0) = || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4, 1)) { - return -EINVAL; - } - return 0; -} - -int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *= bp) -{ - static uint32_t brk; - - if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk, 4, 0) || - brk !=3D brk_insn || - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 4, 1))= { - return -EINVAL; - } - return 0; -} diff --git a/target/arm/meson.build b/target/arm/meson.build index 5d04a8e94f2..d6c3902e676 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -8,7 +8,7 @@ arm_ss.add(files( )) arm_ss.add(zlib) =20 -arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c', 'k= vm64.c'), if_false: files('kvm-stub.c')) +arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c'), i= f_false: files('kvm-stub.c')) arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013524; cv=none; d=zohomail.com; s=zohoarc; b=RSgkhIFf4D8NMe1uFV7dAZLIbUHXGgtdt12E7G8HCx7G9z1qLMuZgqfaPMFrMQfawi0/8FrirLB9JH2HQcWQ9PygF4JkU8TV2U6VtTgksLZP96Mte5Ao7C2k2AIucVXh6Z48KjRX/gL7ngxgC+7a9Thh+0Kd0d2ZmkJxyJJqvEM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013524; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=CIBsZGE1WWySZas0ZHGeHbBmxpd7vxCJhDZi0elDoIo=; b=gYP0DQjuSpX2nvDq2j0ngOLgngUvttZn/rXty3E0aBN+EF7Du4i3n89ZMBnwmg4VC7x0FZbajtmYW6ig3W5fdzAvfd7NmggFhOaozYx4aMr4gTtJsBDzsgoRNJitVXMMEiVvNs5elszcW4nw7/SN4ckSAphzVYVBYrzE458kzPY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013524628781.8648187697381; Tue, 19 Dec 2023 11:18:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWs-0001ta-US; Tue, 19 Dec 2023 14:13:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWq-0001pU-Ix for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:20 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWo-0001nF-BN for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:20 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-40c339d2b88so52874785e9.3 for ; Tue, 19 Dec 2023 11:13:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013526780100003 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 12 ------------ target/arm/kvm.c | 12 +++++++++++- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 1043123cc7a..b96ff35e34a 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -18,18 +18,6 @@ #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) =20 -/** - * kvm_arm_vcpu_init: - * @cs: CPUState - * - * Initialize (or reinitialize) the VCPU by invoking the - * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature - * bitmask specified in the CPUState. - * - * Returns: 0 if success else < 0 error code - */ -int kvm_arm_vcpu_init(CPUState *cs); - /** * kvm_arm_vcpu_finalize: * @cs: CPUState diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ab797409f13..d1edb9bd67c 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -60,7 +60,17 @@ typedef struct ARMHostCPUFeatures { =20 static ARMHostCPUFeatures arm_host_cpu_features; =20 -int kvm_arm_vcpu_init(CPUState *cs) +/** + * kvm_arm_vcpu_init: + * @cs: CPUState + * + * Initialize (or reinitialize) the VCPU by invoking the + * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature + * bitmask specified in the CPUState. + * + * Returns: 0 if success else < 0 error code + */ +static int kvm_arm_vcpu_init(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); struct kvm_vcpu_init init; --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013197; x=1703617997; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Lk12mN4qFsWUyce/FrUNcsWdUn084yu7ANskjsNphT8=; b=V0DnHg+Jy9iND0/rFUNj2Y4D1Py1ILfzZOCZwwwqMr7bM0Biw5M6693PNeO+Kjcx14 fZBLM7s/bH7TQwKNMnRQkNmLS8C275ZtiIjfJfo14qZvSd+e587T+X8SSWpKfrd11AD8 vpR7jKq6xuGxWutWluyMlfn/wMaUcIYupcEbt1tJ4jazBOgg3BPKzoETwONp1qK/nd/d rWcN9d3MBIcmaoimLhW0P9V+9HkdChCLX+GavI9G4cGNimX33MhApeTz10tSV5dDeTMd +2BqlOM0hrSPCoGVmKMrjNWq1q5iDuhwUQie14h5bZlzhU8UE/pu8f3giKO9wCVVXmBa /Vrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013197; x=1703617997; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Lk12mN4qFsWUyce/FrUNcsWdUn084yu7ANskjsNphT8=; b=uSOeMDbIs3bFtR7jU1GMfHwdMxfM7l1jqDjU87To95kORv50MxPkH2dx1WbvU1WWzX IOa8lm8uqVYzFaotENcoha2bFGoA2D7eIirNLIly0yWVwJwUmaO1DopFHwFfc/5NQe9i mIqU36oj7P+0eT7Dk19dvmzrQUN2v0Zcu5daMtplfSfp1WZm/HEqo1sE//rhel0C5nl7 fnykdvnYJMBmsse6fsiU/TMt515SQixXirAnoEQKiKJSs1b9z7scLunorqN/Ib9bwYYM RVsB84j2/tIg7UOeNI35ga9xJ09A5/3lmcxjZaRPmO1PG56zuqYrhyBqpfOhYEzphxzv C8nQ== X-Gm-Message-State: AOJu0YySbKFpVxo/215p+PBoAhBwFvXBJoMxLmhVkHeejikPxu8QazJh PM1HcazHiYm4xj0KEUNThPK/Vm6csAq1hOtnQ60= X-Google-Smtp-Source: AGHT+IFFUnLZ9e2q7kZDom7bEi4VdGXaEnYMWxap9mqr8peJzQQJJ29UdpT10uRNbvRO+z4gi+uTSQ== X-Received: by 2002:adf:f708:0:b0:336:780e:b2e3 with SMTP id r8-20020adff708000000b00336780eb2e3mr187503wrp.38.1703013197183; Tue, 19 Dec 2023 11:13:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/43] target/arm/kvm: Unexport kvm_arm_vcpu_finalize Date: Tue, 19 Dec 2023 19:12:40 +0000 Message-Id: <20231219191307.2895919-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013500812100003 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 14 -------------- target/arm/kvm.c | 14 +++++++++++++- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b96ff35e34a..9b630a1631e 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -18,20 +18,6 @@ #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) =20 -/** - * kvm_arm_vcpu_finalize: - * @cs: CPUState - * @feature: feature to finalize - * - * Finalizes the configuration of the specified VCPU feature by - * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring - * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of - * KVM's API documentation. - * - * Returns: 0 if success else < 0 error code - */ -int kvm_arm_vcpu_finalize(CPUState *cs, int feature); - /** * kvm_arm_register_device: * @mr: memory region for this device diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d1edb9bd67c..5bc96f469e1 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -81,7 +81,19 @@ static int kvm_arm_vcpu_init(CPUState *cs) return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); } =20 -int kvm_arm_vcpu_finalize(CPUState *cs, int feature) +/** + * kvm_arm_vcpu_finalize: + * @cs: CPUState + * @feature: feature to finalize + * + * Finalizes the configuration of the specified VCPU feature by + * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring + * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of + * KVM's API documentation. + * + * Returns: 0 if success else < 0 error code + */ +static int kvm_arm_vcpu_finalize(CPUState *cs, int feature) { return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature); } --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013415; cv=none; d=zohomail.com; s=zohoarc; b=n4irLCWwuXKaNrkYvCqhTvRA9HsUuVoyloG/0iAC9Xlu78ixHQFQiLHSf3bS9MLS3R0IBhIY1TrV5gvVE8Vl4LZhIyOba0qFllKzKWvCkvY35PiHDbayTn2dSUg5ODfmSScRfNU3dPTuA/6hnNxcqWn8P0j7WwCufPkp8iZ+6zw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013415; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Q+JqI01nncfSjIKYc0Twd9PO0mRP3lelRgIHx6yJ+Vs=; b=b2h3N9pPZMld3th/2O+7EUvnzpndFZEKOpot8GWMNUmef2aOBvRmckRARttqNCOthqNxel2SV649goO6x8OIXLe5X4xv4kZT7axUAXeobSYcYR/10WUCXAeN40CZn4st04HFLj5k0bpIdABfN2Gh2/BPrw4YLdSNyRCLcnOOZ9A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013415710992.6602814858988; Tue, 19 Dec 2023 11:16:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWy-0001xL-1i; Tue, 19 Dec 2023 14:13:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWs-0001st-0a for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:22 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWp-0001o5-5v for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:21 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40d2764c0f2so13007205e9.2 for ; Tue, 19 Dec 2023 11:13:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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=20 -/** - * kvm_arm_init_cpreg_list: - * @cpu: ARMCPU - * - * Initialize the ARMCPU cpreg list according to the kernel's - * definition of what CPU registers it knows about (and throw away - * the previous TCG-created cpreg list). - * - * Returns: 0 if success, else < 0 error code - */ -int kvm_arm_init_cpreg_list(ARMCPU *cpu); - /** * write_list_to_kvmstate: * @cpu: ARMCPU diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5bc96f469e1..d87d3e53e02 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -787,11 +787,17 @@ static bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t= regidx) } } =20 -/* Initialize the ARMCPU cpreg list according to the kernel's +/** + * kvm_arm_init_cpreg_list: + * @cpu: ARMCPU + * + * Initialize the ARMCPU cpreg list according to the kernel's * definition of what CPU registers it knows about (and throw away * the previous TCG-created cpreg list). + * + * Returns: 0 if success, else < 0 error code */ -int kvm_arm_init_cpreg_list(ARMCPU *cpu) +static int kvm_arm_init_cpreg_list(ARMCPU *cpu) { struct kvm_reg_list rl; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013198; x=1703617998; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=t6m3lX5Sl9TdeDH1xGZK0J7bT0+H3YIVfUxVvxyivcw=; b=GpdPtBWy+sV+ur2LStTT0t9l8WpS9VNTqaqFDtsGLwqPB+pKjOLH469DjPuP49gMfy zFtbUkLNPrtre3oKDxRGUUhEt+lAJUM2UB7PyUQUxzKP1fWmhCJ7qBbSrMOmPQ6hVhGo htvT8CqSIAZ9lM5CkM4a8kHzkxM+q+XV4YQWkpI+C5SHwwy05p4AByT2g9+c0bn+YqEl obaNpowto8bPKI9EA+GnKzIkUDfXONR8yjkRlbOd3Qem/lQAl3SLetIpnCqYTka4VE2c Q6nl9Hto+rkfjAVo1dht+fB+ulBh2FVg5AeuzAPUVDJWnwSyZwom1IIjulALlA2PjMMc NMfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013198; x=1703617998; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t6m3lX5Sl9TdeDH1xGZK0J7bT0+H3YIVfUxVvxyivcw=; b=DpbWWcKLB3g0hJfbfiYotgplc6IZCtUBUWUNj5eUT2CnlbPlFcxD4uXXMPWnHQnbGX 9J/GiafugKCt8yYKvGou7H9FNQ1RaDuMJzGEBa9HcG8d/LRD2XrqqLLVOmEw+jm6FEOI Gv3y7bzbcyz7BhIcQgdOpm9EYW9dR1IRMe79Nk/55/58+oya6B3bpmbNgV2W/KX1vOaQ 54XQOseFB5arNlfmLtCHqb3sGHfY1a2DWgMq2wbMCnH7s6HVH0j9ydvMAN53n3AzOsSN cTc4p0w7cHW6yVtvt86g+WdIF3SQ0WLGgbR2haY+CvRk7ppX1fPe0iPAyvcdNe1sMhNg m+Ug== X-Gm-Message-State: AOJu0Yzaf6yKMmlUeXgV5TQ9sllZfUz0TexV6wRIrBsPjKXR/W2xq9S6 EtLq/8xmnSWEMWrUfzQvQfls0SFE1lrFT9NtUTk= X-Google-Smtp-Source: AGHT+IFBRh7WoL3I3SAgEbDTNFnWZKN5Sej3GrK2Yln7K4tLvB+6VqnQ5dB4S73xhip/+36nDt9+jw== X-Received: by 2002:a05:600c:1c91:b0:40c:415f:cc48 with SMTP id k17-20020a05600c1c9100b0040c415fcc48mr804525wms.40.1703013198034; Tue, 19 Dec 2023 11:13:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/43] target/arm/kvm: Init cap_has_inject_serror_esr in kvm_arch_init Date: Tue, 19 Dec 2023 19:12:42 +0000 Message-Id: <20231219191307.2895919-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013417765100003 From: Richard Henderson There is no need to do this in kvm_arch_init_vcpu per vcpu. Inline kvm_arm_init_serror_injection rather than keep separate. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 8 -------- target/arm/kvm.c | 13 ++++--------- 2 files changed, 4 insertions(+), 17 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 350ba6cb967..1ec2476de7b 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -98,14 +98,6 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu); */ void kvm_arm_reset_vcpu(ARMCPU *cpu); =20 -/** - * kvm_arm_init_serror_injection: - * @cs: CPUState - * - * Check whether KVM can set guest SError syndrome. - */ -void kvm_arm_init_serror_injection(CPUState *cs); - /** * kvm_get_vcpu_events: * @cpu: ARMCPU diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d87d3e53e02..4a5553864a0 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -98,12 +98,6 @@ static int kvm_arm_vcpu_finalize(CPUState *cs, int featu= re) return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature); } =20 -void kvm_arm_init_serror_injection(CPUState *cs) -{ - cap_has_inject_serror_esr =3D kvm_check_extension(cs->kvm_state, - KVM_CAP_ARM_INJECT_SERROR_ESR); -} - bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, int *fdarray, struct kvm_vcpu_init *init) @@ -564,6 +558,10 @@ int kvm_arch_init(MachineState *ms, KVMState *s) =20 cap_has_mp_state =3D kvm_check_extension(s, KVM_CAP_MP_STATE); =20 + /* Check whether user space can specify guest syndrome value */ + cap_has_inject_serror_esr =3D + kvm_check_extension(s, KVM_CAP_ARM_INJECT_SERROR_ESR); + if (ms->smp.cpus > 256 && !kvm_check_extension(s, KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)) { error_report("Using more than 256 vcpus requires a host kernel " @@ -1946,9 +1944,6 @@ int kvm_arch_init_vcpu(CPUState *cs) } cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; =20 - /* Check whether user space can specify guest syndrome value */ - kvm_arm_init_serror_injection(cs); - return kvm_arm_init_cpreg_list(cpu); } =20 --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013731; cv=none; d=zohomail.com; s=zohoarc; b=YERuoil8AmBtdg5h05fn+tSu5AAEx6EiVXPyoyJ0O5paxQaTFKOjFvInDtlIRM170JKgaYQ65WJyajafp9CLFr4GyZasL7NS556Ju4WBCo0Ezka+qea/Vs0raEf2xoCNCiltmQ9I9F+9okGNy5vHmVTWzySIBnBnNnys1tdP9/4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013731; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Ak4CxhUk6h6TwjSSh7FmGz1AnjJa6mERKfsGXTlTv5I=; b=X2jAg6fTYx7aCgf3PEhzv5zgN8+dKnIucSVdyoSf6P3tkTV1it/SLKeU4hroc1bIClweSzbRme2gDOtOyM9csJTTD41BeYpogvZljIsiRwPz+jQnx3xfi3SqY2ksgLqETXAi7XeZRcPRwXHa1HaJDC//GpdVE7gpKO2N+P5qDYI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013731026992.3416154235849; Tue, 19 Dec 2023 11:22:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWv-0001ve-H8; Tue, 19 Dec 2023 14:13:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWs-0001sx-35 for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:22 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWp-0001oG-MS for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:21 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-40c580ba223so61798725e9.3 for ; Tue, 19 Dec 2023 11:13:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013731487100001 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 20 -------------------- target/arm/kvm.c | 20 ++++++++++++++++++-- 2 files changed, 18 insertions(+), 22 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 1ec2476de7b..b4339d49d11 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -98,26 +98,6 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu); */ void kvm_arm_reset_vcpu(ARMCPU *cpu); =20 -/** - * kvm_get_vcpu_events: - * @cpu: ARMCPU - * - * Get VCPU related state from kvm. - * - * Returns: 0 if success else < 0 error code - */ -int kvm_get_vcpu_events(ARMCPU *cpu); - -/** - * kvm_put_vcpu_events: - * @cpu: ARMCPU - * - * Put VCPU related state to kvm. - * - * Returns: 0 if success else < 0 error code - */ -int kvm_put_vcpu_events(ARMCPU *cpu); - #ifdef CONFIG_KVM /** * kvm_arm_create_scratch_host_vcpu: diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 4a5553864a0..b8923fe1776 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1090,7 +1090,15 @@ static void kvm_arm_put_virtual_time(CPUState *cs) cpu->kvm_vtime_dirty =3D false; } =20 -int kvm_put_vcpu_events(ARMCPU *cpu) +/** + * kvm_put_vcpu_events: + * @cpu: ARMCPU + * + * Put VCPU related state to kvm. + * + * Returns: 0 if success else < 0 error code + */ +static int kvm_put_vcpu_events(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; struct kvm_vcpu_events events; @@ -1119,7 +1127,15 @@ int kvm_put_vcpu_events(ARMCPU *cpu) return ret; } =20 -int kvm_get_vcpu_events(ARMCPU *cpu) +/** + * kvm_get_vcpu_events: + * @cpu: ARMCPU + * + * Get VCPU related state from kvm. + * + * Returns: 0 if success else < 0 error code + */ +static int kvm_get_vcpu_events(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; struct kvm_vcpu_events events; --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013512; cv=none; d=zohomail.com; s=zohoarc; b=UuGfGnRwgjGJEGmFFy6OGVYOpS6XchZBK7tW0HwLaRZ31z69n9twHly+A4uRXtXgjcMTWLbK0/0niuJrtcgTfaQMqAwvjx9BR45InKynQ5T3S3ospqgfyc2EwLxg2u9fEn82mjzbYxq+G/SSQYN1fS5yc3MyIuM3EAwxMRlnm3U= ARC-Message-Signature: i=1; a=rsa-sha256; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013199; x=1703617999; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UUOmNDqY3LeEXA9yEVWqeU26I9B7AoztRHl6/x/doeU=; b=nEpdFvTd0HFI0VPBorSuT3HwbC5G8QbuOm2HJg2clGQAacuxzdoPKuqJZCowTAVauW A645dD0HEHNG6SoaeR/f+mwQD/ZU75Z0KTqAiEoWSPiEa4MLqph+tU+X3iahQZLrGdaA CJv7+4V19bp2MhlGnoe6XobYK/k2AVrEsSYaB/nI6bwUvEgiRFIgHJLBj7K02icn7aNQ dOY7BNj0A+Gf90lgrtN+2SN8/ZT8YBSQxSMGCHt5KWDMj4tXB7eccIeJd4/4sl7iukbL 1xDxL+WISRHAX+Yz4v3YoyzXd1Vj8kxiJ8NbeRsn0JQTg2Fre9RcP7cDOhkg1syrWMfA yzBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013199; x=1703617999; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UUOmNDqY3LeEXA9yEVWqeU26I9B7AoztRHl6/x/doeU=; b=TXJ39MD2kpcm5L8BRiiJVNsX0dv3JZCOqgqAFCNcB/zaNw+elz39wGmgPIWt8Y9jrP 6i4kOPogAUxb+tBNsANg3oPqdSjWOLeSAMJiAmr6vnrctElptI5dNVSFAuA8zOEFDfLb eVMCTpfATKyfPtZfdSa7L1eu/tamRuElKGeNGKdiygRDnslDa4DFxjNx8mTWgEq0/yDk kN4CGT6uCo9/RQPmeMwAgY5lZojrMbOeNdbumh3HTl0iEn4auP0EPumUkBH5mIlnH/Vq d0dvEnvQJRpRu3c+TEWUO+2nfvmpFC7uDjeSEC4eyXhUqZL2RqxK5vO89T1dO3BRep3G FzTw== X-Gm-Message-State: AOJu0YwmkKvSnTFrcrYy1QfjCVkydaIqW+yOfiQYUy5yhhyv2jdHcN8W y7x4xYprDErNtWXXHgTHMBtvdmKvZsQw0r5Zz0Y= X-Google-Smtp-Source: AGHT+IE0FVQLV1HxgvzE+vEqOZf0wkl3wc18rI3tUsotGVgw2jUzqHpnDONm9kzR0EOVSZy5Ak+lAQ== X-Received: by 2002:adf:b301:0:b0:336:782b:ab8b with SMTP id j1-20020adfb301000000b00336782bab8bmr114238wrd.61.1703013198825; Tue, 19 Dec 2023 11:13:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/43] target/arm/kvm: Unexport and tidy kvm_arm_sync_mpstate_to_{kvm, qemu} Date: Tue, 19 Dec 2023 19:12:44 +0000 Message-Id: <20231219191307.2895919-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013512748100005 From: Richard Henderson Drop fprintfs and actually use the return values in the callers. This is OK to do since commit 7191f24c7fcf which added the error-check to the generic accel/kvm functions that eventually call into these ones. Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 [PMM: tweak commit message] Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 20 -------------------- target/arm/kvm.c | 23 ++++++----------------- 2 files changed, 6 insertions(+), 37 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b4339d49d11..8a44a6b762f 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -200,26 +200,6 @@ bool kvm_arm_sve_supported(void); */ int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa); =20 -/** - * kvm_arm_sync_mpstate_to_kvm: - * @cpu: ARMCPU - * - * If supported set the KVM MP_STATE based on QEMU's model. - * - * Returns 0 on success and -1 on failure. - */ -int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); - -/** - * kvm_arm_sync_mpstate_to_qemu: - * @cpu: ARMCPU - * - * If supported get the MP_STATE from KVM and store in QEMU's model. - * - * Returns 0 on success and aborts on failure. - */ -int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); - void kvm_arm_vm_state_change(void *opaque, bool running, RunState state); =20 int kvm_arm_vgic_probe(void); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b8923fe1776..db6d208cf03 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1004,41 +1004,32 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) /* * Update KVM's MP_STATE based on what QEMU thinks it is */ -int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu) +static int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu) { if (cap_has_mp_state) { struct kvm_mp_state mp_state =3D { .mp_state =3D (cpu->power_state =3D=3D PSCI_OFF) ? KVM_MP_STATE_STOPPED : KVM_MP_STATE_RUNNABLE }; - int ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); - if (ret) { - fprintf(stderr, "%s: failed to set MP_STATE %d/%s\n", - __func__, ret, strerror(-ret)); - return -1; - } + return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); } - return 0; } =20 /* * Sync the KVM MP_STATE into QEMU */ -int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) +static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) { if (cap_has_mp_state) { struct kvm_mp_state mp_state; int ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state); if (ret) { - fprintf(stderr, "%s: failed to get MP_STATE %d/%s\n", - __func__, ret, strerror(-ret)); - abort(); + return ret; } cpu->power_state =3D (mp_state.mp_state =3D=3D KVM_MP_STATE_STOPPE= D) ? PSCI_OFF : PSCI_ON; } - return 0; } =20 @@ -2182,9 +2173,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } =20 - kvm_arm_sync_mpstate_to_kvm(cpu); - - return ret; + return kvm_arm_sync_mpstate_to_kvm(cpu); } =20 static int kvm_arch_get_fpsimd(CPUState *cs) @@ -2365,7 +2354,7 @@ int kvm_arch_get_registers(CPUState *cs) */ write_list_to_cpustate(cpu); =20 - kvm_arm_sync_mpstate_to_qemu(cpu); + ret =3D kvm_arm_sync_mpstate_to_qemu(cpu); =20 /* TODO: other registers */ return ret; --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013649; cv=none; d=zohomail.com; s=zohoarc; b=gzgDVghQb6JWAZV4vcF/reBuPZ2aTxk24ayv6FOvNff4MTFM8Ynn9gg2E3U07xE5T4K9RfjRqQaQyTY0A7pZ4fSe4tfpcaKaJjMeBxIc9xVaz0CenRJ4VSugTRIJri3kBns3QxE0t7SkMIFnJPtF47fXQEiLe74oFscrZ4p65Js= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013649; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=hLgC4WHbF5gkYYbt5891jJq9lfv3cmnzjy976cgpXIk=; b=g37/VpdgrnoiCjBkBicjmDTp8qtdqdYAxb6393bw7mRIrcVZItBZOuCbGzcFD+u+YBoWtsFjuCQ5nQXzniKe3nzOUBGwkLsFgWNm52UnDlHuH5elcyfNq9u+1dE0EEsmPn1LBSaSGk9Z/sPgAfTsbf1bjU+YBqgmDwGmgEZ7wRY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013649486398.8601493322119; Tue, 19 Dec 2023 11:20:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfX4-00020o-SM; Tue, 19 Dec 2023 14:13:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWy-0001yE-GS for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:33 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWq-0001ob-Ul for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:28 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-40c2bb872e2so56131675e9.3 for ; Tue, 19 Dec 2023 11:13:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013651208100005 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 2 -- target/arm/kvm.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 8a44a6b762f..2037b2d7ea8 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -200,8 +200,6 @@ bool kvm_arm_sve_supported(void); */ int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool *fixed_ipa); =20 -void kvm_arm_vm_state_change(void *opaque, bool running, RunState state); - int kvm_arm_vgic_probe(void); =20 void kvm_arm_pmu_set_irq(CPUState *cs, int irq); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index db6d208cf03..41fffef5ef1 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1288,7 +1288,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm= _run *run) return MEMTXATTRS_UNSPECIFIED; } =20 -void kvm_arm_vm_state_change(void *opaque, bool running, RunState state) +static void kvm_arm_vm_state_change(void *opaque, bool running, RunState s= tate) { CPUState *cs =3D opaque; ARMCPU *cpu =3D ARM_CPU(cs); --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013199; x=1703617999; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=tjJ6DjjrNF4YS1GYLScIKt9PiPvca+RdqzW7lzNYdLU=; b=OIjeD+r8jmF9L7fbhsJ/zED7werStbAuMnbBmWyPe6Kz+DYfuqQuL1bMGxSl3C2hwf HhpnHiZO/myejB7hUvxsr4tiILsd+Cd21fjq6LMtILCqKwl3erp+i+psjney5M3bIYTE QLlezaoyz7RTFaVVBR6+4cr/fjKd0+8ax+eDIuYCkQqGimhZDrIL3rzmFBHhko7gRk1q EdAxSO381ZkJ5KGLs/tUEyr3YiPwgBHGPlosoW6wcqO42NM3vpniz3buGs2Jn7q8w9kH 4LcfEfatEBzSpf2ytQuBjDzmHe1eR8sKUTPTcn/QaJthn2Czh2XojrtyU3LbKUxwLRiX zWIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013199; x=1703617999; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tjJ6DjjrNF4YS1GYLScIKt9PiPvca+RdqzW7lzNYdLU=; b=Y0L4lrr994AELemAJqvttTMrpj46UcFClc58al9lnuBTi7PyAEtGHcZ2sOTNT5BlTC cfQ16obrp3sKTog8PiWvnNGxu5UOGEksi2W4rgiB3Fq/ODZRHtXU0t7pxk5r4DzCCmpL GOpygImZxR0b9tiJEi7nvTjEchwp357EGQLdElgw31hxIUA7hkxL4lsqaxDuo++1vH/D M9uvjDFLRPhdIg5/k2o95EpEu8hL7wm23cpnf0+qu+XKqcA8ZefwOSS9c+e4wUtbhEWu oaNVTxbecxeDHW4ydVIz66OGs8zY6Tdgak71PxRy2mkK2hB/mmYG8rWpzZCmveAEfQ1r A5Og== X-Gm-Message-State: AOJu0YycNsLsdcv02SE+lIX9v6c7rZaKUZ1EFXse3VaWyP2dX+VS8dZ7 6cZY0EJn0JkgJyBx+yNFUe9YosDqE7UjkRXyfMs= X-Google-Smtp-Source: AGHT+IHMOLTAVif2uLukeNHAaXtLrW7Z8wG1OP/Ky4tO20K3BerZ3YZw48sqSzIo0ds3FIbncwLIBg== X-Received: by 2002:a5d:5551:0:b0:336:7142:8c30 with SMTP id g17-20020a5d5551000000b0033671428c30mr941263wrw.123.1703013199593; Tue, 19 Dec 2023 11:13:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/43] hw/intc/arm_gicv3: Include missing 'qemu/error-report.h' header Date: Tue, 19 Dec 2023 19:12:46 +0000 Message-Id: <20231219191307.2895919-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SPACE_RATIO=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013665226100015 From: Philippe Mathieu-Daud=C3=A9 kvm_arm_its_reset_hold() calls warn_report(), itself declared in "qemu/error-report.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-2-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_its_kvm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index f7df602cfff..3befc960db2 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/error-report.h" #include "hw/intc/arm_gicv3_its_common.h" #include "hw/qdev-properties.h" #include "sysemu/runstate.h" --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013280; cv=none; d=zohomail.com; s=zohoarc; b=WJzigUyl25CPLLhKilAFRiGXAdjA9kLCe9ZnePeye+TicixpOJnpk5qM8SMaaF7p0yzTfTC+EY8kSYS173nmTfj2bGoM7zAnPWhEA40U8lCnExtTlQCeR+NPmjkRkEVgVN6dxRI4TerR44n70C1nljWAs6YDr0JFyMnh9eVmgBU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013280; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=RDIBMPpY2c044rUIduHvSX5HNjBWclM55GKfwRyQOZQ=; b=GfQ31QDnxAVZrXQa1X/jyJL12LbFhgucH4QS414uLem0va/zItykOEqV+zzaAej3yETf6GrR672dGPz8yS9Piyj3V8ORGg6FMMZuuP+XLfaaxBnwXWIt5BzQhJ5EX99XTcr6tLuXx5+Scuy5LeKq7l4hmjD7bxsUwLnJW4yEgWc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013280721270.2802747387552; Tue, 19 Dec 2023 11:14:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWw-0001vy-Hx; Tue, 19 Dec 2023 14:13:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWt-0001tg-9x for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:23 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWr-0001om-Co for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:23 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-336746a545fso79f8f.0 for ; Tue, 19 Dec 2023 11:13:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013200; x=1703618000; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=RDIBMPpY2c044rUIduHvSX5HNjBWclM55GKfwRyQOZQ=; b=XIR+c8UqhbqOFn5NKN50+nstIfg5qY2FTd4bxZid6v2MxI1IB05+nF+CoN4KLHfMep yhhCOQQWbelcvXdK/0TpL0wtmHfUR2Hj2JQHupopEmvZKvdBFrCJqH4osF9jcTSTMVmF NeAfBCtQu4qWgssxVt9L3UDe9RDnQBLtDzF/U8paC/2eW7W8+P+Dvj997xv5jMvJSFsf 5R871pkjXmDMCh6Y8hWV7V7qnT0nF7XJWMTqoX5G2jgUudBENPHt6KTmvFBJQiOMXPEL KMM5uliipjQD87hi0lk242FDx/f6NG5PY0729kVZ4KPbsctlNOdkLVhUbPt07hPQzco4 uJ/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013200; x=1703618000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RDIBMPpY2c044rUIduHvSX5HNjBWclM55GKfwRyQOZQ=; b=Y3R+ok02r3QfpczhYdH0E0a0HuXJGHNyDMPbnyj253bxgATiuKi1pomOyEOmudgnzS O1qMS4P1rFHySkUjYLaRXOneFYFszGVHqXYRkz412qyNvTB0+EAE+5v6XlJ7yv9dEWYQ D2fyjQWn+E1lTy0WQpvmisrPkLSF5Ip9tfh87AV5kgLKEnMrsrwkB4uQdjf2r+TzOp+2 qy8K04IQUyLsnmzQmJPB1XSKiV3S9OqivluobQ8Zu8f//5CUBcFFSA0AHaulvsTLBfos XxwsFWCOVvx41XASRj9DCoaAVYLGJZ1XiMHmoggnrOUbEkK23Qb+By3OBKvgEdARIJMM U4ZA== X-Gm-Message-State: AOJu0YzzmHmFoB+ji5/N1CfwkyHG7lN0203dQZ0ADsd+fJ4TZ75b08Ex HDo+MOgeXRvQuYcNIWW4S0Kr+JuS1xAACYGNVGQ= X-Google-Smtp-Source: AGHT+IG0+Hd+7RaxCfbrcKoVJDoFJJJ//x7SeyrJ0+ZDuaFqz9hWv9uznHTxmTR6RFmYLmYJCZkluA== X-Received: by 2002:adf:ee0c:0:b0:336:7686:d5e2 with SMTP id y12-20020adfee0c000000b003367686d5e2mr479349wrn.53.1703013199985; Tue, 19 Dec 2023 11:13:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/43] target/arm/kvm: Remove unused includes Date: Tue, 19 Dec 2023 19:12:47 +0000 Message-Id: <20231219191307.2895919-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013281291100001 From: Philippe Mathieu-Daud=C3=A9 Both MemoryRegion and Error types are forward declared in "qemu/typedefs.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-3-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 2037b2d7ea8..50967f4ae9c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -12,8 +12,6 @@ #define QEMU_KVM_ARM_H =20 #include "sysemu/kvm.h" -#include "exec/memory.h" -#include "qemu/error-report.h" =20 #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013420; cv=none; d=zohomail.com; s=zohoarc; b=C8XIfDd0RuiWnMAHEgSAXzgqg6WxEW0G8WjOsFwboMAmfGXxaqgdElkmHHoHhwIQrdftRMxMfwYCfxMX+rXAehLqL9Znxj9fl2E7t14E9jNUoh4WkLl25R5R77B57Y1z8gHhkq39IczJlP8SaUSo3PXeJ+PEDRn7fc7BKYbL3pk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013420; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=f99Ujt99QMeF21Uqr8srLUFwBNPf96V7ucD7nm9URUA=; b=LlEo1mJ4ZeD3vbsbioSAv9LPA3h8mUwghClRtyyTb/xkb+L2qgJ/Exw8ef53yfTEe1LDjgigv4vrHAXpPBQvmckckUkzFMiOzraXVeZXVuCwAJpSvI0ZX92ZazX6AP6xdT1k8unuHwr1rGzxl9AsD4zYnJ9oerie++1SsBbSdwc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013420962639.8420572363422; Tue, 19 Dec 2023 11:17:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfWx-0001x1-L8; Tue, 19 Dec 2023 14:13:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWu-0001v4-Qm for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:24 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWr-0001p6-Vz for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:23 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-40c38e292c8so12475e9.0 for ; Tue, 19 Dec 2023 11:13:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013200; x=1703618000; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=f99Ujt99QMeF21Uqr8srLUFwBNPf96V7ucD7nm9URUA=; b=ctw0gsEQz/OI5OUdhqO1VphTQJJMqSdtXqksgTZgr+hGT+APbZMxjrJ9mAHc1BpHfu q3mACZiO0Va5bpmejspEobAL2pwwmSQNCgBGQTsq6RIEUFS9CuW+8qv6wCalAu3yJNGu eHxliVE8qK0YX520emnjKpjDbsKPv9jX3kxQj4wkREPX2W2A5FFubdt0VMRPtwqk5FF9 bCIB2pcmnwxpfCGR3akZgnkHyPnE3Ct9DqX6IiSbMmUqal76Dup6u8v4uKXVeN4AzRk2 yv/IS8g51CIY3yDIxB9zVETtmT2fbGDbU3yysT/qmljlEir9SURUw8NId5rIPCP33+LJ ofeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013200; x=1703618000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f99Ujt99QMeF21Uqr8srLUFwBNPf96V7ucD7nm9URUA=; b=YfZI4WD4kecYRoiiNICzvr/s1y/VzUzxlIa48dasdj3st1JnjCoRYGjVeJ5w5UaANV hn70UuvVdQl6B109PKdvACccgUoWO1n/Yg1V5u8hqvDw2/IkdrrwqTIF/9cnUo0LDJ5N CKQmXL36dYtuJkCuLSNFJUMCg5hIwffyZZUPGQohvTHEXC9O1L/Zu10bfaQrFmv2AVZR Qc/23OTKWxokexpmVnkdJ3AwsVRh6oWFuelrmymvSaT8IzTEL6TOdhK22X4zkSTaVi7a 7umwIyr//CBwAPNTAbDeholoTYhwi0CmriLwnxqo+1ErnQMt1310egn6psXaHXW3OSuW Vg8w== X-Gm-Message-State: AOJu0YwIyut0N5lv23/r7ctP1tKvTL0fbqsQAym2OAlj9OZP5YVWukhw AI2xY0XuhClxD0e6y230ixG4rmJS0XRnDLJXWPw= X-Google-Smtp-Source: AGHT+IGYaWU+Qj249BaoGoqAB+pMVY9hc/TRy1G5PWWcpTNkl4OwyxkDfY4vtkQyXdYyE+NBJahNjw== X-Received: by 2002:a05:600c:43c4:b0:40c:5822:133a with SMTP id f4-20020a05600c43c400b0040c5822133amr848826wmn.69.1703013200396; Tue, 19 Dec 2023 11:13:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/43] target/arm/kvm: Have kvm_arm_add_vcpu_properties take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:48 +0000 Message-Id: <20231219191307.2895919-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013421829100013 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-4-philmd@linaro.org [PMM: fix parameter name in doc comment too] Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 6 +++--- target/arm/cpu.c | 2 +- target/arm/kvm.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 50967f4ae9c..3abbef02601 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -148,12 +148,12 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 /** * kvm_arm_add_vcpu_properties: - * @obj: The CPU object to add the properties to + * @cpu: The CPU object to add the properties to * * Add all KVM specific CPU properties to the CPU object. These * are the CPU properties with "kvm-" prefixed names. */ -void kvm_arm_add_vcpu_properties(Object *obj); +void kvm_arm_add_vcpu_properties(ARMCPU *cpu); =20 /** * kvm_arm_steal_time_finalize: @@ -243,7 +243,7 @@ static inline void kvm_arm_set_cpu_features_from_host(A= RMCPU *cpu) g_assert_not_reached(); } =20 -static inline void kvm_arm_add_vcpu_properties(Object *obj) +static inline void kvm_arm_add_vcpu_properties(ARMCPU *cpu) { g_assert_not_reached(); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index efb22a87f9e..650e09b29c5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1686,7 +1686,7 @@ void arm_cpu_post_init(Object *obj) } =20 if (kvm_enabled()) { - kvm_arm_add_vcpu_properties(obj); + kvm_arm_add_vcpu_properties(cpu); } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 41fffef5ef1..e5a2596890b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -497,10 +497,10 @@ static void kvm_steal_time_set(Object *obj, bool valu= e, Error **errp) } =20 /* KVM VCPU properties should be prefixed with "kvm-". */ -void kvm_arm_add_vcpu_properties(Object *obj) +void kvm_arm_add_vcpu_properties(ARMCPU *cpu) { - ARMCPU *cpu =3D ARM_CPU(obj); CPUARMState *env =3D &cpu->env; + Object *obj =3D OBJECT(cpu); =20 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { cpu->kvm_adjvtime =3D true; --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013332; cv=none; d=zohomail.com; s=zohoarc; b=FuYugRXN1WyrKznb/uqHTvYe/VuP5h9hUVRtO3/5swwz3nAHB4yQnkW7IYfENmJyZBIsuQkoxlzJmWHrEI5eEjsRq5EVQNAtjnLCtYS5qQTcxctJX7Dt+wIgt2wGcbUFjwqb4q8pqhP7lpYVVMywjUdFz/0gTlPgXYPrgx6HZao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013332; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=d/ifw9z6r6bmX0fdH0IVqZ7YqgrTTUGMwKeFbCj1mN8=; b=mwmY/IKRDEpI2JwPJUbqFCls/kr2X12Y4emtJAlHHSac0IkG8noxVos8b6cAyJjrLjdG9idQb7vO7aNaG7Wt6AWjzh4SPaEWHiNlpEFFDxFtaMmZSBqIy3BiHFdz4YCuhMqkUJcpdsSCp7YgFjjqd+dIGKnCxHiQ59omyHvx4FI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013332289468.57405180240835; Tue, 19 Dec 2023 11:15:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfXN-0002L6-Jg; Tue, 19 Dec 2023 14:13:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfX8-00022z-VT for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:39 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWt-0001qH-6N for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:38 -0500 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-33666fb9318so2874765f8f.2 for ; Tue, 19 Dec 2023 11:13:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013201; x=1703618001; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=d/ifw9z6r6bmX0fdH0IVqZ7YqgrTTUGMwKeFbCj1mN8=; b=lUHh8iXgSg0FZIk6wVxdPfVFJF9sUTGd0Jb0xjUNZFmXNxWkor2jSDZpew8fYTg6kO 9M/xEgU42sagv4jQQJGIcQyd2c0ji8ntnbldFi5XwrtDBOOeEvxbq2Vhwx5uGFmx+j0x WK4J1u3OLeBChR4lXVi51ttDVtNLzFbEZ4R1HtFskeZOexBCWfDqlbwhhNr6EuVX8VLL Q2wamH/ie00wS5X3K6PT2w7XoD0MBm3dEemEJXk0rMrVMPjTJ7lwXKsxhYOj+WFXNOhN +0PRdym6BpU8PfWu+O2vcJDl8n+er67e21EfRffLYPFrxozIYXuFjRS5P9t4kjsqPJD1 j5CQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013201; x=1703618001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d/ifw9z6r6bmX0fdH0IVqZ7YqgrTTUGMwKeFbCj1mN8=; b=Z64aF2pjbyhiKSa7tqHt0BSl/vzDvk8/TowhKWv8SSsWxYHur0uDC1bkzAmvksE5DA Yo42WFC7mKhWXtPyCqHF8SjrUbTRgAQUnzL1QgEtE1Yjw1IBT11uCpFAzSzvrD1XRL7x SdhL7oWJEkdyEYg0RL03HuSbLCh6V7bW/KEOy06U7WbnghcFqASj5RleKv4EPABNE169 /REzrMHZ9pMkwU3IU8TI42ZB8Q695G6MoxV7P/NYUavRR0pDWiWc39LyWInNpgeV6lC8 MJ9bYT4AA98oSPUinfFaY19XHRgfoMAqHJGgA0vlrqBUNc6cJPSYGD2EAvOSccJol1zf TJwg== X-Gm-Message-State: AOJu0Yx4OhauN5cQYnut8SPv3h8jXlA2+SJKxKQVQz724ka3U74LSxYB E7zNXsKAWkUfDYQ6ikCg1IpN0avWw2/iZijYGe8= X-Google-Smtp-Source: AGHT+IFgIrz/QiNB9uiDfy8HkVl4kbEuMVbU6wKiM4MBmw30L4D/z893FaazOueV+lKQHMxSuJMAlQ== X-Received: by 2002:a05:6000:1d84:b0:336:1fcf:5aec with SMTP id bk4-20020a0560001d8400b003361fcf5aecmr10149644wrb.55.1703013200759; Tue, 19 Dec 2023 11:13:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/43] target/arm/kvm: Have kvm_arm_sve_set_vls take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:49 +0000 Message-Id: <20231219191307.2895919-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013333461100006 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-5-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e5a2596890b..e9c6e2e17c1 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1855,14 +1855,13 @@ uint32_t kvm_arm_sve_get_vls(CPUState *cs) return vls[0]; } =20 -static int kvm_arm_sve_set_vls(CPUState *cs) +static int kvm_arm_sve_set_vls(ARMCPU *cpu) { - ARMCPU *cpu =3D ARM_CPU(cs); uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D { cpu->sve_vq.map }; =20 assert(cpu->sve_max_vq <=3D KVM_ARM64_SVE_VQ_MAX); =20 - return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]); + return kvm_set_one_reg(CPU(cpu), KVM_REG_ARM64_SVE_VLS, &vls[0]); } =20 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 @@ -1919,7 +1918,7 @@ int kvm_arch_init_vcpu(CPUState *cs) } =20 if (cpu_isar_feature(aa64_sve, cpu)) { - ret =3D kvm_arm_sve_set_vls(cs); + ret =3D kvm_arm_sve_set_vls(cpu); if (ret) { return ret; } --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013457; cv=none; d=zohomail.com; s=zohoarc; b=UyiGFTkj/K02RN1QiY0ExGFZA9IUFU6cRoHKzZTQBIPtWQm1AEln1FH8rET8790nKCuew4LToAmJiQqDZy61z1uPmT0eTNUmO/IzcXTs6AyVPDhRUxh2UUH59Lw3ZlitVkpZDCvoXZUbCtF1mfwpl9+KHNDJQf7joJKQXLZXKic= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013457; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=h3V71XAx3UDA0zBtoUkIA2yNtSzC2BWFrBTkEOk1jT4=; b=QEVG2j1gBiHoXtylYx3nxHe47dRyBg+vLCaOZoHKv4X68hqUsyT5xKhHY4NZFL3mDetrwXVUo0gvULoR2m+0guSBQIvXy+3DINVQJZGSKDAxJKwTyXA9oD7W6E/bPNxGSguYqY6suVw/nTAUEO299EfcfOadzMNXlhoT3szRwPg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013457731860.1792066020604; Tue, 19 Dec 2023 11:17:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfX8-00022y-O4; Tue, 19 Dec 2023 14:13:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWv-0001vf-Jc for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:25 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWs-0001qh-UG for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:25 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-33668163949so2809088f8f.2 for ; Tue, 19 Dec 2023 11:13:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013201; x=1703618001; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=h3V71XAx3UDA0zBtoUkIA2yNtSzC2BWFrBTkEOk1jT4=; b=rHYclgNF2FmdSJqPqjaIx07zD4O4ZilkQt7JXensIj6uWK65XUsWO0Uks8F1QS8+tM qHZpxqRtM9Asp2OfrtTJEAAXPeBwD2cT5tD0ip0eOkwKW0IZAOi61yoT0Xg7oxx46qZJ dLPdwfYgiJeUNbZ/gAbD6I7YBbIF2VJXE65zDU5a9zEobnVLlu6RjFTdYZfT00ZHphvr /97PEVaLD49/aKP+NMxVEdkihUwEYU2bWxMxBFmhqtGqDKd3N0tgAhub9JL6twMgwtyh Uxik1paI07dTGkbnAVrrnfi3krgSZ3mvGmIbr1+7Iv7LksIyTaNyHkJ/tuSFxbRd/zTD UYdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013201; x=1703618001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h3V71XAx3UDA0zBtoUkIA2yNtSzC2BWFrBTkEOk1jT4=; b=oZM2JABsmT4JDxlfST8S7jFD64qPR3Y3ymhNQsC0zloetkmq7XNrutg3Q8+ebupxic SKBng26yK6ilwgEZIF0WwlDEOxucvsQv+tXdImEuCF86lun1CB3HujiovwBWBPDBeC1R AWbr7ec1LVDtzKb81tf+XznPCTPKFJwaaOS5Jy9jDt6Iq1dUZn3w9K9yvXGzw4LXLyM+ qyoWfyddcO1117UwMKoxlsnPARaZm/UJcMgGMlF996fyhsdsAQamBhHdZJKD9RwZNQZW u8qQ6pGX4XVtJM/6SfEEIZFqLkbbZt5b6nH41pop1S8n2OexP1+p70JXaJdFQFLCP59c bvmg== X-Gm-Message-State: AOJu0YzKuXiBjARyX54bH9wQFte06wLusmr9RT+yIUWbgYeWm4XNTZCE +vEud7iqEzN/TXFOojF7oxzOvXxI6Heb7ttzIhQ= X-Google-Smtp-Source: AGHT+IE7IQCmULk4WrzZ0HxkPqv0tYHYAbWSaueyrg+Fcl/Rcr3RKFJlAk1SpNWI96zkjlWPSaOY0A== X-Received: by 2002:a05:6000:1f0f:b0:336:6dad:2698 with SMTP id bv15-20020a0560001f0f00b003366dad2698mr1003805wrb.82.1703013201313; Tue, 19 Dec 2023 11:13:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/43] target/arm/kvm: Have kvm_arm_sve_get_vls take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:50 +0000 Message-Id: <20231219191307.2895919-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013459927100008 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-6-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 6 +++--- target/arm/cpu64.c | 2 +- target/arm/kvm.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 3abbef02601..d6d999b1ff8 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -129,13 +129,13 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); =20 /** * kvm_arm_sve_get_vls: - * @cs: CPUState + * @cpu: ARMCPU * * Get all the SVE vector lengths supported by the KVM host, setting * the bits corresponding to their length in quadwords minus one * (vq - 1) up to ARM_MAX_VQ. Return the resulting map. */ -uint32_t kvm_arm_sve_get_vls(CPUState *cs); +uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu); =20 /** * kvm_arm_set_cpu_features_from_host: @@ -278,7 +278,7 @@ static inline void kvm_arm_steal_time_finalize(ARMCPU *= cpu, Error **errp) g_assert_not_reached(); } =20 -static inline uint32_t kvm_arm_sve_get_vls(CPUState *cs) +static inline uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) { g_assert_not_reached(); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1e9c6c85aec..8e30a7993ea 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -66,7 +66,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) */ if (kvm_enabled()) { if (kvm_arm_sve_supported()) { - cpu->sve_vq.supported =3D kvm_arm_sve_get_vls(CPU(cpu)); + cpu->sve_vq.supported =3D kvm_arm_sve_get_vls(cpu); vq_supported =3D cpu->sve_vq.supported; } else { assert(!cpu_isar_feature(aa64_sve, cpu)); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e9c6e2e17c1..132a1b47d04 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1801,7 +1801,7 @@ bool kvm_arm_sve_supported(void) =20 QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN !=3D 1); =20 -uint32_t kvm_arm_sve_get_vls(CPUState *cs) +uint32_t kvm_arm_sve_get_vls(ARMCPU *cpu) { /* Only call this function if kvm_arm_sve_supported() returns true. */ static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013300; cv=none; d=zohomail.com; s=zohoarc; b=GUbjgr7HeBwGMYeBuT2zCsGy2KMKF5OJ4Qgd/627FFPFCxFd4Q2YL0xi4d2PUyisF3QBpcw/+yby5sJK/SStKyvSn04PwNbRLlzSwrqT9Of9i+X+YjAeN8CD1SF9OfvDj4DhtSnAV2vZUp/LAnQQEVJht7wh3STQ/MKeof7MDeE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013300; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=3ZO8ztgowbV18Gzw4fuVGRHf6IPf5T0BjvZrFbeykXA=; b=AXO1IrM1WSlPrQnYM0FrxE3N3pfsf5NGt34j/1Xr60oM4H0pOIC50fGis2Agf9Awrz6wyeT0S8DrOvOyi4EO9Cx5XL1CuPwiIV92kDBRIjql6/9gDRz/qBwIAYsI8Ai9OZaGWK50c9D5XD6sSpDsXK93XEtgvaeIiOfK9v6/RUc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013300183734.4968176921766; Tue, 19 Dec 2023 11:15:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfX3-0001yL-Sl; Tue, 19 Dec 2023 14:13:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWv-0001vg-LV for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:25 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWt-0001qy-2D for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:25 -0500 Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-33678156e27so178473f8f.1 for ; Tue, 19 Dec 2023 11:13:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013201; x=1703618001; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3ZO8ztgowbV18Gzw4fuVGRHf6IPf5T0BjvZrFbeykXA=; b=vXgcGQWmfrBruQ/kvTrDkWEGI3P3ke1OMkWnJ9ftiOQsHW0VHL1j51+TKuOe5Jh97w kliqETcH9P48F0A/QLXiWNQa6E6kIN/1FeVjI38YLj0DXy2zBpiP1rOra+0Rl7kP8wEI 3pnr7PAhQjda/ktJFkDsfwZh++zgY2lQn6QYUUsmonvRPFiyVDe0b3sQfxzsxdABvo2U 9DmhnND767aHk/YbX/s01mVfXNNYNZaNjHts2Fzj0WD5jtqdT6Kg3NcHYSipp7OrCqw9 Kn3/3vprg/rKnCzCATuS72rdAVun60Ze4FbglpSQiaHHlK2AFGa72y0syBe8FI2kG4Un KBOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013201; x=1703618001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3ZO8ztgowbV18Gzw4fuVGRHf6IPf5T0BjvZrFbeykXA=; b=YZNnAHD1O4sDBzoUN0kemSsVCQaUUr3TCoDctmtNI9/qjEiC9Lv0ybCzWcnGGvd6TE 4/zTs828fuL8O7fL2y92OUHLWmzkM6TSal16darEd3kK60hV4rcshsQGroA+WFy2FIzo OYWJyPL95Z7+I0fb+WHEh03MU8RraFZ9hMpQkuC5G08e5LkjtJmajrabmbAeSKx45NMs EQiruJT8CbrOITSw5Jt2NMGsaE5XBswHGezDdIRWllRS6xix/5RxHkXSaa6jqB0bwMb0 G2oMQfVsy2BLE4do3Ry/HYk2wTdWwCQ9wquEfxMdpIYc+k56SOhQLe3p71b7Bp6h5Z31 8F+Q== X-Gm-Message-State: AOJu0YyjuQ9Lspev2hE+IlhsDdKLo379VwHejm1kF+sgxxI5sIyLOGaZ C78tel1YCTPqpxImwqs2yKWUQ4QFgfGuYsIl/J8= X-Google-Smtp-Source: AGHT+IGzHH59rQE88CK2q5qM/F60Tgrb1A80O07c7/rCPo0h8UV5Ik/pgnjoxZUyaxwiH2SDjhr7XA== X-Received: by 2002:a5d:4e4f:0:b0:336:647c:cef1 with SMTP id r15-20020a5d4e4f000000b00336647ccef1mr2801569wrt.44.1703013201713; Tue, 19 Dec 2023 11:13:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/43] target/arm/kvm: Have kvm_arm_set_device_attr take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:51 +0000 Message-Id: <20231219191307.2895919-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013301331100001 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-7-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 132a1b47d04..e6423d2720b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1689,18 +1689,18 @@ void kvm_arch_remove_all_hw_breakpoints(void) } } =20 -static bool kvm_arm_set_device_attr(CPUState *cs, struct kvm_device_attr *= attr, +static bool kvm_arm_set_device_attr(ARMCPU *cpu, struct kvm_device_attr *a= ttr, const char *name) { int err; =20 - err =3D kvm_vcpu_ioctl(cs, KVM_HAS_DEVICE_ATTR, attr); + err =3D kvm_vcpu_ioctl(CPU(cpu), KVM_HAS_DEVICE_ATTR, attr); if (err !=3D 0) { error_report("%s: KVM_HAS_DEVICE_ATTR: %s", name, strerror(-err)); return false; } =20 - err =3D kvm_vcpu_ioctl(cs, KVM_SET_DEVICE_ATTR, attr); + err =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEVICE_ATTR, attr); if (err !=3D 0) { error_report("%s: KVM_SET_DEVICE_ATTR: %s", name, strerror(-err)); return false; @@ -1719,7 +1719,7 @@ void kvm_arm_pmu_init(CPUState *cs) if (!ARM_CPU(cs)->has_pmu) { return; } - if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { + if (!kvm_arm_set_device_attr(ARM_CPU(cs), &attr, "PMU")) { error_report("failed to init PMU"); abort(); } @@ -1736,7 +1736,7 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) if (!ARM_CPU(cs)->has_pmu) { return; } - if (!kvm_arm_set_device_attr(cs, &attr, "PMU")) { + if (!kvm_arm_set_device_attr(ARM_CPU(cs), &attr, "PMU")) { error_report("failed to set irq for PMU"); abort(); } @@ -1753,7 +1753,7 @@ void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) if (ARM_CPU(cs)->kvm_steal_time =3D=3D ON_OFF_AUTO_OFF) { return; } - if (!kvm_arm_set_device_attr(cs, &attr, "PVTIME IPA")) { + if (!kvm_arm_set_device_attr(ARM_CPU(cs), &attr, "PVTIME IPA")) { error_report("failed to init PVTIME IPA"); abort(); } --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013346; cv=none; d=zohomail.com; s=zohoarc; b=FvI2Y1/aIH0GSDDoVHIBhKTPqnJ/XHUl4KyrsyjPX4+wP+GpQxQ1otcaA5ddfi6BiEr4nmlJem0kUl/5dOZ9yrYxZmCw4s3giQtxyOq46InVBxPIFMPKbmtosXmNcPLgfbxZMpGiAOvCCk2DENxsiv5PMhAspFUyHMhIjSXtl80= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013346; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=6zD6GqgpYlUbqN0SJRkAPG9ZDb0+QKHBj7N0uvLGJQI=; b=eserfaHGpfjxE0XdQFSDg5Sdc/ABU8kRjgKRvwoc1/8EHmOXvjxT3t4FWPkYiT8shmtSRotdlkUZldg4dyPzS87uxTQmEzCXb1YtR6/8mF9l/2pdcP2M8V5Ud9t4Cka4Zo1pEvCMmuiVXCfvUGwZcU0BSrr/tbcr3CUmM8Kh0PE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013346657895.287535778859; Tue, 19 Dec 2023 11:15:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfXG-00024w-FC; Tue, 19 Dec 2023 14:13:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWy-0001xT-0i for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:28 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWt-0001r7-Gn for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:27 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-33621d443a7so5046738f8f.3 for ; Tue, 19 Dec 2023 11:13:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013202; x=1703618002; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6zD6GqgpYlUbqN0SJRkAPG9ZDb0+QKHBj7N0uvLGJQI=; b=V1pOi+0O69AQzp4EkB/kv8pYe1406kYdJwP8W6t5k9vNJHhBHEfRwS5x6/mA4qhu8M h1c7p16fsp3lvsCJ+3QwBlxMzMhz0KXRTTcLL4ghEl59kq9oc76t9psQJ9w9bJaUrJU7 orA6AUiDoovY6zSTwduqg6EHhKkD33rmAv/b+adbu0g1WoyhMIg2z1GvsAgzynQeR+KO xw1XVIh7/t3GrZGH5l+bjFQn+FegmdKmBbUB5gTTDOK1q6cPHJDUpHkcu5jK5r4rpD0p R7Z6N/Q1Eo6oBTms7g5Ur4uL2GzJRrtiiG0PD2GkVpT11o4Fuh4RWusNWfySRZWL8uYe /SSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013202; x=1703618002; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6zD6GqgpYlUbqN0SJRkAPG9ZDb0+QKHBj7N0uvLGJQI=; b=A7iq9QrjddWX4UJox2FkuYuOJ8hdUTkBj5sWmrdADusq2hwJIiuHtZS/2cVIjeRFcr raRZlHjn6NZ2ZA9zT96EWiQuyDS2oPSH0zvVVKOzT1YFxP40ACRzq/9Xa2RoqCHxkJqo cRVPAu1evGcu/CGY/3w039Vx9X3wEfPcD+sgnvPoafRqxdY8/9OL22rk1wxku3GnBb0j xOrTnu8c0434pf0B5CrCaeKR7poTLfLOmFq4Wxh9V02x0MnEuT/gFfZax7wK7uXv+ofA 7S8fyBauvmdpDgmxppiZoSI2k6VLFDqqaUoMvWiRENInHwB3CtHauzr4c+2099Z71c8O ge3A== X-Gm-Message-State: AOJu0YyHlCDSRuChdzVEryEza9JOXZu4N06KxYDVbUqAcKEBkdE4YNaS V4l1G/FnMjmDPO+DXT33MD8TxYY3CcEn8r8zxjY= X-Google-Smtp-Source: AGHT+IG8w3gd7tr9UxZiRGzz2QmvDhKvvzNYrcgSh1BEoHtXb1p3B9YWLc29xPxKhyd/iSK7qR3r+A== X-Received: by 2002:adf:e486:0:b0:336:6d7d:71e6 with SMTP id i6-20020adfe486000000b003366d7d71e6mr1473502wrm.58.1703013202130; Tue, 19 Dec 2023 11:13:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/43] target/arm/kvm: Have kvm_arm_pvtime_init take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:52 +0000 Message-Id: <20231219191307.2895919-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013347502100003 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-8-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 6 +++--- hw/arm/virt.c | 5 +++-- target/arm/kvm.c | 6 +++--- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index d6d999b1ff8..4404ffeb1e3 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -205,12 +205,12 @@ void kvm_arm_pmu_init(CPUState *cs); =20 /** * kvm_arm_pvtime_init: - * @cs: CPUState + * @cpu: ARMCPU * @ipa: Per-vcpu guest physical base address of the pvtime structures * * Initializes PVTIME for the VCPU, setting the PVTIME IPA to @ipa. */ -void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa); +void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa); =20 int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); =20 @@ -268,7 +268,7 @@ static inline void kvm_arm_pmu_init(CPUState *cs) g_assert_not_reached(); } =20 -static inline void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) +static inline void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) { g_assert_not_reached(); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index be2856c018a..b6efe9da4dd 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2003,8 +2003,9 @@ static void virt_cpu_post_init(VirtMachineState *vms,= MemoryRegion *sysmem) kvm_arm_pmu_init(cpu); } if (steal_time) { - kvm_arm_pvtime_init(cpu, pvtime_reg_base + - cpu->cpu_index * PVTIME_SIZE_PER_= CPU); + kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base + + cpu->cpu_index + * PVTIME_SIZE_PER_CPU); } } } else { diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e6423d2720b..dbaebe9cd2c 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1742,7 +1742,7 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) } } =20 -void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) +void kvm_arm_pvtime_init(ARMCPU *cpu, uint64_t ipa) { struct kvm_device_attr attr =3D { .group =3D KVM_ARM_VCPU_PVTIME_CTRL, @@ -1750,10 +1750,10 @@ void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa) .addr =3D (uint64_t)&ipa, }; =20 - if (ARM_CPU(cs)->kvm_steal_time =3D=3D ON_OFF_AUTO_OFF) { + if (cpu->kvm_steal_time =3D=3D ON_OFF_AUTO_OFF) { return; } - if (!kvm_arm_set_device_attr(ARM_CPU(cs), &attr, "PVTIME IPA")) { + if (!kvm_arm_set_device_attr(cpu, &attr, "PVTIME IPA")) { error_report("failed to init PVTIME IPA"); abort(); } --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013463; cv=none; d=zohomail.com; s=zohoarc; b=a9GkOSmJYweFHH6UPMi2d8LoGHRfgMYfus4zPIsE2UQmmJPrLFZWbsKGPksq2suhghzAqxwkc2JLMaBPP5jCZWMtVrExNCqD2/E80xQArgiFGzLTKJwrw5tpAZR+SUhnNcnx2AOxjZvSgz7tsJD+j7AetafsNNfzvYwfi2fSUME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013463; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=IYhSIE/aRJaOrscSujAdKlBizLG69eYQKoHwvZcrqCs=; b=W7MG1gSuajVtJLT8XSEiLWcLvCQYvZEe7J0zJwX18NEYtS3XBz+U5sCGY5PM4Oa4LQk2iGI5SfO7K67CfRQn15Hpc29W2kHrimFJIfBtFlb/gxMRBoDRiE7V3MW2QZ/9CiL0jJFy469Q1wUADjqZMNHt6xTfJNhqt0Td7Es/Nok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013463182555.7875780650786; Tue, 19 Dec 2023 11:17:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfXF-00023u-54; Tue, 19 Dec 2023 14:13:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWx-0001wC-0B for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:27 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWu-0001rI-EW for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:26 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-40c6e2a47f6so51018965e9.0 for ; Tue, 19 Dec 2023 11:13:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013202; x=1703618002; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=IYhSIE/aRJaOrscSujAdKlBizLG69eYQKoHwvZcrqCs=; b=mfoFwr0yKc4vJH/kxxAylKH5uXOFga41U5k9nRWbzzoMkAHGWmEN3IhuApU7DMDfuI OvqSNKF4eIim5/ctz4ZiQhF9VkHKGhUyPb/spG7/ljfwRfRy6VlJVrUUfjfCdjVl2P71 S+hZCJD2eqRY6n9uz372x+99XiUeQPpR5Qa8+h+n/y1PNXPO3NhCAq/6EGj9ITVBJT6B Hs4CBDDVGAUT5h0t5Em/0lr8RsdYlXoq6P0DxVKGz6KK8OvqM1kCmvvCLt1sAk1j+swj h/cbWW5MFNp4HByl6jKsTYlssIImGwQDXhdKJ374lm4xhdkvIs57MKUk7OMV7dF63oJ4 h0wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013202; x=1703618002; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IYhSIE/aRJaOrscSujAdKlBizLG69eYQKoHwvZcrqCs=; b=NUhhBGwQcLbfPitelCe2GvTKUUsJzFko10sOO1gjsbIRBf2zvn3+g5JBJ95h/wfE5N RGOZ55uJF2R+KyRkK/z/gfjdX98LAUCdicSBFUuSd/JFvlfESHYP2SaJHHXyADjeOUMu Qp1tca5OjIdAy66uRPUxXyyXQmTJUwDBBoL2rpZVcLva1t4trE6zkcM2EbF8gszCZEai rHHbXuj5dSSs30vlQuyxZw06vrbNoHVS06TpOEnh4Uwwsi83eE5AWmozt5muScyKLVd2 Ev1DQRmvPCrv5/cJccm2EZqBWaEs6D1W0JpoeXOjCVCPUnJq+zFgn0TrD3g1EDQlqwKQ TE6g== X-Gm-Message-State: AOJu0YxMCkNoAdFeW1KLpPrhnENbY6i3ZH81CcLQl54/vGRHtKYbHws1 ydjs+qNbyzQlbb8Zq/IqzZWF26uzRnrb9vE5u/Y= X-Google-Smtp-Source: AGHT+IEmOmIAnf8rT1bkPC1LXegU30xTzo3molon8+CoWi1x6Vm0aOZMJQopL9PkLmW4b4dpdVgoRg== X-Received: by 2002:a05:600c:1f8b:b0:40c:601c:fc6 with SMTP id je11-20020a05600c1f8b00b0040c601c0fc6mr3208839wmb.245.1703013202544; Tue, 19 Dec 2023 11:13:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/43] target/arm/kvm: Have kvm_arm_pmu_init take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:53 +0000 Message-Id: <20231219191307.2895919-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013463967100003 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-9-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 4 ++-- hw/arm/virt.c | 2 +- target/arm/kvm.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 4404ffeb1e3..0a79545aa12 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -200,8 +200,8 @@ int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool = *fixed_ipa); =20 int kvm_arm_vgic_probe(void); =20 +void kvm_arm_pmu_init(ARMCPU *cpu); void kvm_arm_pmu_set_irq(CPUState *cs, int irq); -void kvm_arm_pmu_init(CPUState *cs); =20 /** * kvm_arm_pvtime_init: @@ -263,7 +263,7 @@ static inline void kvm_arm_pmu_set_irq(CPUState *cs, in= t irq) g_assert_not_reached(); } =20 -static inline void kvm_arm_pmu_init(CPUState *cs) +static inline void kvm_arm_pmu_init(ARMCPU *cpu) { g_assert_not_reached(); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b6efe9da4dd..63f3c0b7502 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2000,7 +2000,7 @@ static void virt_cpu_post_init(VirtMachineState *vms,= MemoryRegion *sysmem) if (kvm_irqchip_in_kernel()) { kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ); } - kvm_arm_pmu_init(cpu); + kvm_arm_pmu_init(ARM_CPU(cpu)); } if (steal_time) { kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base diff --git a/target/arm/kvm.c b/target/arm/kvm.c index dbaebe9cd2c..1e52077a9ce 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1709,17 +1709,17 @@ static bool kvm_arm_set_device_attr(ARMCPU *cpu, st= ruct kvm_device_attr *attr, return true; } =20 -void kvm_arm_pmu_init(CPUState *cs) +void kvm_arm_pmu_init(ARMCPU *cpu) { struct kvm_device_attr attr =3D { .group =3D KVM_ARM_VCPU_PMU_V3_CTRL, .attr =3D KVM_ARM_VCPU_PMU_V3_INIT, }; =20 - if (!ARM_CPU(cs)->has_pmu) { + if (!cpu->has_pmu) { return; } - if (!kvm_arm_set_device_attr(ARM_CPU(cs), &attr, "PMU")) { + if (!kvm_arm_set_device_attr(cpu, &attr, "PMU")) { error_report("failed to init PMU"); abort(); } --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013660; cv=none; d=zohomail.com; s=zohoarc; b=Q8HCQQXhes6MmBUEWxbXgYGHn993QJxy3wSIOTQD/35ryFcyJg2/xICtup2MDYuW6rUZSuSu7GGdbBg4lzfYT8qHxwjlDpajZbiVtLh7c8cuihyjooqNGoNjlNMFWFC9kDuz+NL32/U+3uVsp20idEKcgxWJqc/ugyprch6pqX8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013660; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=oMXiDjXN47Sje7EpZy9Ne96GwzFBEmIGwHarjbgxxck=; b=GL4LfBXpxZsgp0vO+fq+XhjlgGAibAoTUWLmfgBdDarCqRucoX8wyk/UfRY/24V1aDarN5OIDJL4VmMuxY6Xn6P2PZdPBitqVRPFtKhpZ1+LdGsl/rh0IrpoLY0NcSNp5sNLyTfm06YQEEBPcKFqBP7bMxlX5nuw0Yel7vvawlU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170301366091113.046119109973802; Tue, 19 Dec 2023 11:21:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfXH-00025s-Qr; Tue, 19 Dec 2023 14:13:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWz-0001yR-D4 for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:33 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWv-0001rW-AD for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:29 -0500 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-33666fb9318so2874799f8f.2 for ; Tue, 19 Dec 2023 11:13:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013203; x=1703618003; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=oMXiDjXN47Sje7EpZy9Ne96GwzFBEmIGwHarjbgxxck=; b=fYUZ6NC8iiTKbEWfR8FYbLyK/jzP1PqHOIXwqOc5Td0EKx8Z1Kws8cqeAU4cpZ1Cgz at3LFqko+lkIrRHTo4HxAdHzQmQpoBn5lObChBmku0XlI+NzUuxD+lto9bPrNRWiLl2Y 7SJlQyL4oBs8lL15Q1V1TMAPj7ZD14RgD8U4UYtRSsZwis1xNdqLkGDEv0go2ZHyySN1 /9rRy6gozORQIFK1NPiGvKfL0C8rE0Tql9QQJ4NW5I+k5g3pRYAkXX1zVbD2DFV3f+gK 97NPQwtqzEuhV+XDlzHeJcLRjDzuOilA9Gyg+eSa8YqNAXGNEfm4Je7f0dgmq5kwAfGW +k9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013203; x=1703618003; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oMXiDjXN47Sje7EpZy9Ne96GwzFBEmIGwHarjbgxxck=; b=rwaWtuKcMXW3HVDuKP9WcSeHWF5pNt3zRrYPL0IQhN1X76iRR5Az+KqP1FEZprVpX3 /WRyt+vgaXLgICPA1Ot6Gal8oDC1W+d6JGa2g43Jw+c7gWv9tzYNSDia2TShfscu0/GE zPylknYDFw7CFOYmRPSZRKKuP9YBA9kvuKCUVXT1r4GP07CHmbgR3xOhdwTROtpKOGZf p+KyT303CUZl2DbaHqbQWjNb4J+cx7ZEyLk4ppoxK4zGnUXaID6qQ6R2mBJXK/KGJn0i sW+fETkr9wQcByYlQQbConOai3RQpCeEx1HApWjommJRQWMDzxaL+rQDeZh+ftiD1Yzu ZGwA== X-Gm-Message-State: AOJu0YwZcNGdDwGeoplPpE0MS0c+24OTQl6nDB/HyZK6umdfP1Pxoppn 1qSUuIBC9bI5u6WyJN6ZwOV82osvrJNBH91Hvj8= X-Google-Smtp-Source: AGHT+IEmwcMJnKXaFoFSp7Pcz4h5MMF37zFYzqVnnkKAg1itCVT+HYdhm2dhGQ5dMQFMAZaebMLLXA== X-Received: by 2002:a5d:6088:0:b0:336:7474:61a6 with SMTP id w8-20020a5d6088000000b00336747461a6mr771970wrt.64.1703013202975; Tue, 19 Dec 2023 11:13:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/43] target/arm/kvm: Have kvm_arm_pmu_set_irq take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:54 +0000 Message-Id: <20231219191307.2895919-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013661279100001 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-10-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm_arm.h | 4 ++-- hw/arm/virt.c | 2 +- target/arm/kvm.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 0a79545aa12..cfaa0d9bc71 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -201,7 +201,7 @@ int kvm_arm_get_max_vm_ipa_size(MachineState *ms, bool = *fixed_ipa); int kvm_arm_vgic_probe(void); =20 void kvm_arm_pmu_init(ARMCPU *cpu); -void kvm_arm_pmu_set_irq(CPUState *cs, int irq); +void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq); =20 /** * kvm_arm_pvtime_init: @@ -258,7 +258,7 @@ static inline int kvm_arm_vgic_probe(void) g_assert_not_reached(); } =20 -static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) +static inline void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) { g_assert_not_reached(); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 63f3c0b7502..040ca2d7948 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1998,7 +1998,7 @@ static void virt_cpu_post_init(VirtMachineState *vms,= MemoryRegion *sysmem) if (pmu) { assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU)); if (kvm_irqchip_in_kernel()) { - kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ); + kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ); } kvm_arm_pmu_init(ARM_CPU(cpu)); } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1e52077a9ce..45ee491a56b 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1725,7 +1725,7 @@ void kvm_arm_pmu_init(ARMCPU *cpu) } } =20 -void kvm_arm_pmu_set_irq(CPUState *cs, int irq) +void kvm_arm_pmu_set_irq(ARMCPU *cpu, int irq) { struct kvm_device_attr attr =3D { .group =3D KVM_ARM_VCPU_PMU_V3_CTRL, @@ -1733,10 +1733,10 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) .attr =3D KVM_ARM_VCPU_PMU_V3_IRQ, }; =20 - if (!ARM_CPU(cs)->has_pmu) { + if (!cpu->has_pmu) { return; } - if (!kvm_arm_set_device_attr(ARM_CPU(cs), &attr, "PMU")) { + if (!kvm_arm_set_device_attr(cpu, &attr, "PMU")) { error_report("failed to set irq for PMU"); abort(); } --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013279; cv=none; d=zohomail.com; s=zohoarc; b=SOsQHGwqR9BfbnG/9aY1Gf0bRU8X/kjSP5mPnZpn8Gp+Ln/2QsKPtqnqsewP5w6wLIslhL4uuAIcpqRGQ1SCqwJUmdPbKtxwDd0WWrOZOpOqE86aANX5uaemW0xt7+k+AobKLzUFRhwybcLO/6Z5+8owmXV+6sbncpu7IqvTlU8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013279; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=WTa4ndbkRJ7n5XD1OTvmDhz9DP3vcZ/79akTztoRHzs=; b=AIfIS4osLqo1/7u3h7/NVyty1Y34n+vKvhbHagUzqQONOz/p8fkIKYrxBxZaAG1kck81FeQE6YnMIxVJtYYX99f5F9OKdGKSkSEbH8/9AP8X7bBNjOjNZ3VVVJGl9N9InRXhWZqcTrMRL4tRA4sseyG1bDwbCEuBTuSQ1ho8hIk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013279958566.7915304005107; Tue, 19 Dec 2023 11:14:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfX8-00022x-Ng; Tue, 19 Dec 2023 14:13:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWy-0001yG-Hy for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:33 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWu-0001re-SU for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:28 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-40c2308faedso58238635e9.1 for ; Tue, 19 Dec 2023 11:13:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013203; x=1703618003; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=WTa4ndbkRJ7n5XD1OTvmDhz9DP3vcZ/79akTztoRHzs=; b=sGbsg/U7pvR9aNO1v4Rh0A0wMYw2MqtTLlTka/yk3/wC2I1aTYTOvHgKnni1tsiJ7M PBqbKK6AsmhBv6xub4jJu62Nu7sQ9ubXp/U9mx7DP9MCwGK1/hyrGbKIv5MzQ+A7ac6N 4c6ya0tXFTJeKF0WNIrKmDBzESzwz71eJr+ZqU5Xjqt64KW1xQib2yWA3QBSg4mFGa+h 7gccOqvMl6K9mTlaU6lFv03gH+nbvxgSIkan9QLS3sHcxtZxN4wyoQHyGgXnIwrId2GE mtJlfsxLS5t9hFlswpD6Ch0oSyUJRNu2USzgWFwILbD1IukwQrRknE7E+hOfPnqYq5A2 SlLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013203; x=1703618003; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WTa4ndbkRJ7n5XD1OTvmDhz9DP3vcZ/79akTztoRHzs=; b=of0/NW8gJGWyKEc5FWb2qaMI9fkEmFolSg0WOKC38tfGP1bcRxzQJkqVRSldRxRG5k FE8gSQiiPmYe7OPCvYefi/soVrGnJj98ug8tjtJwkuNVS0EKHf1w8gs6d8daV8R7YhsS atnLvqkRQU5W4ECMJK9RC+d7BJDHQhS9PdsFJoxizRaRMpLcIKH99F3WOvho1yehm9UF PGrpHXwgc1I3UrBQkcK0qGJbBQebZdBV27vAwH3pG0vRqWYy1mOSTPiThoaUt96pVmoA 5PzNrXIb+6UkYU+mu+r2gNn+v5kJae9WPTaidNxENd+M0LynmdIAxQyhPsmwM5uGpVLb h24Q== X-Gm-Message-State: AOJu0YyaGw9UqdIef0IsZUlvHLGMhEi8MOkxr7OQmwQBIpgqi8PGrURG JQE6/kWZLBQxC961MeCm5+NzCu2qpipa9eKP+SI= X-Google-Smtp-Source: AGHT+IG3jkrLOBKv6FCgqWGtd5k5HaiMPcVFx7t/M42lS6WakImqEMo3vUWYya+NO/rmB4k8h6NtNw== X-Received: by 2002:a05:600c:2296:b0:40c:3103:2ecb with SMTP id 22-20020a05600c229600b0040c31032ecbmr10220394wmf.43.1703013203534; Tue, 19 Dec 2023 11:13:23 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/43] target/arm/kvm: Have kvm_arm_vcpu_init take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:55 +0000 Message-Id: <20231219191307.2895919-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013281314100002 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-11-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 45ee491a56b..9540d3cb618 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -62,7 +62,7 @@ static ARMHostCPUFeatures arm_host_cpu_features; =20 /** * kvm_arm_vcpu_init: - * @cs: CPUState + * @cpu: ARMCPU * * Initialize (or reinitialize) the VCPU by invoking the * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature @@ -70,15 +70,14 @@ static ARMHostCPUFeatures arm_host_cpu_features; * * Returns: 0 if success else < 0 error code */ -static int kvm_arm_vcpu_init(CPUState *cs) +static int kvm_arm_vcpu_init(ARMCPU *cpu) { - ARMCPU *cpu =3D ARM_CPU(cs); struct kvm_vcpu_init init; =20 init.target =3D cpu->kvm_target; memcpy(init.features, cpu->kvm_init_features, sizeof(init.features)); =20 - return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); + return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_VCPU_INIT, &init); } =20 /** @@ -982,7 +981,7 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) /* Re-init VCPU so that all registers are set to * their respective reset values. */ - ret =3D kvm_arm_vcpu_init(CPU(cpu)); + ret =3D kvm_arm_vcpu_init(cpu); if (ret < 0) { fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret)); abort(); @@ -1912,7 +1911,7 @@ int kvm_arch_init_vcpu(CPUState *cs) } =20 /* Do KVM_ARM_VCPU_INIT ioctl */ - ret =3D kvm_arm_vcpu_init(cs); + ret =3D kvm_arm_vcpu_init(cpu); if (ret) { return ret; } --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013477; cv=none; d=zohomail.com; s=zohoarc; b=hDxMqT1Gn70GRFGE6FCSLW3KPu7mMGmIor8Dr8lk+whWJKW+ZZCJLfXoA9kD4RX8pcI7YO6OkK0lXqmVcohLJBxpsPk5v5xj7gRbsib8HK8Dr/CmZJ3ZoXhH/KR5LJHOOPeA2K+4WiI3quXW+U8ghUfZG+hKpxlFELyd6IJq/Gs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013477; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=u7RSwDz13+9sv6W+3QlIzSQPKzKTiI3ycp67owFhcNM=; b=hwwikNGq5fE0EZxDtkfQxCS2/z+U115mE0RgdPxBsxaoacVCFTXCctLizUeEJPQ2FqaKvpA0Z1lh5O3GU1DaE6fcJuE5Cr7Wl3X5hGOP3nsw1JqqJHz8LNEsHe13nimWT9yyj2EemHPixjZrhNp+CIvAWOH0qqxSP+c+UaoV1NQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013477487720.3561048295999; Tue, 19 Dec 2023 11:17:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfXC-00023h-3X; Tue, 19 Dec 2023 14:13:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWz-0001yS-NB for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:33 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWw-0001ro-8z for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:29 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40c39e936b4so56217315e9.1 for ; Tue, 19 Dec 2023 11:13:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013205; x=1703618005; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=u7RSwDz13+9sv6W+3QlIzSQPKzKTiI3ycp67owFhcNM=; b=gA5uj+lX9sLkqTI3YNNrGi64fk2YQ/9jDP1QBYootLkNsStg1ikhUilbkFOXE+Qqwe ZUOsSb+aqAPT1R0sFP1QWmNJBlD4lqTOovM3uQLjyhRjqmbYDyvpd5uscsj+wQ6anj32 pPh0xfVbWFBNp+HcIN74sG7arMcXULuMVfgFh1nBs0bHSYlV6rEzzjvcxTqXysUNccGv 4VmE7VLfhEjQbvvWnXJmphuDN1BaV0edrkKXspYOMRvro8XWuBsjVyV8hMqCSduCA5g5 /7ekFOS2MjvDEWDifewRTUboLvVyIY6vaGWrrzsfdCtQsGf5NTGMXRFYAql2uiG/nwiK jdVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013205; x=1703618005; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u7RSwDz13+9sv6W+3QlIzSQPKzKTiI3ycp67owFhcNM=; b=r/5YU8xB+VNCTzKjGY+wSPQ12zEkFZD2BI4tV/1fmiOUfX8e38OAcHjUV0eMezvBCZ 1kKoBlczzgkTefboCVFexNM9+tdNSw7Rqed+9xJlCyCkK7bsT7h0T4FFdrkEH8jPaUn+ cWjC03qDsHfQAEASNLAUECV6tiHwNhe0i/xN9pW+1eavCCTB59tbJukRkZC8iP+6ZbNl JV/dnA54j4HY6HtzJiQhI6HYVdwrNfl5LuMNDJbck1ropnMBGCjMcye8pnaCB1CDiwR8 v0IEBIz5eL8U9/laiz6izOiMMZNTNFEHbR3vJxLEwkj3+qt3NVyfGhhymcC904jNG/jO aHyQ== X-Gm-Message-State: AOJu0YwQ8c/jl/ZYsToCNtC7xQN+8F/aKv4Qga81PNi8CtoWYw8f7Q4A dA76/MKbXPMByLRG360fa18I4vxPGDTY9ffCnt0= X-Google-Smtp-Source: AGHT+IHZNn6/HaDsLqGPgMwa7K1LQ9FCrHo2foMkvozzOwSBF8Kvo5j05ahsAImOt8iaXHNdYxUxIA== X-Received: by 2002:a05:600c:16c4:b0:40c:3133:6f02 with SMTP id l4-20020a05600c16c400b0040c31336f02mr5045282wmn.342.1703013204803; Tue, 19 Dec 2023 11:13:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/43] target/arm/kvm: Have kvm_arm_vcpu_finalize take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:56 +0000 Message-Id: <20231219191307.2895919-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013478920100003 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-12-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 9540d3cb618..a2370bc5747 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -82,7 +82,7 @@ static int kvm_arm_vcpu_init(ARMCPU *cpu) =20 /** * kvm_arm_vcpu_finalize: - * @cs: CPUState + * @cpu: ARMCPU * @feature: feature to finalize * * Finalizes the configuration of the specified VCPU feature by @@ -92,9 +92,9 @@ static int kvm_arm_vcpu_init(ARMCPU *cpu) * * Returns: 0 if success else < 0 error code */ -static int kvm_arm_vcpu_finalize(CPUState *cs, int feature) +static int kvm_arm_vcpu_finalize(ARMCPU *cpu, int feature) { - return kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_FINALIZE, &feature); + return kvm_vcpu_ioctl(CPU(cpu), KVM_ARM_VCPU_FINALIZE, &feature); } =20 bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, @@ -1921,7 +1921,7 @@ int kvm_arch_init_vcpu(CPUState *cs) if (ret) { return ret; } - ret =3D kvm_arm_vcpu_finalize(cs, KVM_ARM_VCPU_SVE); + ret =3D kvm_arm_vcpu_finalize(cpu, KVM_ARM_VCPU_SVE); if (ret) { return ret; } --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013485; cv=none; d=zohomail.com; s=zohoarc; b=jXLi2indYY3zbAYf9hdmrTuR5rx4fyXdz8AO5B+1Z+YBAHnu0ihPtvrJOWPqOKHM1ET3VmhNRftJmGy4jyPu3SYEBNuxKohiMeQw3che8g2nZFmFZsSKNruXeKC+ln3pV77Arb5VJW8NRP30TB/8ra3Nx0PYTBXX6mLjG0+OE1k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013485; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=DxeuhpipM3BEPBaMclMGluLt2DuQa6fF5XvciTbwcOc=; b=HMw880VVZG051OrUbArBGJIA6XpVQD1X7RvJMYh+4qDcS9gq+fNvpJQ0685m8hLzrSqQgyr5U8jHdPQNwiZaxJFEXkdPUGHyq5wCXI2rF2DQpfTvbn/ayttvDtRC6OFVSZ0GqzFefpWEekFjJ7oWCEBKZtefUYYpPDs0xxRpj7Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013484622538.6172341134848; Tue, 19 Dec 2023 11:18:04 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfX5-00020p-B5; Tue, 19 Dec 2023 14:13:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfWz-0001yT-Tz for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:33 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWw-0001s0-KK for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:29 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-40c38de1ee4so49391895e9.0 for ; Tue, 19 Dec 2023 11:13:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013205; x=1703618005; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DxeuhpipM3BEPBaMclMGluLt2DuQa6fF5XvciTbwcOc=; b=jPP4v1YFt8FfLAPiWsSUpcKCpTCeuZa+i2Pb7sbkqp1HTKtsQF3Jt0THmhoN0FNsai ZIcEGJXVHv+4pZ/4VV/A9hgozdaQFBvEVHAV7B5Cl9vCPNNVmLW0ek02riSL0hUKclin pXelxT4NE7QCLhWFtcsTafzdMxDUpPy+rXJl460TPF2XE+OKmj+XIFrrvRY0tjnQ1Njc xPDcVjwxKkKlIXaEQfXXpfsq4OuF47uQr899WOXEzP4UblNOZeT2Blkn4/SY5kp4zGeZ EZ3nNJKRJqkuN9uaOYc9WcLcg4uXevoIIEGCe+qoEvNsYBdRUtCpDnOk8jFcYjI0vNL4 GAcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013205; x=1703618005; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DxeuhpipM3BEPBaMclMGluLt2DuQa6fF5XvciTbwcOc=; b=D02BE4GD0KyNAyr4hzJhIRhU6fL7ozE1N+7kOtDdMPAwsHK6pDRByyY9EWkMIxzc/G dqEHKqEyEbt3Q0GmOcYBgbwVN+7xUUlT0zdvbFMqVsWRMbzul4ALyD1CUJZq+JJCVzWK 6VfhZfSxlVBENVp4aQaoXtpx3B16T1l1dK4L1fGI2mnyDaj3fMDexuhcuSjtNFR6UjcS YaVYKddMm7Smg4C0Ly6hb3H3h8qYIhRbts+vdI+IFZOXFMlaPMMXBVfhmY3u3o7Tw1mh f8QBxwxJhPnXdhLvpfyWbeBfWkgeul+pC1YE/fPhwlgpM+hZfWen9ezY/TVuMUs8554G CNCg== X-Gm-Message-State: AOJu0YzxGfIpaby5yfRwrzbY+rtEcbrM9MBsL1rUL2TC144K718fUeQ2 Dn+EV3YsOskFD6rGvJUEnoL3+iS57ZbxaJFWi6U= X-Google-Smtp-Source: AGHT+IHyRfHk0j75hzvrHN6b2AHyayX2ZXxz2idLKZNf3Gpu3HNa/lGcR0wBhDZ9J91NI0H8jl9j9A== X-Received: by 2002:a05:600c:b41:b0:40c:2a41:4a35 with SMTP id k1-20020a05600c0b4100b0040c2a414a35mr9594728wmr.130.1703013205339; Tue, 19 Dec 2023 11:13:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/43] target/arm/kvm: Have kvm_arm_[get|put]_virtual_time take ARMCPU argument Date: Tue, 19 Dec 2023 19:12:57 +0000 Message-Id: <20231219191307.2895919-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013486694100007 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-13-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index a2370bc5747..5973fbedde1 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1034,20 +1034,19 @@ static int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) =20 /** * kvm_arm_get_virtual_time: - * @cs: CPUState + * @cpu: ARMCPU * * Gets the VCPU's virtual counter and stores it in the KVM CPU state. */ -static void kvm_arm_get_virtual_time(CPUState *cs) +static void kvm_arm_get_virtual_time(ARMCPU *cpu) { - ARMCPU *cpu =3D ARM_CPU(cs); int ret; =20 if (cpu->kvm_vtime_dirty) { return; } =20 - ret =3D kvm_get_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); + ret =3D kvm_get_one_reg(CPU(cpu), KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vti= me); if (ret) { error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); abort(); @@ -1058,20 +1057,19 @@ static void kvm_arm_get_virtual_time(CPUState *cs) =20 /** * kvm_arm_put_virtual_time: - * @cs: CPUState + * @cpu: ARMCPU * * Sets the VCPU's virtual counter to the value stored in the KVM CPU stat= e. */ -static void kvm_arm_put_virtual_time(CPUState *cs) +static void kvm_arm_put_virtual_time(ARMCPU *cpu) { - ARMCPU *cpu =3D ARM_CPU(cs); int ret; =20 if (!cpu->kvm_vtime_dirty) { return; } =20 - ret =3D kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); + ret =3D kvm_set_one_reg(CPU(cpu), KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vti= me); if (ret) { error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); abort(); @@ -1289,16 +1287,15 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct k= vm_run *run) =20 static void kvm_arm_vm_state_change(void *opaque, bool running, RunState s= tate) { - CPUState *cs =3D opaque; - ARMCPU *cpu =3D ARM_CPU(cs); + ARMCPU *cpu =3D opaque; =20 if (running) { if (cpu->kvm_adjvtime) { - kvm_arm_put_virtual_time(cs); + kvm_arm_put_virtual_time(cpu); } } else { if (cpu->kvm_adjvtime) { - kvm_arm_get_virtual_time(cs); + kvm_arm_get_virtual_time(cpu); } } } @@ -1879,7 +1876,7 @@ int kvm_arch_init_vcpu(CPUState *cs) return -EINVAL; } =20 - qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs); + qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cpu); =20 /* Determine init features for this CPU */ memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features)); --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013486; cv=none; d=zohomail.com; s=zohoarc; b=e+VOtowkdh4mgyiBtCmXuewbUMqowkL9t71rmK7HtbLnXfAwGVzAQfGZ+KAVvneEamm7FLq3s/esfEpkViig4z0sfVyCfcVyQ3YvKqnIhRgeh0VUWg7X2E97sdvafyzP64KBQK+UoqPfa9ug4TchhneemKn705mkwk4XolpvFQg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013486; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ttQrBvB/20bRVa3vwR6cfQBa/oaIBUExjVmg1GHCzFA=; b=CbwHDwPW190yf5CMyg/yD0q9IYHq6mRK9PjgT0vbp9ByhZm68UdkOWijQc0GW3W/DD0Yl3Ph8FIbX3Jz17kjnUMiltya+EKbt6u3TPM5g6o9+1jNq80lMFmejyj0VFgT3B0Y62NPjbNqNMnN4iWNKQPW++1ExOYdeTQu+7X8mUo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170301348638026.35525246127486; Tue, 19 Dec 2023 11:18:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfXC-00023f-0h; Tue, 19 Dec 2023 14:13:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfX4-0001zR-2L for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:34 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWy-0001s4-9p for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:30 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-3364c9ff8e1so755f8f.0 for ; Tue, 19 Dec 2023 11:13:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013205; x=1703618005; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ttQrBvB/20bRVa3vwR6cfQBa/oaIBUExjVmg1GHCzFA=; b=vmEzDX3+hLpd9ZL7wqjm3euvH7BLGb4DOaDorChTGy8mRgAAbEDJBbXo/FLz/hyjGa Jsyxtp6KPqKZmTYOiDpvIlVTwaG5I4pJlu+S+CeJrCkQUo3LDUnm05Eopj4/0rzU2ADV fq9e31tLVgKgK2dmSfzZfTy0r03Hg04Hb6YXiRgyZC+gFYo0+BSUpHpdD9ySeri6swke NvH+fYD7aSep5Soq9XiOg0B+zeRHKLLOCXxl5Hae/t/p1pqiNl+e23ydwDj+1SEeMeyM 9nsr8kjSfIomyX8ruJsNgOop1P7OrR0lRgV43zpLoh20/9/D2RHsvnqphgFNLwWJ1O+t 7v1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013205; x=1703618005; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ttQrBvB/20bRVa3vwR6cfQBa/oaIBUExjVmg1GHCzFA=; b=gcj9kcT9fCtQaHuCpElwJRsQER1zmlTGA/3IaKvWphq943YtlQCd5uA52dD3lr1Q9e EUBXjT2rk92VUxLQpniYVA7Gfhwq+XZa5lHHzTI35wdpNl3/LnDmi22wpV3YZTiyKNNb 9PDMafear4pH5/umfmb3Q9JPOTQTGcZ4nYHFSLsroyCo2sPokSSBrMG9qN72kWE4dUcl VuZJdQY3C5rYG2cjMEtUlhwn0h+ImLS2JDmQrNaI2vClGdLfAMLFUm+KSUOk3vQxQere 0x9EJ51FdPN5bJgrYlMI/Q3XZt6NTllrAi6kbRPIDw2y+dz34sqS4a8nBAZ27CsKuzsT Ozwg== X-Gm-Message-State: AOJu0YxRulXhgaQeL080nv61F6/QbD1cpQSuI5Hg4tErnLzMoKqfPits yOa1+Ta02QPl96OuYqhqCPUNDaXWVLLaxQVx7+8= X-Google-Smtp-Source: AGHT+IGeIQJ6bGvIAyvPVWeOG4w7gQiUgdwO/d1DniY9gM73Avx5SXBeoGO1VjaVnX8rTcL2ayB7rg== X-Received: by 2002:a5d:4ac8:0:b0:336:4a0e:34bb with SMTP id y8-20020a5d4ac8000000b003364a0e34bbmr961215wrs.39.1703013205746; Tue, 19 Dec 2023 11:13:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/43] target/arm/kvm: Have kvm_arm_verify_ext_dabt_pending take a ARMCPU arg Date: Tue, 19 Dec 2023 19:12:58 +0000 Message-Id: <20231219191307.2895919-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013486685100006 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-14-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5973fbedde1..e4cd21caefc 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1170,18 +1170,18 @@ static int kvm_get_vcpu_events(ARMCPU *cpu) =20 /** * kvm_arm_verify_ext_dabt_pending: - * @cs: CPUState + * @cpu: ARMCPU * * Verify the fault status code wrt the Ext DABT injection * * Returns: true if the fault status code is as expected, false otherwise */ -static bool kvm_arm_verify_ext_dabt_pending(CPUState *cs) +static bool kvm_arm_verify_ext_dabt_pending(ARMCPU *cpu) { + CPUState *cs =3D CPU(cpu); uint64_t dfsr_val; =20 if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) { - ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; int aarch64_mode =3D arm_feature(env, ARM_FEATURE_AARCH64); int lpae =3D 0; @@ -1218,7 +1218,7 @@ void kvm_arch_pre_run(CPUState *cs, struct kvm_run *r= un) * an IMPLEMENTATION DEFINED exception (for 32-bit EL1) */ if (!arm_feature(env, ARM_FEATURE_AARCH64) && - unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) { + unlikely(!kvm_arm_verify_ext_dabt_pending(cpu))) { =20 error_report("Data abort exception with no valid ISS generated= by " "guest memory access. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013206; x=1703618006; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mV1FstJ24t/zgC1MccTigP3pcwPlKu6JPGqh4aMLl+Y=; b=HSBpxcnkmyTbOdmUQln6188XXPSyqQ+CHpalRvB+U6gLMcQLDapAe1c+msanSmVXT5 kdyJcciSkwfJ/IPop4CQC53QwP85SjXbIpsIWbEq0DPRHfxapT6PJJghFxTOsg332iKK i/7O0ResTrXdJVDfP0RpsPZKd7GWETOQXDu1GvuM+hf1z7SyCXzZ7GWqkboVdnFvAQDb 1hKN5bealGE27DKrzw08wQ54JSlSbXzmf+ctMhB1yJF6ZpGf7dABpqqrYO1pjGQtZhU5 qEzHuAuI93ft5pFoi7Uyd4ieY91kJIp/JT1+2SH7jP5478s1ql53j6pEcUMPg+6P0yAT 8IgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013206; x=1703618006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mV1FstJ24t/zgC1MccTigP3pcwPlKu6JPGqh4aMLl+Y=; b=SoYFlBiapuSRjLEBq9TdsA4aWfodG6nbo9S9abzIVl36Vs0cyy/+KwAUcVantXqYDQ G4PYnlUZTqD7aJghxKuwrUG66LKwGDlLiYmI47fkVyq61Yhtvr6HPg/wUfk8Okf/KILI TakCDUGoTSscxr8J9wxBq95O2D/zkKh/3mU5CaDdxdoq6HNIOZLzTOJHmcsriE5j/YqH l9FPBnKDaqyVXrb9+CaMZvX+jNjcMNRiaEO1F1StJui6FuLVQJXUht4EuQYl1uWNH3d7 p4fPths/ClfHu3hnK7MHmQBdt5hRJ7/C6RNhACpHYtFg8SwaTKFyxKIQaixUjbDhZatK afpQ== X-Gm-Message-State: AOJu0Yzk6nx92NeeqnBghBH9kJwM8mUqLC5HbVwUNoyjU8iWaYVyWKnV f2e4AchunDRcT0+UOYXdCSHbzxNFZbdiMdzgrDs= X-Google-Smtp-Source: AGHT+IHmb9G6NaboR28VNtAHRvWPXbu14TTMDuSKBtU0p/rPdlmE+mulVpSab+9yqGSGYTSgijAWNw== X-Received: by 2002:a5d:6641:0:b0:336:5be9:adfd with SMTP id f1-20020a5d6641000000b003365be9adfdmr3515616wrw.68.1703013206162; Tue, 19 Dec 2023 11:13:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/43] target/arm/kvm: Have kvm_arm_handle_dabt_nisv take a ARMCPU argument Date: Tue, 19 Dec 2023 19:12:59 +0000 Message-Id: <20231219191307.2895919-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013673290100003 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-15-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index e4cd21caefc..075487e62f1 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1302,17 +1302,16 @@ static void kvm_arm_vm_state_change(void *opaque, b= ool running, RunState state) =20 /** * kvm_arm_handle_dabt_nisv: - * @cs: CPUState + * @cpu: ARMCPU * @esr_iss: ISS encoding (limited) for the exception from Data Abort * ISV bit set to '0b0' -> no valid instruction syndrome * @fault_ipa: faulting address for the synchronous data abort * * Returns: 0 if the exception has been handled, < 0 otherwise */ -static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss, +static int kvm_arm_handle_dabt_nisv(ARMCPU *cpu, uint64_t esr_iss, uint64_t fault_ipa) { - ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; /* * Request KVM to inject the external data abort into the guest @@ -1328,7 +1327,7 @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uin= t64_t esr_iss, */ events.exception.ext_dabt_pending =3D 1; /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */ - if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) { + if (!kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events)) { env->ext_dabt_raised =3D 1; return 0; } @@ -1420,6 +1419,7 @@ static bool kvm_arm_handle_debug(CPUState *cs, =20 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { + ARMCPU *cpu =3D ARM_CPU(cs); int ret =3D 0; =20 switch (run->exit_reason) { @@ -1430,7 +1430,7 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run= *run) break; case KVM_EXIT_ARM_NISV: /* External DABT with no valid iss to decode */ - ret =3D kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss, + ret =3D kvm_arm_handle_dabt_nisv(cpu, run->arm_nisv.esr_iss, run->arm_nisv.fault_ipa); break; default: --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013496; cv=none; d=zohomail.com; s=zohoarc; b=B7GtFNsZlbfzOd2dDZ5nPAkd15S+Ya3fs6gN+WvFavYXpBcb0KVsehsxMMy1PqphKgH7InANR0LHcBj2CckA7kyMomTeRRxUwMS21qMp6+jIGijC43xXzvSozGuV8DH9zRMKm2urui3ifhQlKg8bHCFI7Dc3lTvQHwiXU5tAJTY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013496; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=hXHi71kEAlJCpqi9ahK7azGhnduyvRCji9I/qeZQJBk=; b=KHdQCkHgVhCMiL7BrmALffgD+/UYVb4d2Oeutwki7y3nrnk/sNXbSDwzJYwzFjr1ZGXwhFe1vXT/Fbl6Z1p5jypYsCUtyj2yLb3r1XBZUNdr1uJi+WXkh/wiY2bbNuWVcy/k768cHnUHGegNbpzhbUdK52WlsTfJB4Px5PVAVd8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013496082273.3788755770704; Tue, 19 Dec 2023 11:18:16 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfX5-00020q-I1; Tue, 19 Dec 2023 14:13:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfX4-0001zS-2U for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:34 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWy-0001sG-AX for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:30 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-40c29f7b068so54206185e9.0 for ; Tue, 19 Dec 2023 11:13:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013206; x=1703618006; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=hXHi71kEAlJCpqi9ahK7azGhnduyvRCji9I/qeZQJBk=; b=Vsd3gANflFneGA+YS05TmFSkGLznOeWxai9npqf6DHkqce9qKikWJ//prVPC5LPabI 8M8uHZNNSyAUEC+VBaFkJpjBMn/1O8mkO1/+OMJ3Kg+W0Gbxoe672YK8zFhEWJDBBDdO t+kwtXuFETAsiSjUFAUhyCYxkj7gLEBUmb09Gm8JFk1D1f0orR90bf+Aj3Oeepnp4ePs 8Ro92KGKS7pNwZSG2blKNN4BbUqq/TUUFMLtUN4gzhTFg538b80xSQAg6QuWlypMbxpx +VJtAnPhlYhAxttgr0hMZP0bTOTnIYIkJfCp+YYinwZotuWb16UuBTmF6oxIN5lTVxJJ Knxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013206; x=1703618006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hXHi71kEAlJCpqi9ahK7azGhnduyvRCji9I/qeZQJBk=; b=JCNIiTDnEU49F+SEV33uTckiiT9YwBmLz02PFQc2yPGLXXj3GXXAoyOAD1bgSe7aaE 09wUKyosvS75sK9WgIm3KTeBXtlzv4yHo5vDuGlihpV47T+bxRbkGyr0Sae48kK3KSNV rfg+w9N32/zTb7+7B6zFbF8p3CbTg7Z/AtcT0V7+LvpHcBObuX2Qb4WWgSKm7MFHtXoq plzm/W90o3j52kJzoWPEujYb6ie/JrW/TEQAfQo+Hphp1UI2jfwmpG2S+DLHckhkbg2N Dqb1P5A+vxcZmVCycAh2HGDbrQ6fN8kyCft6ICij68+7+eOMI/o7fm1auFfnHJGFBIEM ersg== X-Gm-Message-State: AOJu0Yw9TaqQh0uRNNoLgYlObGvN4QLO0+MmUckszOLx2i2YvGtzbC9P JAwO2+8BmNItNywivSU2NxTgLUMHeq5ncrYU3d8= X-Google-Smtp-Source: AGHT+IHhJkObBwTfqbB8lly4Y+6IpViaKxTymtwvfRuUSdZETZMTe28oyFikr2m8OXAmAhZn414MIg== X-Received: by 2002:a05:600c:450e:b0:40c:2b2b:6414 with SMTP id t14-20020a05600c450e00b0040c2b2b6414mr8710138wmo.100.1703013206646; Tue, 19 Dec 2023 11:13:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/43] target/arm/kvm: Have kvm_arm_handle_debug take a ARMCPU argument Date: Tue, 19 Dec 2023 19:13:00 +0000 Message-Id: <20231219191307.2895919-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013498743100001 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-16-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 075487e62f1..6794dc8ad61 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1342,7 +1342,7 @@ static int kvm_arm_handle_dabt_nisv(ARMCPU *cpu, uint= 64_t esr_iss, =20 /** * kvm_arm_handle_debug: - * @cs: CPUState + * @cpu: ARMCPU * @debug_exit: debug part of the KVM exit structure * * Returns: TRUE if the debug exception was handled. @@ -1353,11 +1353,11 @@ static int kvm_arm_handle_dabt_nisv(ARMCPU *cpu, ui= nt64_t esr_iss, * ABI just provides user-space with the full exception syndrome * register value to be decoded in QEMU. */ -static bool kvm_arm_handle_debug(CPUState *cs, +static bool kvm_arm_handle_debug(ARMCPU *cpu, struct kvm_debug_exit_arch *debug_exit) { int hsr_ec =3D syn_get_ec(debug_exit->hsr); - ARMCPU *cpu =3D ARM_CPU(cs); + CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; =20 /* Ensure PC is synchronised */ @@ -1424,7 +1424,7 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run= *run) =20 switch (run->exit_reason) { case KVM_EXIT_DEBUG: - if (kvm_arm_handle_debug(cs, &run->debug.arch)) { + if (kvm_arm_handle_debug(cpu, &run->debug.arch)) { ret =3D EXCP_DEBUG; } /* otherwise return to guest */ break; --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013550; cv=none; d=zohomail.com; s=zohoarc; b=g+S9vBi6+kmMW8RKqChzbzXTQZGY8TaVKbSpa6KqBzN/g2OXCU2OT7zK4bjNJbm75Jyji0Sv8HkMKME8oIGxKrEL+Yv3G5+keDtWqdY91OibBF6U19MKEy+OV0VusXUoY2mP1mqwUk2ubz3NURYZVC/HoHRXh2st6qABT5Cj3sM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013550; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=3OdKUaJzJak2eJQTHO6VMVDhLUVUEOXkAdntoItIO00=; b=KcdSOrsftyt/yZrEvriLW/aUDS0MHTyxxn/HAdcYCBzO/H8z8I4BioADrga9nOkzsudpZYMwyxPxiAzvJFH9+zVAXsN5W9toOuc4RGGwEfSKPqdhtlOSp4Ng4qoAcKJf5MvQa7LQnG/iYyhSmh1qTj7D6xodaL7ETlV+nQQ6zqg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013550414754.7055302579938; Tue, 19 Dec 2023 11:19:10 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfX7-000220-Gw; Tue, 19 Dec 2023 14:13:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfX4-0001zc-3g for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:34 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWy-0001sN-Fk for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:31 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-40c236624edso54041375e9.1 for ; Tue, 19 Dec 2023 11:13:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013207; x=1703618007; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3OdKUaJzJak2eJQTHO6VMVDhLUVUEOXkAdntoItIO00=; b=mqgwWU7d3m47kwVFn1TJ7XRihgcdPXFNv7xbqPHPItrSHnMhtWKjI68y7UWyNft6Xs ku+yuzwZbTo04qiOG0oa3irf0VE1gJnppLQOjI2HQrpLOKCE2c6oilFpq8lAiZpypzRg PadlId9hNDMTd1Whh/YelqmJB5aqf9JJCqtnAMkjiWrMipZVXBXb1iQWZJHT9kC7VU1E Tuk8mv5eYuj6eNh/GCKeAQhd4/RnlY39/uVATX3kC6NBdE69KItD6ieNrPSv9vOkFPtR Oh1A9/6BRV3TA8rlb0AZDl1iKPjglSVkyHEVavMjVUvPEQPOWeBG+hmehvV6aJW0Z1Mt HXPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013207; x=1703618007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3OdKUaJzJak2eJQTHO6VMVDhLUVUEOXkAdntoItIO00=; b=JARoYOrOvt8h6FfodYY1+Mj6p17Rgv/ZrCGiseA6mZalzubo0ab6ja4i6jVSnxi7US PwigF/cLkuyOSTsK7xuWw1gbnhBaTdzw2L4DRwFqBs5f1n9Od+d4ATwR8NlscAUNlIhr MIeipSzvdFJN6q3yeL6RdhFDtCd9MdAdqynVU51ATTB/5GmhuoCPxrmHZnwt8vR+1XwC cmJ3F8IzR91xcMyVFPjOOtPooahVgv+Zp78abAO8R6/OC9IgqQwxN6twvxdCZZ4gSKkd 8g56LmRgfgLFjx/v+fk3AiCtldkxWu+YADUvadiNEQ2SgUmZlkm31NFVRJImHrRuMN0u 5Jog== X-Gm-Message-State: AOJu0YxLmp1rhtnxWWiwim/HP+eMFviCYQ+hPDsZlWh9HnE70+eGFFWF QKuyK+Ctb2ZJd7uIXaw6gcP4gKL40i/l5gM1r40= X-Google-Smtp-Source: AGHT+IGnnspE7Dph81DxXwA12I+VBrjv+juHPva6t3s/1nxF+yihD4nh6hhzEkO+sbcWzWUmcHutpQ== X-Received: by 2002:a05:600c:a43:b0:40d:28ce:bb9e with SMTP id c3-20020a05600c0a4300b0040d28cebb9emr765800wmq.58.1703013207172; Tue, 19 Dec 2023 11:13:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/43] target/arm/kvm: Have kvm_arm_hw_debug_active take a ARMCPU argument Date: Tue, 19 Dec 2023 19:13:01 +0000 Message-Id: <20231219191307.2895919-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013550896100001 From: Philippe Mathieu-Daud=C3=A9 Unify the "kvm_arm.h" API: All functions related to ARM vCPUs take a ARMCPU* argument. Use the CPU() QOM cast macro When calling the generic vCPU API from "sysemu/kvm.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Message-id: 20231123183518.64569-17-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/kvm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 6794dc8ad61..c5a31838437 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1453,11 +1453,11 @@ int kvm_arch_process_async_events(CPUState *cs) =20 /** * kvm_arm_hw_debug_active: - * @cs: CPU State + * @cpu: ARMCPU * * Return: TRUE if any hardware breakpoints in use. */ -static bool kvm_arm_hw_debug_active(CPUState *cs) +static bool kvm_arm_hw_debug_active(ARMCPU *cpu) { return ((cur_hw_wps > 0) || (cur_hw_bps > 0)); } @@ -1491,7 +1491,7 @@ void kvm_arch_update_guest_debug(CPUState *cs, struct= kvm_guest_debug *dbg) if (kvm_sw_breakpoints_active(cs)) { dbg->control |=3D KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; } - if (kvm_arm_hw_debug_active(cs)) { + if (kvm_arm_hw_debug_active(ARM_CPU(cs))) { dbg->control |=3D KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW; kvm_arm_copy_hw_debug_data(&dbg->arch); } --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013673; cv=none; d=zohomail.com; s=zohoarc; b=Sz7KCr0p01OnH6lmvdRgF2P+YsATL1euT2FWFPRd7QfQkwKCvMk9KkLl+I0B1dUtmqExp9nFdvVkvhwlEvR1GTANK3T3rAdZk9tNZph0lFzlRRWNLGjcj4GpE5GK74UBvocZip4Uv9nMaXpOhYcd0LQUOlJDn6zfqhYS0GXn1fA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013673; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=0gBHCNexdbG+zEv+b4Ytrqor1JdvLFRCIBJ8HsM7maA=; b=Qx66wvvr6/fdy0+0NM+uiW+1lDQUTpD3yH9LnRwO4DIz6jWcwOXTajGIKgYmZ1rmvJvtZ4iPGTAwfs5AQriz6V/1aaXairreuDiC8DBbiPci3x8DFcSkIfCzOu87qNTfjLS6UYjGUka8euE2JT9Wlc92kQcvfKwV0rop7slVicI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17030136733591014.1268643759586; Tue, 19 Dec 2023 11:21:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfX6-00021Q-Lj; Tue, 19 Dec 2023 14:13:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfX4-0001zb-4S for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:34 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfWy-0001sX-Sp for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:32 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-33660cf2296so3956139f8f.3 for ; Tue, 19 Dec 2023 11:13:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013207; x=1703618007; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0gBHCNexdbG+zEv+b4Ytrqor1JdvLFRCIBJ8HsM7maA=; b=xLsc6S/akiQ/dmQtKHUjcn4qHhHW3FjifaO2eaS4zaocJOm8bWj/oT7+Ogz3Zz2qi0 mm6CddeSsJr3u2tCn3Ne8XHOWTKs5UnPJ5JmRsXLIdINK2LAA1BGgCcK2nL8JwS7S8Q8 bxkISKoeAogZjTD2GthMzMElQzDPZFjvPM44fcnu8Y7k0/wddvcwyjeYyzNTxKNIQMiF z1gAYKfU1P+kMVeJyt3aeVPQXmuSi1DYUMdsjUiNeHcBfRuWiiBqELkZFniB95MzkdGL LWsi2xYPPEBLHGPMizw/7R7dsssfQ+ShWaOnXAtuKwYgVfEJ8Z3iNPa5qMCSvOnCfqOT FZoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013207; x=1703618007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0gBHCNexdbG+zEv+b4Ytrqor1JdvLFRCIBJ8HsM7maA=; b=H7f4CbNoewuoQbcV4zPwS2D47CpyTlU9RtF44QXaAuqwKB1igozjTLmQuZSRgT4xwQ JL6YORyYcqLmoipfqoeyaq6CIZZlSgRP9xLhx1kCLVMlnTUKzFH+qIjMCFClqMhWn7sS OO7Sjw+gYsnCNFFpW4pJGLMNSDkk0Yc0TC1i9PUz4wWFk9yDfOIIoAJmzwt3J1Pw1ZtR bFFaFs2r7xMOP2TZ6Jdl4MBziPJcKSMjm4EAcuRKBiLeP1uHZUEk+02q8wkG7O573VM6 neNmXhXc6tWdVOyYiEWmQ1Dcry+LVK/baOvNwITLu0m+2GA43YCRVl2y9fwsSwpNZoBV 85NQ== X-Gm-Message-State: AOJu0Yx/2vW8rpHw+2qoY1bfV0t4YKH2QKknFnv3C17xHwlx3Uul2V1m yJNIlhj/vg19P1/jGTRP1HtuQ++DNR/9INZcuHk= X-Google-Smtp-Source: AGHT+IHF536noumzaQyVsy1+bksZIMp16F47IX/DvFW1Km/8kz7wHqERIRQv0cVqMaVWzSWSkf0sJg== X-Received: by 2002:adf:f5c6:0:b0:336:7197:56e6 with SMTP id k6-20020adff5c6000000b00336719756e6mr1149861wrp.136.1703013207615; Tue, 19 Dec 2023 11:13:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/43] target/arm: Don't implement *32_EL2 registers when EL1 is AArch64 only Date: Tue, 19 Dec 2023 19:13:02 +0000 Message-Id: <20231219191307.2895919-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013675345100007 Content-Type: text/plain; charset="utf-8" The system registers DBGVCR32_EL2, FPEXC32_EL2, DACR32_EL2 and IFSR32_EL2 are present only to allow an AArch64 EL2 or EL3 to read and write the contents of an AArch32-only system register. The architecture requires that they are present only when EL1 can be AArch32, but we implement them unconditionally. This was OK when all our CPUs supported AArch32 EL1, but we have quite a lot of CPU models now which only support AArch64 at EL1: a64fx cortex-a76 cortex-a710 neoverse-n1 neoverse-n2 neoverse-v1 Only define these registers for CPUs which allow AArch32 EL1. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20231121144605.3980419-1-peter.maydell@linaro.org --- target/arm/debug_helper.c | 23 +++++++++++++++-------- target/arm/helper.c | 35 +++++++++++++++++++++-------------- 2 files changed, 36 insertions(+), 22 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index cbfba532f50..83d2619080f 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -1026,14 +1026,6 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tda, .type =3D ARM_CP_NOP }, - /* - * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor - * to save and restore a 32-bit guest's DBGVCR) - */ - { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, /* * Dummy MDCCINT_EL1, since we don't implement the Debug Communications * Channel but Linux may try to access this register. The 32-bit @@ -1062,6 +1054,18 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.dbgclaim) }, }; =20 +/* These are present only when EL1 supports AArch32 */ +static const ARMCPRegInfo debug_aa32_el1_reginfo[] =3D { + /* + * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor + * to save and restore a 32-bit guest's DBGVCR) + */ + { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, +}; + static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { /* 64 bit access versions of the (dummy) debug registers */ { .name =3D "DBGDRAR", .cp =3D 14, .crm =3D 1, .opc1 =3D 0, @@ -1207,6 +1211,9 @@ void define_debug_regs(ARMCPU *cpu) assert(ctx_cmps <=3D brps); =20 define_arm_cp_regs(cpu, debug_cp_reginfo); + if (cpu_isar_feature(aa64_aa32_el1, cpu)) { + define_arm_cp_regs(cpu, debug_aa32_el1_reginfo); + } =20 if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); diff --git a/target/arm/helper.c b/target/arm/helper.c index 2746d3fdac8..39830c7f948 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5698,20 +5698,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 0, .type =3D ARM_CP_NO_RAW, .access =3D PL1_RW, .readfn =3D spsel_read, .writefn =3D spsel_write= }, - { .name =3D "FPEXC32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, - .type =3D ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, - .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, - { .name =3D "DACR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, - .writefn =3D dacr_write, .raw_writefn =3D raw_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.dacr32_el2) }, - { .name =3D "IFSR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, - .fieldoffset =3D offsetof(CPUARMState, cp15.ifsr32_el2) }, { .name =3D "SPSR_IRQ", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 0, @@ -5746,6 +5732,24 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, }; =20 +/* These are present only when EL1 supports AArch32 */ +static const ARMCPRegInfo v8_aa32_el1_reginfo[] =3D { + { .name =3D "FPEXC32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, + .type =3D ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, + .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, + { .name =3D "DACR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, + .writefn =3D dacr_write, .raw_writefn =3D raw_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.dacr32_el2) }, + { .name =3D "IFSR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, + .fieldoffset =3D offsetof(CPUARMState, cp15.ifsr32_el2) }, +}; + static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) { ARMCPU *cpu =3D env_archcpu(env); @@ -8716,6 +8720,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) } define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); + if (cpu_isar_feature(aa64_aa32_el1, cpu)) { + define_arm_cp_regs(cpu, v8_aa32_el1_reginfo); + } =20 for (i =3D 4; i < 16; i++) { /* --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013478; cv=none; d=zohomail.com; s=zohoarc; b=H59tCfmL2MJn3ZU040sLYlydJJ1xIZj6ebLgMDsjxLHjnrpwb04Z45uhIvb4X6VspBy8J3BLgdINwZUT9e/wN/JyHUS2Q5KrW8UUenJ+SdMGETVh2v6xP272+Isu0lingtSAxQc/u9hYdBeZL7wd50x79UoINzGK3UuiIEiWfWo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013478; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013478954100004 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20231130142519.28417-2-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 55 -------------------------------------- target/arm/tcg/op_helper.c | 55 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 55 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 39830c7f948..5d4796b99a8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10142,61 +10142,6 @@ void cpsr_write(CPUARMState *env, uint32_t val, ui= nt32_t mask, } } =20 -/* Sign/zero extend */ -uint32_t HELPER(sxtb16)(uint32_t x) -{ - uint32_t res; - res =3D (uint16_t)(int8_t)x; - res |=3D (uint32_t)(int8_t)(x >> 16) << 16; - return res; -} - -static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) -{ - /* - * Take a division-by-zero exception if necessary; otherwise return - * to get the usual non-trapping division behaviour (result of 0) - */ - if (arm_feature(env, ARM_FEATURE_M) - && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { - raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); - } -} - -uint32_t HELPER(uxtb16)(uint32_t x) -{ - uint32_t res; - res =3D (uint16_t)(uint8_t)x; - res |=3D (uint32_t)(uint8_t)(x >> 16) << 16; - return res; -} - -int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) -{ - if (den =3D=3D 0) { - handle_possible_div0_trap(env, GETPC()); - return 0; - } - if (num =3D=3D INT_MIN && den =3D=3D -1) { - return INT_MIN; - } - return num / den; -} - -uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) -{ - if (den =3D=3D 0) { - handle_possible_div0_trap(env, GETPC()); - return 0; - } - return num / den; -} - -uint32_t HELPER(rbit)(uint32_t x) -{ - return revbit32(x); -} - #ifdef CONFIG_USER_ONLY =20 static void switch_mode(CPUARMState *env, int mode) diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index ea08936a852..9de0fa2d1f6 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -121,6 +121,61 @@ void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t= newvalue) } } =20 +/* Sign/zero extend */ +uint32_t HELPER(sxtb16)(uint32_t x) +{ + uint32_t res; + res =3D (uint16_t)(int8_t)x; + res |=3D (uint32_t)(int8_t)(x >> 16) << 16; + return res; +} + +static void handle_possible_div0_trap(CPUARMState *env, uintptr_t ra) +{ + /* + * Take a division-by-zero exception if necessary; otherwise return + * to get the usual non-trapping division behaviour (result of 0) + */ + if (arm_feature(env, ARM_FEATURE_M) + && (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_DIV_0_TRP_MASK)) { + raise_exception_ra(env, EXCP_DIVBYZERO, 0, 1, ra); + } +} + +uint32_t HELPER(uxtb16)(uint32_t x) +{ + uint32_t res; + res =3D (uint16_t)(uint8_t)x; + res |=3D (uint32_t)(uint8_t)(x >> 16) << 16; + return res; +} + +int32_t HELPER(sdiv)(CPUARMState *env, int32_t num, int32_t den) +{ + if (den =3D=3D 0) { + handle_possible_div0_trap(env, GETPC()); + return 0; + } + if (num =3D=3D INT_MIN && den =3D=3D -1) { + return INT_MIN; + } + return num / den; +} + +uint32_t HELPER(udiv)(CPUARMState *env, uint32_t num, uint32_t den) +{ + if (den =3D=3D 0) { + handle_possible_div0_trap(env, GETPC()); + return 0; + } + return num / den; +} + +uint32_t HELPER(rbit)(uint32_t x) +{ + return revbit32(x); +} + uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) { uint32_t res =3D a + b; --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013208; x=1703618008; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fBX5Bcn92Yspk1CoRgrc8XvrSCWWIJ0mbmpizqjvfLY=; b=o/AL22yb0h1EZlujE9C0HUaob0nV4nemiYukGgaODdQ74by3WZy5/jWV+2Nv0T9d24 pSla52UmPLgY4eR+kPw4iOIROvsXVJvOjDmKGmtCFWqPz0wmMpUhv690F1xbkgRLCweP sg0tlcqytSzD2HldUNsQMxN+BZbusSPD8sJThwN2/WlbmtBLprO62/cRyR+2+TKU2m9f XRWtH8sCuTwchpSIHKsSSv+Y/YVqp066yPIe9XFtmouBgHu0Ss+AKpKOpCQUb3rR9R6G Ybn2JYmKH4wYAQvkynHpA1a/ldBhQ1h8HR1at1LrouoU7jwzEtEeMoIsizfpKaHEHBMX /9lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013208; x=1703618008; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fBX5Bcn92Yspk1CoRgrc8XvrSCWWIJ0mbmpizqjvfLY=; b=agR2qb5nE8JT4cgK6Z/If+vUAJF0TKsRlj/i8jiBg/GIX7HgHgzdMZtB0UotO0GqsW R7XLuPTM6sC/qTrjzQ7hJCJ0f2IVBkFH0wPKqZeoHK1sfUXvCnOOOMgp1g3Q76m09k2I 2HdgUv5JD0eoAKbH4zTO7+XnfbkKqOcV/BNKbxdKyrOBhHXRGuXGHxlZwp9rtGQqxDgH GhGKaLM8Qs9ey3eQWH3hRG+0kknWBrPI9P8RKn2EDygLpYzFSq5mlvx3OPBALtnlYoEc Uk5CpV/XbXyCT+GZiuhRY04JZLRsTQOBx5NScwfPokRGMPD6pXO8MIJNUlIhwUoHB7WN J+pg== X-Gm-Message-State: AOJu0Yzl2A0+AVdzYfpZ4/t4/+MqtIF1cRxKJdyFe0rz40xuYPYo0nrk pCU5FI7KpmaEA/knvsOULBwcC/TWa4wei1Pji1Y= X-Google-Smtp-Source: AGHT+IG6i/CYPCMSV0gsU4pjKCPU12SWAOHq7qXYP+fHj8Kk25UMGcqsYsg5kXwgmPA3fRW98IVzNg== X-Received: by 2002:a05:600c:3581:b0:40d:2853:8204 with SMTP id p1-20020a05600c358100b0040d28538204mr721917wmq.166.1703013208584; Tue, 19 Dec 2023 11:13:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/43] target/arm: Restrict DC CVAP & DC CVADP instructions to TCG accel Date: Tue, 19 Dec 2023 19:13:04 +0000 Message-Id: <20231219191307.2895919-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013327464100005 From: Philippe Mathieu-Daud=C3=A9 Hardware accelerators handle that in *hardware*. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20231130142519.28417-3-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5d4796b99a8..436a43a4b7b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7649,6 +7649,7 @@ static const ARMCPRegInfo rndr_reginfo[] =3D { static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, uint64_t value) { +#ifdef CONFIG_TCG ARMCPU *cpu =3D env_archcpu(env); /* CTR_EL0 System register -> DminLine, bits [19:16] */ uint64_t dline_size =3D 4 << ((cpu->ctr >> 16) & 0xF); @@ -7673,6 +7674,10 @@ static void dccvap_writefn(CPUARMState *env, const A= RMCPRegInfo *opaque, } #endif /*CONFIG_USER_ONLY*/ } +#else + /* Handled by hardware accelerator. */ + g_assert_not_reached(); +#endif /* CONFIG_TCG */ } =20 static const ARMCPRegInfo dcpop_reg[] =3D { --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013457; cv=none; d=zohomail.com; s=zohoarc; b=cvwFrw+OnCNHnYBVuzsjlZzTEG6FxbYzOdv8cKjOJIW0G+tZoRD9PXn5WSaLXJz9ZDD8b3L4Hq+FqOVgtYHaeIv1hgscvOPJxHDxJl9iKq1zSbXaDHul8xADw8XgPK46bWLFr4qr0eaHxHDkeUOuO7F5xf8rqOEf4H8NzXnfIgY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013457; h=Content-Type:Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=0NHBQEa3FZkeVazUjrvD8hJIhg1weYMkC8vKZ2fiVRE=; b=IYiCaiMkxQDcI0gzdMBNiKXB+Z/6WfclVYF5jJU7e/V+D3p8fCrr+Y3d4q824U5XT38yBvEcM5GlozVXOYcV3ZkAtr/h3RlrsfksbIH1FUIloa+ZjgBq+1FX+GDTQzYqhhzxhDtAf0jdwRhh7XakwswONzHGQnHWqLh77Ld3x8U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013457986479.2121138779397; Tue, 19 Dec 2023 11:17:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfXF-00024J-8m; Tue, 19 Dec 2023 14:13:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfX5-00020s-MS for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:35 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfX3-0001t4-PQ for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:35 -0500 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-33671384e50so1164622f8f.0 for ; Tue, 19 Dec 2023 11:13:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013209; x=1703618009; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=0NHBQEa3FZkeVazUjrvD8hJIhg1weYMkC8vKZ2fiVRE=; b=Uib49gWLdb3vfuqC1OgxGc9qf1gdwR5yZM0+LnQIYiNajlGzLrgcbR1wmvgwlUCHzd mtrAAI7eyBypJ1kTagNB8tqEmit+230lxwFQzF5Cbp7ampuU2P6JdWg5IOYg38iFazyI acn6IU943hGiy0k1dn9I1gr+1sG7CccPmEnEkQKsWqpvvf3Va/zuhg4k0gr2SPZBNAg3 /0bTmScO3ltRoCgytMR1v1/yjNOwFNCZyhztP+uvgX7rxfnPmx/KJUIRAH3ZxflVY5r6 SV+9NLHtYUOqdfLTuBiih+4xzn1WNCflOHVI3DXvdwqEtFEi7QFL2xSvZhMMl26kymQU B0Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013209; x=1703618009; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_SPACE_RATIO=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013459918100007 From: Philippe Mathieu-Daud=C3=A9 translate_insn() ends up calling probe_access_full(), itself declared in "exec/exec-all.h": TranslatorOps::translate_insn -> aarch64_tr_translate_insn() -> is_guarded_page() -> probe_access_full() Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20231130142519.28417-4-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a2e49c39f9f..f3b5b9124d0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" =20 +#include "exec/exec-all.h" #include "translate.h" #include "translate-a64.h" #include "qemu/log.h" --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f5-20020a5d5685000000b0033657376b62sm12007754wrv.105.2023.12.19.11.13.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 11:13:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1703013209; x=1703618009; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/gf8/3mTDB0itjVLwlHBVzUhArBcmJcd155HpJsvLVw=; b=GL/Mvyql0n+t3AVzfBeIMaq68s4jsXYvGxyiDQWgjW85rqKvmJpeHODVt4WRtiBG07 CO3cUnoHNVGpqumxW8mPLMqncVTrPj8E0ra6976aU/zHMqfckL+Qas92SXJKbFRHMDRR VK7Uj29MW8Id3ptNxMwBQH8/f74EdqfUc8/Hib3Mlla2vDwAeUpcrq4UnpN8FOVg3chc QZUP2zCseU/gLLf8a+aInD/6diBak6qefV17oHKBwnhjGfDIVpPSFII5G61r/47OOruZ I+8yz3zpaw9YjT7wrhRL9z8rmAjv3qTQwS3n/sxE1Wo3RrBh8XfVVgfwi6+TNbEO1kue ElVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703013209; x=1703618009; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/gf8/3mTDB0itjVLwlHBVzUhArBcmJcd155HpJsvLVw=; b=TwWVRynNKHRWZiis+P2NK2haXqLyVvXJuYACruCxPcoizJtUtfxcbHObm+Oruwb4hb dTHYTMwxl8GBBGZ0Luj2fCbQpmyxn/SduNFkwjUoBpnkO+iweJ6cHjUt8xKfoA33nlpu ei/L2E5ZWJ8/5xS1wIlOR+TuC5MgqwxBHBkpLqPFnftlGtt92t5BGtniQnO4HHaw7yUM Vf8h+KTP/VJqr1qoPPHrelIgErQG68qyK1TZ5BGeHnEFMAlC45bUJwdLTkQ8DAfxsFXb Fb4eb7+QvQYDCXu13/CnGuf8XJp9H9+7IdosrTlu5iwVLNMWWC/kr/1UKK1boL89EPVN 3FGQ== X-Gm-Message-State: AOJu0Yy8kY3a8na8BDYR5KeA1tjD/utZYV9z/EPDPco+guKv8MP0i99X TfSP8KiWnzHf+p+nDBtwqp2vdXYgeBJcBH5S3ao= X-Google-Smtp-Source: AGHT+IHHdECr/lMfo0tqbfiYh0DPweVnrowQRPvmE9SeDFG/qtELchrokRdbZ5pGRtiIc9n2nrvZPw== X-Received: by 2002:a5d:5445:0:b0:336:5496:b5e6 with SMTP id w5-20020a5d5445000000b003365496b5e6mr3129483wrv.123.1703013209466; Tue, 19 Dec 2023 11:13:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/43] target/arm/helper: Propagate MDCR_EL2.HPMN into PMCR_EL0.N Date: Tue, 19 Dec 2023 19:13:06 +0000 Message-Id: <20231219191307.2895919-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231219191307.2895919-1-peter.maydell@linaro.org> References: <20231219191307.2895919-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013469976100001 Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker MDCR_EL2.HPMN allows an hypervisor to limit the number of PMU counters available to EL1 and EL0 (to keep the others to itself). QEMU already implements this split correctly, except for PMCR_EL0.N reads: the number of counters read by EL1 or EL0 should be the one configured in MDCR_EL2.HPMN. Cc: qemu-stable@nongnu.org Signed-off-by: Jean-Philippe Brucker Message-id: 20231215144652.4193815-2-jean-philippe@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 436a43a4b7b..fc546df5c70 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1475,6 +1475,22 @@ static void pmcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, pmu_op_finish(env); } =20 +static uint64_t pmcr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t pmcr =3D env->cp15.c9_pmcr; + + /* + * If EL2 is implemented and enabled for the current security state, r= eads + * of PMCR.N from EL1 or EL0 return the value of MDCR_EL2.HPMN or HDCR= .HPMN. + */ + if (arm_current_el(env) <=3D 1 && arm_is_el2_enabled(env)) { + pmcr &=3D ~PMCRN_MASK; + pmcr |=3D (env->cp15.mdcr_el2 & MDCR_HPMN) << PMCRN_SHIFT; + } + + return pmcr; +} + static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -7158,8 +7174,9 @@ static void define_pmu_regs(ARMCPU *cpu) .fgt =3D FGT_PMCR_EL0, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), - .accessfn =3D pmreg_access, .writefn =3D pmcr_write, - .raw_writefn =3D raw_write, + .accessfn =3D pmreg_access, + .readfn =3D pmcr_read, .raw_readfn =3D raw_read, + .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; ARMCPRegInfo pmcr64 =3D { .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, @@ -7169,6 +7186,7 @@ static void define_pmu_regs(ARMCPU *cpu) .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), .resetvalue =3D cpu->isar.reset_pmcr_el0, + .readfn =3D pmcr_read, .raw_readfn =3D raw_read, .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; =20 --=20 2.34.1 From nobody Tue Nov 26 22:23:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1703013661; cv=none; d=zohomail.com; s=zohoarc; b=VrSPyvzuD9mE4BRkHNn/5GGZgZbsWigE8Jtw60FZHJNRD5qvglds7PxkJYDDHRf59rZrSJzKAdNtyhYD/JMpqsLERLhcN317Da2vGfRIgnQ0MDxEq6ZDhONvnZeGOjBY+wO8ga9rVtrd1mRXgpnSQJbajN1JDJicqC9lbEKME6U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703013661; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=00hMtN5BXevzRJATDfX8VsM5S59s6M4RCIFrJXcR5Q4=; b=KQHbCvgAoxtnvUtc80BJxcANg2oXmYbmNO/sR8FlkltT3rNjKVlKORL7PxXGDhs25+4zwWETbL4eGCSBk/N0Wwj5nFgwx+/k+AfsgJZXLMLbRmPy1UtDbaK3pKZvGH7zQAskNlnvPVlWHEDD+ehTFHPJ3PvyOTZB60FgFe0SxhU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1703013660933784.0485240952141; Tue, 19 Dec 2023 11:21:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFfXH-00025J-CH; Tue, 19 Dec 2023 14:13:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFfX7-00021v-1t for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:37 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rFfX3-0001tV-PF for qemu-devel@nongnu.org; Tue, 19 Dec 2023 14:13:36 -0500 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-336695c4317so2493984f8f.3 for ; Tue, 19 Dec 2023 11:13:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1703013661298100002 Content-Type: text/plain; charset="utf-8" From: Nikita Ostrenkov Signed-off-by: Nikita Ostrenkov Message-id: 20231216133408.2884-1-n.ostrenkov@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/misc/imx7_snvs.h | 7 ++- hw/misc/imx7_snvs.c | 93 ++++++++++++++++++++++++++++++++++--- hw/misc/trace-events | 4 +- 3 files changed, 94 insertions(+), 10 deletions(-) diff --git a/include/hw/misc/imx7_snvs.h b/include/hw/misc/imx7_snvs.h index 14a1d6fe6b0..1272076086a 100644 --- a/include/hw/misc/imx7_snvs.h +++ b/include/hw/misc/imx7_snvs.h @@ -20,7 +20,9 @@ enum IMX7SNVSRegisters { SNVS_LPCR =3D 0x38, SNVS_LPCR_TOP =3D BIT(6), - SNVS_LPCR_DP_EN =3D BIT(5) + SNVS_LPCR_DP_EN =3D BIT(5), + SNVS_LPSRTCMR =3D 0x050, /* Secure Real Time Counter MSB Register */ + SNVS_LPSRTCLR =3D 0x054, /* Secure Real Time Counter LSB Register */ }; =20 #define TYPE_IMX7_SNVS "imx7.snvs" @@ -31,6 +33,9 @@ struct IMX7SNVSState { SysBusDevice parent_obj; =20 MemoryRegion mmio; + + uint64_t tick_offset; + uint64_t lpcr; }; =20 #endif /* IMX7_SNVS_H */ diff --git a/hw/misc/imx7_snvs.c b/hw/misc/imx7_snvs.c index a245f96cd4e..8e7f43187f6 100644 --- a/hw/misc/imx7_snvs.c +++ b/hw/misc/imx7_snvs.c @@ -13,28 +13,100 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qemu/timer.h" +#include "migration/vmstate.h" #include "hw/misc/imx7_snvs.h" +#include "qemu/cutils.h" #include "qemu/module.h" +#include "sysemu/sysemu.h" +#include "sysemu/rtc.h" #include "sysemu/runstate.h" #include "trace.h" =20 +#define RTC_FREQ 32768ULL + +static const VMStateDescription vmstate_imx7_snvs =3D { + .name =3D TYPE_IMX7_SNVS, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(tick_offset, IMX7SNVSState), + VMSTATE_UINT64(lpcr, IMX7SNVSState), + VMSTATE_END_OF_LIST() + } +}; + +static uint64_t imx7_snvs_get_count(IMX7SNVSState *s) +{ + uint64_t ticks =3D muldiv64(qemu_clock_get_ns(rtc_clock), RTC_FREQ, + NANOSECONDS_PER_SECOND); + return s->tick_offset + ticks; +} + static uint64_t imx7_snvs_read(void *opaque, hwaddr offset, unsigned size) { - trace_imx7_snvs_read(offset, 0); + IMX7SNVSState *s =3D IMX7_SNVS(opaque); + uint64_t ret =3D 0; =20 - return 0; + switch (offset) { + case SNVS_LPSRTCMR: + ret =3D extract64(imx7_snvs_get_count(s), 32, 15); + break; + case SNVS_LPSRTCLR: + ret =3D extract64(imx7_snvs_get_count(s), 0, 32); + break; + case SNVS_LPCR: + ret =3D s->lpcr; + break; + } + + trace_imx7_snvs_read(offset, ret, size); + + return ret; +} + +static void imx7_snvs_reset(DeviceState *dev) +{ + IMX7SNVSState *s =3D IMX7_SNVS(dev); + + s->lpcr =3D 0; } =20 static void imx7_snvs_write(void *opaque, hwaddr offset, uint64_t v, unsigned size) { - const uint32_t value =3D v; - const uint32_t mask =3D SNVS_LPCR_TOP | SNVS_LPCR_DP_EN; + trace_imx7_snvs_write(offset, v, size); =20 - trace_imx7_snvs_write(offset, value); + IMX7SNVSState *s =3D IMX7_SNVS(opaque); =20 - if (offset =3D=3D SNVS_LPCR && ((value & mask) =3D=3D mask)) { - qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + uint64_t new_value =3D 0, snvs_count =3D 0; + + if (offset =3D=3D SNVS_LPSRTCMR || offset =3D=3D SNVS_LPSRTCLR) { + snvs_count =3D imx7_snvs_get_count(s); + } + + switch (offset) { + case SNVS_LPSRTCMR: + new_value =3D deposit64(snvs_count, 32, 32, v); + break; + case SNVS_LPSRTCLR: + new_value =3D deposit64(snvs_count, 0, 32, v); + break; + case SNVS_LPCR: { + s->lpcr =3D v; + + const uint32_t mask =3D SNVS_LPCR_TOP | SNVS_LPCR_DP_EN; + + if ((v & mask) =3D=3D mask) { + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } + break; + } + } + + if (offset =3D=3D SNVS_LPSRTCMR || offset =3D=3D SNVS_LPSRTCLR) { + s->tick_offset +=3D new_value - snvs_count; } } =20 @@ -59,17 +131,24 @@ static void imx7_snvs_init(Object *obj) { SysBusDevice *sd =3D SYS_BUS_DEVICE(obj); IMX7SNVSState *s =3D IMX7_SNVS(obj); + struct tm tm; =20 memory_region_init_io(&s->mmio, obj, &imx7_snvs_ops, s, TYPE_IMX7_SNVS, 0x1000); =20 sysbus_init_mmio(sd, &s->mmio); + + qemu_get_timedate(&tm, 0); + s->tick_offset =3D mktimegm(&tm) - + qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; } =20 static void imx7_snvs_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->reset =3D imx7_snvs_reset; + dc->vmsd =3D &vmstate_imx7_snvs; dc->desc =3D "i.MX7 Secure Non-Volatile Storage Module"; } =20 diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 05ff692441b..85725506bff 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -116,8 +116,8 @@ imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64 imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value= 0x%08" PRIx64 =20 # imx7_snvs.c -imx7_snvs_read(uint64_t offset, uint32_t value) "addr 0x%08" PRIx64 "value= 0x%08" PRIx32 -imx7_snvs_write(uint64_t offset, uint32_t value) "addr 0x%08" PRIx64 "valu= e 0x%08" PRIx32 +imx7_snvs_read(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS = read: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" +imx7_snvs_write(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS= write: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" =20 # mos6522.c mos6522_set_counter(int index, unsigned int val) "T%d.counter=3D%d" --=20 2.34.1