From nobody Tue Nov 26 22:15:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1702989272; cv=none; d=zohomail.com; s=zohoarc; b=EsjTFUc5rbxn67cofHhXh371ZyFES/jFNxH0Tuq/N7+PBeDtMqBN9MSGMcIu3AwdXdQlO3oRb9KeHwgQRh6NyTYPBm86AhOdgiwrOK+woTPOseekMHSMqvIaaKJRayqKByjebWbcDxZvJrvUBS+Y2XIOnGD+NC+qE9MVW/uSwyg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1702989272; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:Sender:Subject:Subject:To:To:Message-Id; bh=5GgcSWG9rW+D3aM4GCUAqgEXlMQ40tSWRc/IUIwkSf0=; b=LAQpG1y4SeoXK5ylRK1aZ9YsrGDM3y/uIFV9F2C90yCORqlQIQ5Hg/Kt9GquPjq/H1oe5KHA+UxyvaY3iwNTSdLOX8iuwslKWaPSmevNjFrPsT9oHcqyrCxF0HfR3PRNJna9kZA4JsswjkEXeE42vghJ1P9H7vN0ptiSWc1AqMc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1702989272427267.5945182805958; Tue, 19 Dec 2023 04:34:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rFZHn-000207-7t; Tue, 19 Dec 2023 07:33:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFZHk-0001zU-30 for qemu-devel@nongnu.org; Tue, 19 Dec 2023 07:33:20 -0500 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rFZHi-00038a-5X for qemu-devel@nongnu.org; Tue, 19 Dec 2023 07:33:19 -0500 Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BJCWnbx055594; Tue, 19 Dec 2023 20:32:49 +0800 (+08) (envelope-from alvinga@andestech.com) Received: from alvinga-VirtualBox.andestech.com (10.0.13.65) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Tue, 19 Dec 2023 20:32:49 +0800 To: , CC: , , , , , Alvin Chang Subject: [PATCH v2] target/riscv: Implement optional CSR mcontext of debug Sdtrig extension Date: Tue, 19 Dec 2023 20:32:44 +0800 Message-ID: <20231219123244.290935-1-alvinga@andestech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.13.65] X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3BJCWnbx055594 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=alvinga@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RDNS_DYNAMIC=0.982, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, TVD_RCVD_IP=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Alvin Chang From: Alvin Chang via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1702989274009100001 Content-Type: text/plain; charset="utf-8" The debug Sdtrig extension defines an CSR "mcontext". This commit implements its predicate and read/write operations into CSR table. Its value is reset as 0 when the trigger module is reset. Signed-off-by: Alvin Chang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- Changes from v1: Remove dedicated cfg, always implement mcontext. target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 7 +++++++ target/riscv/csr.c | 36 +++++++++++++++++++++++++++++++----- target/riscv/debug.c | 2 ++ 4 files changed, 41 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361..e117641 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -345,6 +345,7 @@ struct CPUArchState { target_ulong tdata1[RV_MAX_TRIGGERS]; target_ulong tdata2[RV_MAX_TRIGGERS]; target_ulong tdata3[RV_MAX_TRIGGERS]; + target_ulong mcontext; struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ebd7917..3296648 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -361,6 +361,7 @@ #define CSR_TDATA2 0x7a2 #define CSR_TDATA3 0x7a3 #define CSR_TINFO 0x7a4 +#define CSR_MCONTEXT 0x7a8 =20 /* Debug Mode Registers */ #define CSR_DCSR 0x7b0 @@ -905,4 +906,10 @@ typedef enum RISCVException { /* JVT CSR bits */ #define JVT_MODE 0x3F #define JVT_BASE (~0x3F) + +/* Debug Sdtrig CSR masks */ +#define MCONTEXT32 0x0000003F +#define MCONTEXT64 0x0000000000001FFFULL +#define MCONTEXT32_HCONTEXT 0x0000007F +#define MCONTEXT64_HCONTEXT 0x0000000000003FFFULL #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fde7ce1..ff1e128 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3900,6 +3900,31 @@ static RISCVException read_tinfo(CPURISCVState *env,= int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mcontext(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mcontext; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mcontext(CPURISCVState *env, int csrno, + target_ulong val) +{ + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? true : false; + int32_t mask; + + if (riscv_has_ext(env, RVH)) { + /* Spec suggest 7-bit for RV32 and 14-bit for RV64 w/ H extension = */ + mask =3D rv32 ? MCONTEXT32_HCONTEXT : MCONTEXT64_HCONTEXT; + } else { + /* Spec suggest 6-bit for RV32 and 13-bit for RV64 w/o H extension= */ + mask =3D rv32 ? MCONTEXT32 : MCONTEXT64; + } + + env->mcontext =3D val & mask; + return RISCV_EXCP_NONE; +} + /* * Functions to access Pointer Masking feature registers * We have to check if current priv lvl could modify @@ -4794,11 +4819,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_PMPADDR15] =3D { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, =20 /* Debug CSRs */ - [CSR_TSELECT] =3D { "tselect", debug, read_tselect, write_tselect }, - [CSR_TDATA1] =3D { "tdata1", debug, read_tdata, write_tdata }, - [CSR_TDATA2] =3D { "tdata2", debug, read_tdata, write_tdata }, - [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata }, - [CSR_TINFO] =3D { "tinfo", debug, read_tinfo, write_ignore }, + [CSR_TSELECT] =3D { "tselect", debug, read_tselect, write_tselect= }, + [CSR_TDATA1] =3D { "tdata1", debug, read_tdata, write_tdata = }, + [CSR_TDATA2] =3D { "tdata2", debug, read_tdata, write_tdata = }, + [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata = }, + [CSR_TINFO] =3D { "tinfo", debug, read_tinfo, write_ignore = }, + [CSR_MCONTEXT] =3D { "mcontext", debug, read_mcontext, write_mcontex= t }, =20 /* User Pointer Masking */ [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write_u= mte }, diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 4945d1a..e30d99c 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -940,4 +940,6 @@ void riscv_trigger_reset_hold(CPURISCVState *env) env->cpu_watchpoint[i] =3D NULL; timer_del(env->itrigger_timer[i]); } + + env->mcontext =3D 0; } --=20 2.34.1