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([179.93.21.205]) by smtp.gmail.com with ESMTPSA id x20-20020aa793b4000000b006ce7e65159bsm2627905pff.28.2023.12.18.12.43.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 12:43:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1702932220; x=1703537020; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0doA4Frlxb1MZjlKWbeqhjICgS6mp5GR5r4hSfWPbnU=; b=m0M8luMRfk0W5YyvH5Ho9Xj9jpN7YTlkPc4v0KyLTULdswl0c5+Xd0KERvVmtl+fxE m6tGNljGaD/9ZZCCwvIlxV775JOPKMN3TYsH+jblUE0MdjN51qrPHi5HVjHRBBsQMxSu T1Rd+/+ItskkP6iLc5gEiMBvol80DJBs3Rc5I8xCvCf/d70uWOMMdGDDocogibaxhH6t fBA/oGfW/vYPSFiOA/9i7lBNKbR+NtAdB8jF+0uu9tTkaV2ZljNqeLqzZup5i+NW1JLl 3VmZNmhx6D9IgAFHzcivixljuntLyw7OB8GRH/Sw2A2upb3LovbWE6xgyIqAmoYQisTa aMpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702932220; x=1703537020; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0doA4Frlxb1MZjlKWbeqhjICgS6mp5GR5r4hSfWPbnU=; b=dleVoOak/lbFlYhmxSyOKe3AD+urIVv91fvLjXYQUU/wBrLyb5R2WQde5WluqxRxnC sRjBD/tddYxNT0WY3VLD8CiPuHC7bTjsPDtDJVA4qg04uaqEyFkobrsxvWOxMaafC+BK C2OyxGdDa4I+j2X7jrdH+N1uDdLPZgsMxZ5x0xFNhzIX0EZfpjTUpnBN61vO6jX6uv+/ n1O+gg40qwYMYE5G7rIMFQ3uGsSXePirrCXmVf5xw1SjsqZ7zxu0qAHM9w64bqZyNAmR G42QFXcUOUshkcHpQy4ezLV2v7ZwiZtNE+RBIWFetn+O+rgBK4dnYwNaZ8puObtl9g+w kCLQ== X-Gm-Message-State: AOJu0Yw/AZam9PfX+4Wf8J1Nd20GlOdtzd05eJb5+utoOG0HEyW+KAnK 7WDaq+CTiaICaoI6dTeZK8/VLdseTerKJaJVTZI= X-Google-Smtp-Source: AGHT+IFmMgf2/7fIYhujHQc/Bo1l/N96qMRLE+Q/wA2/qu/o/psc8ihKJ2sxM309UEgXZbxy2Thkyg== X-Received: by 2002:a05:6a21:6da1:b0:190:5d48:ddd9 with SMTP id wl33-20020a056a216da100b001905d48ddd9mr22050758pzb.59.1702932220027; Mon, 18 Dec 2023 12:43:40 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v2 4/4] target/riscv/kvm: add RVV and Vector CSR regs Date: Mon, 18 Dec 2023 17:43:21 -0300 Message-ID: <20231218204321.75757-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231218204321.75757-1-dbarboza@ventanamicro.com> References: <20231218204321.75757-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1702932306146100001 Content-Type: text/plain; charset="utf-8" Add support for RVV and Vector CSR KVM regs vstart, vl and vtype. Support for vregs[] requires KVM side changes and an extra reg (vlenb) and will be added later. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 74 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 0298c5dd69..dfebcc1692 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -105,6 +105,10 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, ui= nt64_t idx) =20 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) =20 +#define RISCV_VECTOR_CSR_REG(env, name) \ + kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_VECTOR, \ + KVM_REG_RISCV_VECTOR_CSR_REG(name)) + #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ do { \ int _ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ @@ -158,6 +162,7 @@ static KVMCPUConfig kvm_misa_ext_cfgs[] =3D { KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H), KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I), KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), + KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V), }; =20 static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, @@ -704,6 +709,65 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) env->kvm_timer_dirty =3D false; } =20 +static int kvm_riscv_get_regs_vector(CPUState *cs) +{ + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + target_ulong reg; + int ret =3D 0; + + if (!riscv_has_ext(env, RVV)) { + return 0; + } + + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); + if (ret) { + return ret; + } + env->vstart =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); + if (ret) { + return ret; + } + env->vl =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); + if (ret) { + return ret; + } + env->vtype =3D reg; + + return 0; +} + +static int kvm_riscv_put_regs_vector(CPUState *cs) +{ + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + target_ulong reg; + int ret =3D 0; + + if (!riscv_has_ext(env, RVV)) { + return 0; + } + + reg =3D env->vstart; + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vstart), ®); + if (ret) { + return ret; + } + + reg =3D env->vl; + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vl), ®); + if (ret) { + return ret; + } + + reg =3D env->vtype; + ret =3D kvm_set_one_reg(cs, RISCV_VECTOR_CSR_REG(env, vtype), ®); + + return ret; +} + typedef struct KVMScratchCPU { int kvmfd; int vmfd; @@ -1001,6 +1065,11 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } =20 + ret =3D kvm_riscv_get_regs_vector(cs); + if (ret) { + return ret; + } + return ret; } =20 @@ -1041,6 +1110,11 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } =20 + ret =3D kvm_riscv_put_regs_vector(cs); + if (ret) { + return ret; + } + if (KVM_PUT_RESET_STATE =3D=3D level) { RISCVCPU *cpu =3D RISCV_CPU(cs); if (cs->cpu_index =3D=3D 0) { --=20 2.43.0