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Tsirkin" , Igor Mammedov , Ani Sinha , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Anup Patel , Atish Kumar Patra , Haibo Xu , Sunil V L , Andrew Jones Subject: [PATCH v8 09/13] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT Date: Mon, 18 Dec 2023 20:32:43 +0530 Message-Id: <20231218150247.466427-10-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231218150247.466427-1-sunilvl@ventanamicro.com> References: <20231218150247.466427-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=sunilvl@ventanamicro.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1702911943045100003 Content-Type: text/plain; charset="utf-8" MMU type information is available via MMU node in RHCT. Add this node in RHCT. Signed-off-by: Sunil V L Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis Acked-by: Michael S. Tsirkin --- hw/riscv/virt-acpi-build.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 506d487ede..86c38f7c2b 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -152,6 +152,8 @@ static void build_rhct(GArray *table_data, size_t len, aligned_len; uint32_t isa_offset, num_rhct_nodes, cmo_offset =3D 0; RISCVCPU *cpu =3D &s->soc[0].harts[0]; + uint32_t mmu_offset =3D 0; + uint8_t satp_mode_max; char *isa; =20 AcpiTable table =3D { .sig =3D "RHCT", .rev =3D 1, .oem_id =3D s->oem_= id, @@ -171,6 +173,10 @@ static void build_rhct(GArray *table_data, num_rhct_nodes++; } =20 + if (cpu->cfg.satp_mode.supported !=3D 0) { + num_rhct_nodes++; + } + /* Number of RHCT nodes*/ build_append_int_noprefix(table_data, num_rhct_nodes, 4); =20 @@ -226,6 +232,26 @@ static void build_rhct(GArray *table_data, } } =20 + /* MMU node structure */ + if (cpu->cfg.satp_mode.supported !=3D 0) { + satp_mode_max =3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); + mmu_offset =3D table_data->len - table.table_offset; + build_append_int_noprefix(table_data, 2, 2); /* Type */ + build_append_int_noprefix(table_data, 8, 2); /* Length */ + build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ + build_append_int_noprefix(table_data, 0, 1); /* Reserved */ + /* MMU Type */ + if (satp_mode_max =3D=3D VM_1_10_SV57) { + build_append_int_noprefix(table_data, 2, 1); /* Sv57 */ + } else if (satp_mode_max =3D=3D VM_1_10_SV48) { + build_append_int_noprefix(table_data, 1, 1); /* Sv48 */ + } else if (satp_mode_max =3D=3D VM_1_10_SV39) { + build_append_int_noprefix(table_data, 0, 1); /* Sv39 */ + } else { + assert(1); + } + } + /* Hart Info Node */ for (int i =3D 0; i < arch_ids->len; i++) { len =3D 16; @@ -238,17 +264,25 @@ static void build_rhct(GArray *table_data, num_offsets++; } =20 + if (mmu_offset) { + len +=3D 4; + num_offsets++; + } + build_append_int_noprefix(table_data, len, 2); build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ /* Number of offsets */ build_append_int_noprefix(table_data, num_offsets, 2); build_append_int_noprefix(table_data, i, 4); /* ACPI Processor U= ID */ - /* Offsets */ build_append_int_noprefix(table_data, isa_offset, 4); if (cmo_offset) { build_append_int_noprefix(table_data, cmo_offset, 4); } + + if (mmu_offset) { + build_append_int_noprefix(table_data, mmu_offset, 4); + } } =20 acpi_table_end(linker, &table); --=20 2.39.2