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([179.93.21.205]) by smtp.gmail.com with ESMTPSA id c2-20020a170902848200b001d09c539c96sm7494897plo.229.2023.12.18.04.54.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:54:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1702904099; x=1703508899; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8U63IzMzjkWDwurEnFNMBUdg1Ag6di1ouiDAsRlbPvQ=; b=KnaXo4tzjsqqLI2JrVA+EIRerrRRoTgcqQLEv+3/N+T8cTWWYVNtH/d3cJ5sy55Wgn F9Y7kq7QrROMddFGo8OKXBo06UaIkyDMRPxy7yIPtm2ttjpjiA/eBuuTSbqeyGiQNyPv WHy9FJWHWCc6dZC9SyvmjfQftJUEAizj/0ll5hA6arxzMDQ4PbJUgcR6sIr0NecR/fLj VgH6b16ho4XBXx7xlxV3eYshTw/AGLVibeOLYJ54jzIjEy6X6djz+N4qzJEiNmDXs0zt xUjWRfn4+RUsFSj5IWtvzLwQookbiuk9ElH1tmnwtemiI5AseU2mHEWjPwJ2Jn+AlLMp Z71Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702904099; x=1703508899; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8U63IzMzjkWDwurEnFNMBUdg1Ag6di1ouiDAsRlbPvQ=; b=uUZ0BV1puZulJrINrNuVYDezplbP2EFgIh+y18kKwuwhlUMAe4W9SNco4j2WquuKP8 lGbOpUWdA+HA/d6WUDq9B1OQtBO8LBOO9w397cyTqmlayTxB2DtlZobsjPT9Rp0mlZye xUTMqRechew1kQjSVFTNDp2vyK+vZFAGYGmz7ir0DeU37aLtoNuGveBzOLOfbTyFi9TK TshToseL2ab8l8VRuSvOglg57OEZIXy0WwbKo5TrvG5Mfv221R6ODSv98DtJBw/NAQkq gsruMEaqtNaNSeTHuQkJTUfd5rzhjVBGOi2DL/ktvz03yAr/9L9aQSqPi4w8+SSWlUeD 662Q== X-Gm-Message-State: AOJu0YzcG7yV77JGxZLDBI9V54aUoWqUGYVoft050tVteca7n+1MPXuO +6QDdYPEESmjKMjnP/h0mo2XYbkfuE8bCCskL0E= X-Google-Smtp-Source: AGHT+IGTgL2Yc3xKJ6AG2j9tkh7QtC0zGciJnKUvHXY/DvRit2+VqPLm3o5fe37oJmy59WEhv7v5jA== X-Received: by 2002:a17:903:22d0:b0:1d0:6ffd:6e69 with SMTP id y16-20020a17090322d000b001d06ffd6e69mr9570450plg.97.1702904099580; Mon, 18 Dec 2023 04:54:59 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v13 24/26] target/riscv: add 'parent' in profile description Date: Mon, 18 Dec 2023 09:53:32 -0300 Message-ID: <20231218125334.37184-25-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231218125334.37184-1-dbarboza@ventanamicro.com> References: <20231218125334.37184-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1702904306561100001 Content-Type: text/plain; charset="utf-8" Certain S-mode profiles, like RVA22S64 and RVA23S64, mandate all the mandatory extensions of their respective U-mode profiles. RVA22S64 includes all mandatory extensions of RVA22U64, and the same happens with RVA23 profiles. Add a 'parent' field to allow profiles to enable other profiles. This will allow us to describe S-mode profiles by specifying their parent U-mode profile, then adding just the S-mode specific extensions. We're naming the field 'parent' to consider the possibility of other uses (e.g. a s-mode profile including a previous s-mode profile) in the future. Suggested-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 14 +++++++++++++- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6795f5da41..aa33e7a1cf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1540,6 +1540,7 @@ Property riscv_cpu_options[] =3D { * having a cfg offset) at this moment. */ static RISCVCPUProfile RVA22U64 =3D { + .parent =3D NULL, .name =3D "rva22u64", .misa_ext =3D RVI | RVM | RVA | RVF | RVD | RVC | RVU, .priv_spec =3D RISCV_PROFILE_ATTR_UNUSED, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6c5fceb5f5..44fb0a9ca8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -77,6 +77,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit); #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) =20 typedef struct riscv_cpu_profile { + struct riscv_cpu_profile *parent; const char *name; uint32_t misa_ext; bool enabled; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 152f95718b..6284d36809 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -797,7 +797,7 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu, CPURISCVState *env =3D &cpu->env; const char *warn_msg =3D "Profile %s mandates disabled extension %s"; bool send_warn =3D profile->user_set && profile->enabled; - bool profile_impl =3D true; + bool parent_enabled, profile_impl =3D true; int i; =20 #ifndef CONFIG_USER_ONLY @@ -850,6 +850,13 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu, } =20 profile->enabled =3D profile_impl; + + if (profile->parent !=3D NULL) { + parent_enabled =3D object_property_get_bool(OBJECT(cpu), + profile->parent->name, + NULL); + profile->enabled =3D profile->enabled && parent_enabled; + } } =20 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) @@ -1107,6 +1114,11 @@ static void cpu_set_profile(Object *obj, Visitor *v,= const char *name, profile->user_set =3D true; profile->enabled =3D value; =20 + if (profile->parent !=3D NULL) { + object_property_set_bool(obj, profile->parent->name, + profile->enabled, NULL); + } + if (profile->enabled) { cpu->env.priv_ver =3D profile->priv_spec; } --=20 2.43.0