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([179.93.21.205]) by smtp.gmail.com with ESMTPSA id c2-20020a170902848200b001d09c539c96sm7494897plo.229.2023.12.18.04.53.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:53:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1702904029; x=1703508829; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j6t5xAuPx1bV0YGIDJjgNIDlvxYVT5pIurR1k6u3RqA=; b=m770ugV/9bUxqTl5XPP4/e+CWJE3uJhgJzg4usOnNnajzqnV4P4BV2BjKuam9wnXQS N8sLC0YBVUfir6JNRh86lOgc/jtC8UVCgGDEiPFaK4JZzp7LVmn7ht7KvCmexSZuJLfa ZOP5vBqfiYFpMnAZimevy4ec2XFapnZHQ1EhENob36V37H20KkxE79FgSOboNDahTosU +lun3qdxWi9fq9693pKUzQUWw+o79aWWy8uPZSvd5AollykV4CHF8lbr8sLV9gEwMIub kUz0eLrIXx3SMBLUH95aIdnYxmH5sSvbSeA0LDTbHAxoU8GHCdHeo380tJwcr5nvZldF 1iaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702904029; x=1703508829; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j6t5xAuPx1bV0YGIDJjgNIDlvxYVT5pIurR1k6u3RqA=; b=IkFlloUPyYeJpaSkrGvrlWSFVZnaFpSyTQjAlb0K12cfzFeGL6H/v9PRlTK6GlycHx qLH6p+k2Vm6S7GBWRJFuZtTJ8NUXJPJnonRkDUPJV4dPBMsAaX2L1i2fEpzduUJD9t+5 /tu+cQDrxgZqETrpyhSGOh9gNNPOszJkH5AoAYrf97RmAnW52EtwG+HeAfuRdp/XlXpi M4K8BP1UTVeOEAhBwdSu2xvfBtsZ2z/xvYaPOO/7bPvKYqfx3rwFtCcdIsQez5glo+Y/ mz7fWEeSlQuNCyQOydXP69BYakqxePTwIiUytbp9l8rUTjbfwdNrG94gdDFtm/zzJ6GG ZBMg== X-Gm-Message-State: AOJu0YxifIEwMd8VbsRNl/1f1wb95GVWNoLVm9+Gev87Fypiiuo7BlNq 3mFJx9qKXU9sk+W1B/EYqQ72J4v57zCgvlW/Ceo= X-Google-Smtp-Source: AGHT+IFUHwm59VgG2IfJXd/4HZpsa8tMvs8WeYNCjJEoIwLMTflx8yqiC1kTl3yKm7qGbcD796RjwQ== X-Received: by 2002:a17:902:da90:b0:1d3:adef:a49d with SMTP id j16-20020a170902da9000b001d3adefa49dmr764322plx.117.1702904029426; Mon, 18 Dec 2023 04:53:49 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v13 01/26] target/riscv: create TYPE_RISCV_VENDOR_CPU Date: Mon, 18 Dec 2023 09:53:09 -0300 Message-ID: <20231218125334.37184-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231218125334.37184-1-dbarboza@ventanamicro.com> References: <20231218125334.37184-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1702904461511100001 Content-Type: text/plain; charset="utf-8" We want to add a new CPU type for bare CPUs that will inherit specific traits of the 2 existing types: - it will allow for extensions to be enabled/disabled, like generic CPUs; - it will NOT inherit defaults, like vendor CPUs. We can make this conditions met by adding an explicit type for the existing vendor CPUs and change the existing logic to not imply that "not generic" means vendor CPUs. Let's add the "vendor" CPU type first. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 30 +++++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 91b3361dec..ca7dd509e3 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -23,6 +23,7 @@ =20 #define TYPE_RISCV_CPU "riscv-cpu" #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" +#define TYPE_RISCV_VENDOR_CPU "riscv-vendor-cpu" =20 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 70bf10aa7c..bb91bcacee 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1778,6 +1778,13 @@ void riscv_cpu_list(void) .instance_init =3D initfn \ } =20 +#define DEFINE_VENDOR_CPU(type_name, initfn) \ + { \ + .name =3D type_name, \ + .parent =3D TYPE_RISCV_VENDOR_CPU, \ + .instance_init =3D initfn \ + } + static const TypeInfo riscv_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU, @@ -1795,21 +1802,26 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .parent =3D TYPE_RISCV_CPU, .abstract =3D true, }, + { + .name =3D TYPE_RISCV_VENDOR_CPU, + .parent =3D TYPE_RISCV_CPU, + .abstract =3D true, + }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_in= it), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init= ), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; --=20 2.43.0