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([179.93.21.205]) by smtp.gmail.com with ESMTPSA id c2-20020a170902848200b001d09c539c96sm7494897plo.229.2023.12.18.04.54.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:54:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1702904066; x=1703508866; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pLrVv8VBLDDI9xgw0i6V3nJixdQ2OWE6VqwsOyfazpo=; b=PalTVUJrSA3LBtE3bWnO3mBvD3lPtFikQi2KYgbs1yWLrkoeUt68JJ4zuvQRd2uRaF vLIvcSywrHey/oWvJO4oT54XDtBVNkmNv2rfPvvHhFK9Bs9qj7gibmRSp4jlMgJwNgfh ZjvdGbCO9QsqHdShI7smekssHriAHj4iRd4W1LHXuZvnlDWGMBjOWu4n6myLEW2AplCS ElRwipdbpBt8+skj54zloLUc3R72YwrPQoHmDYT+fLE6fXSVDb3onJMSy00R3Wl/KNRu OHTP43WQnbGH2Ojhoj7w0Fynl76lhOGErN6IiymTpEoq1/ILOn7O6iBigBXYctSTf8ZZ inaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702904066; x=1703508866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pLrVv8VBLDDI9xgw0i6V3nJixdQ2OWE6VqwsOyfazpo=; b=goZ42Z1Avb2pLBmbnAB3daWQuCGJxmrhHNROgdlI7atlnTnnVCvY8vnIduNW2nkaDN 9XF4VkwFeQn73Tzuous5YpC4aDO2fXFbJLlLpz6RSBHYW990rUKFGc0+bdt3RcfcyVqH fUo1QUAs4LGt2WndPmpfpRSUd8KQI/slrZ4qAziUMakY97U0aHP8UCMDKEonmsHm5ku+ BifPU3ihUiw4RYvjCWzTjg/8kCLyhHcUiSCA+DdOHYfKaeiNNlucdB+w7sy59GHgC4Rc bXb/ae4qtfklpwTHwWk8OnKDJFPW0dZyUIdeEYAu16MHSspV2lO4MOmHkIdcPt5WPAe1 2slg== X-Gm-Message-State: AOJu0YxreRkH2T35d0l2GShPG0DLgDsAL4AlwHaRkN9QX9Xc3IcWQKNc Z+m+zQh6JO7Q4V35cZY7rbTtnoFWiHCcDEnmZ4w= X-Google-Smtp-Source: AGHT+IF3Z4PYxaaBPck2HlRzf5kbrUhJh6dthf0/E21mjgJ20h8sJ2jfRp4Jrr9e2IewKyw5b0vk1w== X-Received: by 2002:a17:902:d548:b0:1d3:7d0b:a878 with SMTP id z8-20020a170902d54800b001d37d0ba878mr3103003plf.124.1702904066132; Mon, 18 Dec 2023 04:54:26 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v13 13/26] target/riscv/tcg: handle profile MISA bits Date: Mon, 18 Dec 2023 09:53:21 -0300 Message-ID: <20231218125334.37184-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231218125334.37184-1-dbarboza@ventanamicro.com> References: <20231218125334.37184-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1702904425374100003 Content-Type: text/plain; charset="utf-8" The profile support is handling multi-letter extensions only. Let's add support for MISA bits as well. We'll go through every known MISA bit. If the profile doesn't declare the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext and env->misa_ext_mask. Now that we're setting profile MISA bits, one can use the rv64i CPU to boot Linux using the following options: -cpu rv64i,rva22u64=3Dtrue,rv39=3Dtrue,s=3Dtrue,zifencei=3Dtrue In the near future, when rva22s64 (where, 's', 'zifencei' and sv39 are mandatory), is implemented, rv64i will be able to boot Linux loading rva22s64 and no additional flags. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f8c35ba060..f2e0ce0f3d 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -941,6 +941,27 @@ static void cpu_set_profile(Object *obj, Visitor *v, c= onst char *name, profile->user_set =3D true; profile->enabled =3D value; =20 + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + uint32_t bit =3D misa_bits[i]; + + if (!(profile->misa_ext & bit)) { + continue; + } + + if (bit =3D=3D RVI && !profile->enabled) { + /* + * Disabling profiles will not disable the base + * ISA RV64I. + */ + continue; + } + + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(bit), + (gpointer)value); + riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); + } + for (i =3D 0; profile->ext_offsets[i] !=3D RISCV_PROFILE_EXT_LIST_END;= i++) { ext_offset =3D profile->ext_offsets[i]; =20 --=20 2.43.0