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([179.93.21.205]) by smtp.gmail.com with ESMTPSA id c2-20020a170902848200b001d09c539c96sm7494897plo.229.2023.12.18.04.54.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:54:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1702904062; x=1703508862; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i8rzVcCRKDFqmG0n6+Dd5TCpeM1lIcu/rUiXyvezW+Y=; b=V3sGv7Z1JbaKSoka3iTc+NcoUtKW5MTEQTmeIbuqrI0CqfhDMYLrXvSURgOXizkoe7 s98GPioCZ0cHN0328NS0L/ZaRgKr2WTJWV/16nqF2eNVBrH1V7fjC5huN85sy/wd3lNp EncUbBrQYu5KxVOSUjZGIfzJ2WyeJcRk4+SU9uMErgoH8nYfcC19cWSl0RdgaUZxRUxv WSP1/7UTYriKa9o8VzXPGlBcsl7Hs6lnkGGy599sZmZl5KPKip6yuEuQym8f126MBEJk a9aEBJghBQdxz0CYOK4X/Om/Rmv+ivoGrJ7ToE72ikDZLMrLiy2AwKCZytbwgRxsKsRT USlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702904062; x=1703508862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i8rzVcCRKDFqmG0n6+Dd5TCpeM1lIcu/rUiXyvezW+Y=; b=qLvVe8LIT5MhJJzs9J6g22wvI7QjpqicC/7jHNGk0b8meuYPiQJrD8qmwmEUDoxtiX bNRANfNadNWlHnh5TSwRj25KjGZ16t5L634GDz7WRpyDHqey08QpK0iegj8R76AvAakp 67raIfv6JzlXqeJ2tBdbcRA7Wpbb24euJWMVZi2QNhg3J5rEsTdAIRDinGTLDPhTkFlL qgSEC+srGzZpJ+6CmnsVttcYUmYNZpKZXdh1L5/ZmJUH9jCWWuGIVDNDkiCVTPK9IJGX IP+URz9OetsR0gK8PkD1EwZCSdF84cePUsG+d6Bz4eA/xyK6ihAFArd6Xl6D+4TlW1Cn wpXg== X-Gm-Message-State: AOJu0YzbVLx+gxdjYFFcwD4icUcm940MWraCVDGXAYHoK3i9Oo/KiaUv 3Kx8PNv19TfdK/vLo1BRzAoUbwZCx1d86s5v4XE= X-Google-Smtp-Source: AGHT+IF6yZXA6KAW8dLHAdO544NUNdmfgmRhwrfppZApt5u3ZoTG5v6eKewHStJgIdixgEwvnTqWuw== X-Received: by 2002:a05:6a20:d413:b0:18f:97c:4f6d with SMTP id il19-20020a056a20d41300b0018f097c4f6dmr7325361pzb.121.1702904062703; Mon, 18 Dec 2023 04:54:22 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v13 12/26] target/riscv/tcg: add riscv_cpu_write_misa_bit() Date: Mon, 18 Dec 2023 09:53:20 -0300 Message-ID: <20231218125334.37184-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231218125334.37184-1-dbarboza@ventanamicro.com> References: <20231218125334.37184-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1702904197683100003 Content-Type: text/plain; charset="utf-8" We have two instances of the setting/clearing a MISA bit from env->misa_ext and env->misa_ext_mask pattern. And the next patch will end up adding one more. Create a helper to avoid code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 2affc1f771..f8c35ba060 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -42,6 +42,20 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) GUINT_TO_POINTER(ext_offset)); } =20 +static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, + bool enabled) +{ + CPURISCVState *env =3D &cpu->env; + + if (enabled) { + env->misa_ext |=3D bit; + env->misa_ext_mask |=3D bit; + } else { + env->misa_ext &=3D ~bit; + env->misa_ext_mask &=3D ~bit; + } +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -828,13 +842,9 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, */ env->priv_ver =3D PRIV_VERSION_1_12_0; } - - env->misa_ext |=3D misa_bit; - env->misa_ext_mask |=3D misa_bit; - } else { - env->misa_ext &=3D ~misa_bit; - env->misa_ext_mask &=3D ~misa_bit; } + + riscv_cpu_write_misa_bit(cpu, misa_bit, value); } =20 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, @@ -878,7 +888,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { - CPURISCVState *env =3D &RISCV_CPU(cpu_obj)->env; bool use_def_vals =3D riscv_cpu_is_generic(cpu_obj); int i; =20 @@ -899,13 +908,8 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - if (misa_cfg->enabled) { - env->misa_ext |=3D bit; - env->misa_ext_mask |=3D bit; - } else { - env->misa_ext &=3D ~bit; - env->misa_ext_mask &=3D ~bit; - } + riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit, + misa_cfg->enabled); } } } --=20 2.43.0