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([179.93.21.205]) by smtp.gmail.com with ESMTPSA id c2-20020a170902848200b001d09c539c96sm7494897plo.229.2023.12.18.04.54.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 04:54:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1702904059; x=1703508859; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rNARKIfhoPxmRP3J0BiDE+A19wjwPVPxbW/hLjbI6Z0=; b=P5G6ru3T40IoaYAy/zSY7FNIDY1LnOXbr2rtKCX35U6b8GcKjM7Crfvy1xYqa/EeSi Wkb1LzyyRs5cgDvPSKTk/Qy0/dhD7ofI7bPfaRaI0hZwrK+ti4CkcAbleLElg53Eh1xV vteouGZUad3FvG8MUu1BsVLP/NdnJmTA8Rk4cEiHf4iqD+5hsyiXm48WsV/4uMRZwESb dtI/8i5WmKGeiB43Pf1F/931eYP0vJ5ITOH0fDG0y5WjvNXXicVWCpR7V04YpSaZ1Tt8 2aJQVLOMT1ldu8QgBa1fvMNGmiufcET29RNj6mpIShRVmMjwlHHj/WbeJI1lqXkWPQcy mwig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702904059; x=1703508859; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rNARKIfhoPxmRP3J0BiDE+A19wjwPVPxbW/hLjbI6Z0=; b=Exh5ePTwvf7ePdU8fG+XDhk4kG2CdaeJoQnPXQhp/yR2LUCk2R99wkmidQC0mKRyQ4 eqLNz0n29BKwLOg1Del2qGzmZHGrldZ991IL/iWnqEnR+i+dgtSI4UqmjiD4qJydtSFP gc4DzAQRrVEMsZpwGMD1AuwTLrTXhyKzyWh/g2J2D+uoySh9l0pPyF4hncJ+Js6e4Zvm UbeWpOe402vzqS6AkFnjzFAIQlQQGCd+IJYgIzffVpIzNkSSTyGZLEl74b2E/tI2sHVe 4Lf+tKx3iGr6kN9kpUrmGOQioxQ0u9GjyuCi0fENBprywAbvOnDE4/6v5BlnnqihSKni tHlA== X-Gm-Message-State: AOJu0Yzg/m3naoJ/NRYm+neyvIeVO8ugbPhy6yTkx1n7eKCsTaRccfLt a9NikltvUZpvIYit5SH9lA5dis5wkGIDsFER4kQ= X-Google-Smtp-Source: AGHT+IEaNqrBd/UocUgddmcUMIEXioWsOvDaGAeWyCoD1FyfBiAMLHoFst+OfDXlr9nRNXJcmSb1Lg== X-Received: by 2002:a17:903:18a:b0:1d0:acd4:e711 with SMTP id z10-20020a170903018a00b001d0acd4e711mr22518068plg.15.1702904059625; Mon, 18 Dec 2023 04:54:19 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v13 11/26] target/riscv/tcg: add MISA user options hash Date: Mon, 18 Dec 2023 09:53:19 -0300 Message-ID: <20231218125334.37184-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231218125334.37184-1-dbarboza@ventanamicro.com> References: <20231218125334.37184-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1702904298520100001 Content-Type: text/plain; charset="utf-8" We already track user choice for multi-letter extensions because we needed to honor user choice when enabling/disabling extensions during realize(). We refrained from adding the same mechanism for MISA extensions since we didn't need it. Profile support requires tne need to check for user choice for MISA extensions, so let's add the corresponding hash now. It works like the existing multi-letter hash (multi_ext_user_opts) but tracking MISA bits options in the cpu_set_misa_ext_cfg() callback. Note that we can't re-use the same hash from multi-letter extensions because that hash uses cpu->cfg offsets as keys, while for MISA extensions we're using MISA bits as keys. After adding the user hash in cpu_set_misa_ext_cfg(), setting default values with object_property_set_bool() in add_misa_properties() will end up marking the user choice hash with them. Set the default value manually to avoid it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 83d4dd00cf..2affc1f771 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -34,6 +34,7 @@ =20 /* Hash that stores user set extensions */ static GHashTable *multi_ext_user_opts; +static GHashTable *misa_ext_user_opts; =20 static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { @@ -802,6 +803,10 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor = *v, const char *name, return; } =20 + g_hash_table_insert(misa_ext_user_opts, + GUINT_TO_POINTER(misa_bit), + (gpointer)value); + prev_val =3D env->misa_ext & misa_bit; =20 if (value =3D=3D prev_val) { @@ -873,6 +878,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { + CPURISCVState *env =3D &RISCV_CPU(cpu_obj)->env; bool use_def_vals =3D riscv_cpu_is_generic(cpu_obj); int i; =20 @@ -893,7 +899,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_= obj) NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); if (use_def_vals) { - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NUL= L); + if (misa_cfg->enabled) { + env->misa_ext |=3D bit; + env->misa_ext_mask |=3D bit; + } else { + env->misa_ext &=3D ~bit; + env->misa_ext_mask &=3D ~bit; + } } } } @@ -1142,6 +1154,7 @@ static void tcg_cpu_instance_init(CPUState *cs) RISCVCPU *cpu =3D RISCV_CPU(cs); Object *obj =3D OBJECT(cpu); =20 + misa_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); riscv_cpu_add_user_properties(obj); =20 --=20 2.43.0