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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j18-20020adff012000000b003366da509ecsm671193wro.85.2023.12.18.03.33.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 03:33:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702899189; x=1703503989; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=pI9y91DFQZNTbXdExRzAPNc0Dc6/QVSgo+x9WHnJ4D4=; b=hY/r8ifhnnkLT8kCj5d6TSHFlhNM4CteUJjUba5lnZj719FMg00uA49gBNyTQE/YWe Dmsbw/1Q4RwsCv7AJ+aYoj6Jgeb3WjpzqhbCgy4lj0Y//yGWiEGH/7Q/JyjEKnuaPkyl OTqVI1eYaYLxOWUh5KOWBMhhyWh44yqkMq2ctCvQyQlOzl5RSVdVgYjC406uR0upx4q5 PM7QUsh+ajwVCpQ1wLvIcy7lMTKGQyRI/+0bCbjFaYUVgftXvrClCwxP4f+OJqxbqXI8 MiFOoo/ruwWF87uBwQu91w2UYqv20/ZmIBPm+Tk6iATNGIEZtxw8j+l0VjC5WiJ9e2Ea wB6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702899189; x=1703503989; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pI9y91DFQZNTbXdExRzAPNc0Dc6/QVSgo+x9WHnJ4D4=; b=sh/PW3GFenip4yTk9td0Snd+UyXVxH08MatHe94GFk/NIpPy5dgZ83iB1C0fgEb3vI JuWvdBvq6Nd9JVi8EkgLExAW+v/LoT4vo+bAHZ1T74cc9/1xzKtVL+s4vF+FnDI6Gwjh nzfr8h0hdcPwBA1LVmdLRRTBT+XLz5I5xTpz8KWislb9YxzTe36kpQuGc1gxK5tUgmfO SEzkfAeFNUp3MeRHCEyPpmwSYF9Po1mi4u5q9KvPOKauI80gTvKsPCcUv626bIyprOaW z+7JCSGkFxwRkmzkvg7fqpFmpMIP5X8u+4xDOW5RzGy9BSvqdorfFP4jQe55u7FyMQPV 66EQ== X-Gm-Message-State: AOJu0YyZpF+Oth02xIzBgC0S389SbxER7UIRdTZBwi0+rMTZ67BJKKa2 f8wyAwzGT6AGLn+Ki9EIvKJ48g== X-Google-Smtp-Source: AGHT+IEujoN2e5M/N9xLGvHGlpFt6gGGpsHZXN2QZGUyTGiN3q5v1k5g1r5+90zmmHKQq+DnsI0qrA== X-Received: by 2002:a05:600c:3c8b:b0:40c:4b42:a20b with SMTP id bg11-20020a05600c3c8b00b0040c4b42a20bmr5830850wmb.8.1702899189147; Mon, 18 Dec 2023 03:33:09 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/35] target/arm: Implement HCR_EL2.AT handling Date: Mon, 18 Dec 2023 11:32:35 +0000 Message-Id: <20231218113305.2511480-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113305.2511480-1-peter.maydell@linaro.org> References: <20231218113305.2511480-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1702899265739100011 Content-Type: text/plain; charset="utf-8" The FEAT_NV HCR_EL2.AT bit enables trapping of some address translation instructions from EL1 to EL2. Implement this behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ca8de414bdb..f1c7fbf319c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3687,6 +3687,15 @@ static CPAccessResult at_s1e2_access(CPUARMState *en= v, const ARMCPRegInfo *ri, return at_e012_access(env, ri, isread); } =20 +static CPAccessResult at_s1e01_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_AT)) { + return CP_ACCESS_TRAP_EL2; + } + return at_e012_access(env, ri, isread); +} + static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5552,22 +5561,22 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt =3D FGT_ATS1E1R, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt =3D FGT_ATS1E1W, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, { .name =3D "AT_S1E0R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 2, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt =3D FGT_ATS1E0R, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, { .name =3D "AT_S1E0W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 3, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt =3D FGT_ATS1E0W, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, { .name =3D "AT_S12E1R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 4, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, @@ -8145,12 +8154,12 @@ static const ARMCPRegInfo ats1e1_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt =3D FGT_ATS1E1RP, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, { .name =3D "AT_S1E1WP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .fgt =3D FGT_ATS1E1WP, - .accessfn =3D at_e012_access, .writefn =3D ats_write64 }, + .accessfn =3D at_s1e01_access, .writefn =3D ats_write64 }, }; =20 static const ARMCPRegInfo ats1cp_reginfo[] =3D { --=20 2.34.1