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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j18-20020adff012000000b003366da509ecsm671193wro.85.2023.12.18.03.33.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 03:33:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702899201; x=1703504001; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=nDtTmxnTvjnXEk8xcvOOb8nCioQSxbevWpP7qdlO2bA=; b=NP7stvqto2DP1dMJU4jwONfSRNkn9zFUNx9+gLUPftvVQFh6BGfFqtczEFe3z2kq3Q UjS3vzuhPMSJB1tkm28wTB0eBKPEBW8fTWry4qxekqWTZbft/TPHyRN7JgbMJgf2piNF xajNxMhOe6a00N4+W8LNdktHXjWsmetTxr07gbs8BORGnvlqV7V5dRvfKAcpfx+WjSzS 5PGGhJs3QJN2scLgoT2kcE2VcDPPI5/MYqDVL/AGsyOyN4CdDAJ9dVxz2Ng6xdbIOhQK hVcE42DwzErO0NgYwneSqtAclsioUm8miG+Cl8hVlLtJTxmQihnL0ITcTMbbvmSg1eZ1 FBLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702899201; x=1703504001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nDtTmxnTvjnXEk8xcvOOb8nCioQSxbevWpP7qdlO2bA=; b=gVpRlnwHkkJVk6NoAtOX+meZw7xjSDINIjRzu9NzwwVEPlbN/vAY0fEyisxz1X+nn6 dnlS49GI2g6EgWYciUWi8CieZ0GtB0uidi16dkQcGP8LdWOlC4nbTkueZglfmgH3aNo5 mOuiwoI2qHD2PXrdNoq7SelPnUXP0NeWYXl9s8uP5IyUXuWbW7bAPT3/kAK4r3H3I9Iw fYZ67UR+vHp1nIJuIGmcUl9vpmKPP6z6m5Lhbo/jghwsfZQ2RmRoUkPYB/QWSQPmt7ea Vd0+yKx+DBi3LoIyVLJeI8oPgjVWgFkJIJ/XGnUP5UVxDBobSLvCHaAevhthAmCGf5kW VrQQ== X-Gm-Message-State: AOJu0YysXoGO1kUWlmEOKBRkJJ1h9GYVYsXXz6zED0Ax4LcO2VUWMot2 eUlCDc9Y1tAgWi+43cOZCSnnLnBfW9Fmz5IFXpg= X-Google-Smtp-Source: AGHT+IG6kv57zpFTZcTvXUdeRGXf9tnDa/ZRB9rfNWJcNgsv5NHDTQzXsDRzcW+1N60E/VzY9VogAQ== X-Received: by 2002:a5d:5191:0:b0:333:3c28:2895 with SMTP id k17-20020a5d5191000000b003333c282895mr7819790wrv.77.1702899201695; Mon, 18 Dec 2023 03:33:21 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 31/35] target/arm: Mark up VNCR offsets (offsets >= 0x200, except GIC) Date: Mon, 18 Dec 2023 11:33:01 +0000 Message-Id: <20231218113305.2511480-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113305.2511480-1-peter.maydell@linaro.org> References: <20231218113305.2511480-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1702899312104100002 Content-Type: text/plain; charset="utf-8" Mark up the cpreginfo structs to indicate offsets for system registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. This covers all the remaining offsets at 0x200 and above, except for the GIC ICH_* registers. (Note that because we don't implement FEAT_SPE, FEAT_TRF, FEAT_MPAM, FEAT_BRBE or FEAT_AMUv1p1 we don't implement any of the registers that use offsets at 0x800 and above.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6c33619d646..c72ce4aee09 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4271,6 +4271,7 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { .opc0 =3D 3, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_FAR_EL1, + .nv2_redirect_offset =3D 0x220 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, }; @@ -4286,6 +4287,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR0_EL1, + .nv2_redirect_offset =3D 0x200 | NV2_REDIR_NV1, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, @@ -4293,6 +4295,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR1_EL1, + .nv2_redirect_offset =3D 0x210 | NV2_REDIR_NV1, .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, @@ -5725,6 +5728,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_nv1, + .nv2_redirect_offset =3D 0x230 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, elr_el[1]) }, { .name =3D "SPSR_EL1", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, @@ -5744,6 +5748,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, sp_el[0]) }, { .name =3D "SP_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, + .nv2_redirect_offset =3D 0x240, .access =3D PL2_RW, .type =3D ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP, .fieldoffset =3D offsetof(CPUARMState, sp_el[1]) }, { .name =3D "SPSel", .state =3D ARM_CP_STATE_AA64, @@ -6866,9 +6871,11 @@ static const ARMCPRegInfo minimal_ras_reginfo[] =3D { .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "VDISR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .nv2_redirect_offset =3D 0x500, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vdis= r_el2) }, { .name =3D "VSESR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 3, + .nv2_redirect_offset =3D 0x508, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vses= r_el2) }, }; =20 @@ -9524,6 +9531,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_RW, .writefn =3D vbar_write, .accessfn =3D access_nv1, .fgt =3D FGT_VBAR_EL1, + .nv2_redirect_offset =3D 0x250 | NV2_REDIR_NV1, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue =3D 0 }, --=20 2.34.1