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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j18-20020adff012000000b003366da509ecsm671193wro.85.2023.12.18.03.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 03:33:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702899201; x=1703504001; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=kn2/l6hTTPHeOx0ZYSVe0llwanYj6080bnCCd9Z4V2M=; b=baaT3mTaKdbbi+uXKErRNSrjroRLEWhAIOndp5dlVhFL9SPP/I5HH30MaMQAYTR6QK rTcAtbjlfG0rnBUCH3amYqfm1cz2Uje7DBQ4+MdxL2+wsFzw33pkdmf8Isy9B/b/hm9n pKR+iNM67JilZMpA2G63AYOGMLeV5dLlzBlXY47HIEuZC6OLNjahOtVIqKOF/r3tgHj7 LdkhnjR9feBuwDkMx0lta55ce6yeVWarjQVzYZIu2KycO0ZV56fvGBt8gNHIK/B45bg8 SrT7OBjYpkFKE4MVcu2wC2jD6ET2JIWUtAJkuDRBW9k2ZFoV3tYKJBI/e9sMnErG/biA zXBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702899201; x=1703504001; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kn2/l6hTTPHeOx0ZYSVe0llwanYj6080bnCCd9Z4V2M=; b=NwPXPK/MIOTiI43T1SRNpbdm8QwjjOHZbp+rUNOtHX2LjvXfucU3KEj5+cTfTm9mBe kHpkP/AR8FG57kjb5CC6Fwg8vjSv9aD7yJKUJmQCcnhvVJFVH6yOoZIgxmqy9Mo1HC/B QlPZCLTbVr9HVHTBRKg99wtYF/N0xSwLoY+puziwtPgsgBRbs3g/EoHSi1yeXWhHTwxy aBRg6wSFRErWLreNMgpUEETdCEOLafvpaZC94qAUzA3oRgCov4jtXzn2P97y6nQAIVxN hzQbjN5JpL/o6wRj4bG29rkouwez46eDSzORiOlam8KzVl3bVCrm5SeMx0CtnZckdIX/ wBcg== X-Gm-Message-State: AOJu0YylCvjMQ5nzulspJBn+eLNZmjLOP/nbu9qNgiX7++vumXkX43Fq PpmPh4t6raxeM1d/X/uhc5LZWQ== X-Google-Smtp-Source: AGHT+IElndi+94KSFK6LRarRfR6Us0Wnk9FBdAzRala1ydZKfsZknkQr6fYPYCJ3SzL+zgdmectMQQ== X-Received: by 2002:adf:f4c5:0:b0:336:6102:9c04 with SMTP id h5-20020adff4c5000000b0033661029c04mr1652570wrp.125.1702899201227; Mon, 18 Dec 2023 03:33:21 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 30/35] target/arm: Mark up VNCR offsets (offsets 0x168..0x1f8) Date: Mon, 18 Dec 2023 11:33:00 +0000 Message-Id: <20231218113305.2511480-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113305.2511480-1-peter.maydell@linaro.org> References: <20231218113305.2511480-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1702899263770100005 Content-Type: text/plain; charset="utf-8" Mark up the cpreginfo structs to indicate offsets for system registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. This commit covers offsets 0x168 to 0x1f8. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 78c3c3ebd8d..6c33619d646 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3175,6 +3175,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, .type =3D ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_ptimer_access, + .nv2_redirect_offset =3D 0x180 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), .resetvalue =3D 0, .readfn =3D gt_phys_redir_ctl_read, .raw_readfn =3D raw_read, @@ -3192,6 +3193,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, .type =3D ARM_CP_IO, .access =3D PL0_RW, .accessfn =3D gt_vtimer_access, + .nv2_redirect_offset =3D 0x170 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), .resetvalue =3D 0, .readfn =3D gt_virt_redir_ctl_read, .raw_readfn =3D raw_read, @@ -3271,6 +3273,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, .access =3D PL0_RW, .type =3D ARM_CP_IO, + .nv2_redirect_offset =3D 0x178 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), .resetvalue =3D 0, .accessfn =3D gt_ptimer_access, .readfn =3D gt_phys_redir_cval_read, .raw_readfn =3D raw_read, @@ -3288,6 +3291,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, .access =3D PL0_RW, .type =3D ARM_CP_IO, + .nv2_redirect_offset =3D 0x168 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), .resetvalue =3D 0, .accessfn =3D gt_vtimer_access, .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, @@ -7036,6 +7040,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, static const ARMCPRegInfo zcr_reginfo[] =3D { { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .nv2_redirect_offset =3D 0x1e0 | NV2_REDIR_NV1, .access =3D PL1_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }, @@ -7177,6 +7182,7 @@ static const ARMCPRegInfo sme_reginfo[] =3D { .writefn =3D svcr_write, .raw_writefn =3D raw_write }, { .name =3D "SMCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 6, + .nv2_redirect_offset =3D 0x1f0 | NV2_REDIR_NV1, .access =3D PL1_RW, .type =3D ARM_CP_SME, .fieldoffset =3D offsetof(CPUARMState, vfp.smcr_el[1]), .writefn =3D smcr_write, .raw_writefn =3D raw_write }, @@ -7210,6 +7216,7 @@ static const ARMCPRegInfo sme_reginfo[] =3D { .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "SMPRIMAP_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 5, + .nv2_redirect_offset =3D 0x1f8, .access =3D PL2_RW, .accessfn =3D access_smprimap, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; @@ -7924,6 +7931,7 @@ static const ARMCPRegInfo mte_reginfo[] =3D { { .name =3D "TFSR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tfsr_el1, + .nv2_redirect_offset =3D 0x190 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[1]) }, { .name =3D "TFSR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_NV2_REDIRECT, @@ -8098,6 +8106,7 @@ static const ARMCPRegInfo scxtnum_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, .access =3D PL1_RW, .accessfn =3D access_scxtnum_el1, .fgt =3D FGT_SCXTNUM_EL1, + .nv2_redirect_offset =3D 0x188 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, @@ -8122,22 +8131,27 @@ static CPAccessResult access_fgt(CPUARMState *env, = const ARMCPRegInfo *ri, static const ARMCPRegInfo fgt_reginfo[] =3D { { .name =3D "HFGRTR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, + .nv2_redirect_offset =3D 0x1b8, .access =3D PL2_RW, .accessfn =3D access_fgt, .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_read[FGTREG_HFGRTR])= }, { .name =3D "HFGWTR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 5, + .nv2_redirect_offset =3D 0x1c0, .access =3D PL2_RW, .accessfn =3D access_fgt, .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_write[FGTREG_HFGWTR]= ) }, { .name =3D "HDFGRTR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 1, .opc2 =3D 4, + .nv2_redirect_offset =3D 0x1d0, .access =3D PL2_RW, .accessfn =3D access_fgt, .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_read[FGTREG_HDFGRTR]= ) }, { .name =3D "HDFGWTR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 1, .opc2 =3D 5, + .nv2_redirect_offset =3D 0x1d8, .access =3D PL2_RW, .accessfn =3D access_fgt, .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_write[FGTREG_HDFGWTR= ]) }, { .name =3D "HFGITR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 6, + .nv2_redirect_offset =3D 0x1c8, .access =3D PL2_RW, .accessfn =3D access_fgt, .fieldoffset =3D offsetof(CPUARMState, cp15.fgt_exec[FGTREG_HFGITR])= }, }; @@ -8324,12 +8338,14 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL2_RW, .accessfn =3D e2h_access, + .nv2_redirect_offset =3D 0x180 | NV2_REDIR_NO_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write }, { .name =3D "CNTV_CTL_EL02", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL2_RW, .accessfn =3D e2h_access, + .nv2_redirect_offset =3D 0x170 | NV2_REDIR_NO_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write }, { .name =3D "CNTP_TVAL_EL02", .state =3D ARM_CP_STATE_AA64, @@ -8346,11 +8362,13 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), + .nv2_redirect_offset =3D 0x178 | NV2_REDIR_NO_NV1, .access =3D PL2_RW, .accessfn =3D e2h_access, .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write }, { .name =3D "CNTV_CVAL_EL02", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .nv2_redirect_offset =3D 0x168 | NV2_REDIR_NO_NV1, .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), .access =3D PL2_RW, .accessfn =3D e2h_access, .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write }, --=20 2.34.1