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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j18-20020adff012000000b003366da509ecsm671193wro.85.2023.12.18.03.33.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 03:33:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702899200; x=1703504000; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Z7QW8HRv+OdPPQfiZWYsUh8DiaaeWI6g2SxQoB+HBCo=; b=RKMA4up7J6tkfvw9L+xRRJ3WEeXNIF0sSbj4FAn/yJGj+F/XVJwICyIKcKNsgpxF7N vYUvcqFM8c0EUMfFQcfC8DQwHCdxnbhkR0Woar/rCFK9PQguz4/7IGkYPcq2A622HxXo jpr6Ae05Y1oPnGgCGTB1IgSucDJmeY84DEARQmre4O6lYkMoEaSrEDHAVM13pEmHDz8w Mma7thXsqV2kBGqeI1U8x+4uiUXOxVxqQFwe3aSRI4Ef2sSWIn1+IUMjf4/ZUYW7Nb77 uEvtZgMdA0XSHzcsslVvzfjtK8PDT9yiaDc484VUhLf6K9RF9V1GSeij3K2gQrwvMnFK ZnFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702899200; x=1703504000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z7QW8HRv+OdPPQfiZWYsUh8DiaaeWI6g2SxQoB+HBCo=; b=SVbFNMRA7kX8KzftYK8WMdMNQVqsZ2wRF5WN0gpdV2nGS/AVXQ91Lf8wuS6VlL4pa2 IpsBoVZII2caz53ZO9VGH1ClB9E8clC0FsXxbanu7FhVQm/zWw7rjoCgHmUV2uRBFzzZ 5Vfgaths0RyDricE/m0pfT0V6X4xwtuT2cunAENfGfPQZIy/yn/IshPiLtFWxGUilmEN +kbvYc+KCs3dTCoG4rjxU4jZlPIJR2Aksr8Rv2zFIiqE4x3rvV582+xktJWebbaXXC9o Md3MoCDIi9FRnrC4mOupnvewGCRDQgCJqlfkBIQ39beLjoU9zafrvzx7jzK5bwuKePN5 fUOA== X-Gm-Message-State: AOJu0Yz+9prkSvQSIMSg0anJB6mcyK2kBNVHpetFdf7lH65tGCMILVx6 lBj8oOo9D1HwKGiclyuK8BgPfWYtuDTvP992EzY= X-Google-Smtp-Source: AGHT+IEg2OrL+46VK0iq2bU6MtV5rWjBDYULpVVIdCSBJzQnR/h/I3vHMaHggYTLTLONYRhYO7DrEA== X-Received: by 2002:adf:ea0a:0:b0:336:6054:7dda with SMTP id q10-20020adfea0a000000b0033660547ddamr1657181wrm.131.1702899200310; Mon, 18 Dec 2023 03:33:20 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 28/35] target/arm: Mark up VNCR offsets (offsets 0x0..0xff) Date: Mon, 18 Dec 2023 11:32:58 +0000 Message-Id: <20231218113305.2511480-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231218113305.2511480-1-peter.maydell@linaro.org> References: <20231218113305.2511480-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1702899483206100009 Content-Type: text/plain; charset="utf-8" Mark up the cpreginfo structs to indicate offsets for system registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in the Arm ARM. This commit covers offsets below 0x100; all of these registers are redirected to memory regardless of the value of HCR_EL2.NV1. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 61aac61bcc4..ff7f90fa4af 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6043,6 +6043,7 @@ static const ARMCPRegInfo hcrx_el2_reginfo =3D { .name =3D "HCRX_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 2, .access =3D PL2_RW, .writefn =3D hcrx_write, .accessfn =3D access_hxen, + .nv2_redirect_offset =3D 0xa0, .fieldoffset =3D offsetof(CPUARMState, cp15.hcrx_el2), }; =20 @@ -6109,6 +6110,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .type =3D ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), + .nv2_redirect_offset =3D 0x78, .writefn =3D hcr_write, .raw_writefn =3D raw_write }, { .name =3D "HCR", .state =3D ARM_CP_STATE_AA32, .type =3D ARM_CP_ALIAS | ARM_CP_IO, @@ -6193,6 +6195,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, .access =3D PL2_RW, + .nv2_redirect_offset =3D 0x40, /* no .writefn needed as this can't cause an ASID change */ .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, @@ -6204,6 +6207,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .writefn =3D vttbr_write, .raw_writefn =3D raw_w= rite, + .nv2_redirect_offset =3D 0x20, .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2) }, { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, @@ -6212,6 +6216,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_RW, .resetvalue =3D 0, + .nv2_redirect_offset =3D 0x90, .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) }, { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, @@ -6307,6 +6312,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, .access =3D PL2_RW, .type =3D ARM_CP_IO, .resetvalue =3D 0, .writefn =3D gt_cntvoff_write, + .nv2_redirect_offset =3D 0x60, .fieldoffset =3D offsetof(CPUARMState, cp15.cntvoff_el2) }, { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_I= O, @@ -6345,6 +6351,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, .cp =3D 15, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 = =3D 3, .access =3D PL2_RW, + .nv2_redirect_offset =3D 0x80, .fieldoffset =3D offsetof(CPUARMState, cp15.hstr_el2) }, }; =20 @@ -6370,10 +6377,12 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] =3D { { .name =3D "VSTTBR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 6, .opc2 =3D 0, .access =3D PL2_RW, .accessfn =3D sel2_access, + .nv2_redirect_offset =3D 0x30, .fieldoffset =3D offsetof(CPUARMState, cp15.vsttbr_el2) }, { .name =3D "VSTCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 6, .opc2 =3D 2, .access =3D PL2_RW, .accessfn =3D sel2_access, + .nv2_redirect_offset =3D 0x48, .fieldoffset =3D offsetof(CPUARMState, cp15.vstcr_el2) }, }; =20 @@ -8131,6 +8140,7 @@ static const ARMCPRegInfo nv2_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 2, .opc2 =3D 0, .access =3D PL2_RW, .writefn =3D vncr_write, + .nv2_redirect_offset =3D 0xb0, .fieldoffset =3D offsetof(CPUARMState, cp15.vncr_el2) }, }; =20 @@ -8962,6 +8972,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, .access =3D PL2_RW, .resetvalue =3D cpu->midr, .type =3D ARM_CP_EL3_NO_EL2_C_NZ, + .nv2_redirect_offset =3D 0x88, .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, { .name =3D "VMPIDR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 5, @@ -8973,6 +8984,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 5, .access =3D PL2_RW, .resetvalue =3D vmpidr_def, .type =3D ARM_CP_EL3_NO_EL2_C_NZ, + .nv2_redirect_offset =3D 0x50, .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, }; /* --=20 2.34.1