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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=n.ostrenkov@gmail.com; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1702733723732100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Nikita Ostrenkov --- hw/misc/imx7_snvs.c | 93 ++++++++++++++++++++++++++++++++++--- hw/misc/trace-events | 4 +- include/hw/misc/imx7_snvs.h | 7 ++- 3 files changed, 94 insertions(+), 10 deletions(-) diff --git a/hw/misc/imx7_snvs.c b/hw/misc/imx7_snvs.c index a245f96cd4..8e7f43187f 100644 --- a/hw/misc/imx7_snvs.c +++ b/hw/misc/imx7_snvs.c @@ -13,28 +13,100 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qemu/timer.h" +#include "migration/vmstate.h" #include "hw/misc/imx7_snvs.h" +#include "qemu/cutils.h" #include "qemu/module.h" +#include "sysemu/sysemu.h" +#include "sysemu/rtc.h" #include "sysemu/runstate.h" #include "trace.h" =20 +#define RTC_FREQ 32768ULL + +static const VMStateDescription vmstate_imx7_snvs =3D { + .name =3D TYPE_IMX7_SNVS, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(tick_offset, IMX7SNVSState), + VMSTATE_UINT64(lpcr, IMX7SNVSState), + VMSTATE_END_OF_LIST() + } +}; + +static uint64_t imx7_snvs_get_count(IMX7SNVSState *s) +{ + uint64_t ticks =3D muldiv64(qemu_clock_get_ns(rtc_clock), RTC_FREQ, + NANOSECONDS_PER_SECOND); + return s->tick_offset + ticks; +} + static uint64_t imx7_snvs_read(void *opaque, hwaddr offset, unsigned size) { - trace_imx7_snvs_read(offset, 0); + IMX7SNVSState *s =3D IMX7_SNVS(opaque); + uint64_t ret =3D 0; + + switch (offset) { + case SNVS_LPSRTCMR: + ret =3D extract64(imx7_snvs_get_count(s), 32, 15); + break; + case SNVS_LPSRTCLR: + ret =3D extract64(imx7_snvs_get_count(s), 0, 32); + break; + case SNVS_LPCR: + ret =3D s->lpcr; + break; + } =20 - return 0; + trace_imx7_snvs_read(offset, ret, size); + + return ret; +} + +static void imx7_snvs_reset(DeviceState *dev) +{ + IMX7SNVSState *s =3D IMX7_SNVS(dev); + + s->lpcr =3D 0; } =20 static void imx7_snvs_write(void *opaque, hwaddr offset, uint64_t v, unsigned size) { - const uint32_t value =3D v; - const uint32_t mask =3D SNVS_LPCR_TOP | SNVS_LPCR_DP_EN; + trace_imx7_snvs_write(offset, v, size); + + IMX7SNVSState *s =3D IMX7_SNVS(opaque); =20 - trace_imx7_snvs_write(offset, value); + uint64_t new_value =3D 0, snvs_count =3D 0; =20 - if (offset =3D=3D SNVS_LPCR && ((value & mask) =3D=3D mask)) { - qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + if (offset =3D=3D SNVS_LPSRTCMR || offset =3D=3D SNVS_LPSRTCLR) { + snvs_count =3D imx7_snvs_get_count(s); + } + + switch (offset) { + case SNVS_LPSRTCMR: + new_value =3D deposit64(snvs_count, 32, 32, v); + break; + case SNVS_LPSRTCLR: + new_value =3D deposit64(snvs_count, 0, 32, v); + break; + case SNVS_LPCR: { + s->lpcr =3D v; + + const uint32_t mask =3D SNVS_LPCR_TOP | SNVS_LPCR_DP_EN; + + if ((v & mask) =3D=3D mask) { + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } + break; + } + } + + if (offset =3D=3D SNVS_LPSRTCMR || offset =3D=3D SNVS_LPSRTCLR) { + s->tick_offset +=3D new_value - snvs_count; } } =20 @@ -59,17 +131,24 @@ static void imx7_snvs_init(Object *obj) { SysBusDevice *sd =3D SYS_BUS_DEVICE(obj); IMX7SNVSState *s =3D IMX7_SNVS(obj); + struct tm tm; =20 memory_region_init_io(&s->mmio, obj, &imx7_snvs_ops, s, TYPE_IMX7_SNVS, 0x1000); =20 sysbus_init_mmio(sd, &s->mmio); + + qemu_get_timedate(&tm, 0); + s->tick_offset =3D mktimegm(&tm) - + qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND; } =20 static void imx7_snvs_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->reset =3D imx7_snvs_reset; + dc->vmsd =3D &vmstate_imx7_snvs; dc->desc =3D "i.MX7 Secure Non-Volatile Storage Module"; } =20 diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 05ff692441..85725506bf 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -116,8 +116,8 @@ imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64 imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value= 0x%08" PRIx64 =20 # imx7_snvs.c -imx7_snvs_read(uint64_t offset, uint32_t value) "addr 0x%08" PRIx64 "value= 0x%08" PRIx32 -imx7_snvs_write(uint64_t offset, uint32_t value) "addr 0x%08" PRIx64 "valu= e 0x%08" PRIx32 +imx7_snvs_read(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS = read: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" +imx7_snvs_write(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS= write: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u" =20 # mos6522.c mos6522_set_counter(int index, unsigned int val) "T%d.counter=3D%d" diff --git a/include/hw/misc/imx7_snvs.h b/include/hw/misc/imx7_snvs.h index 14a1d6fe6b..1272076086 100644 --- a/include/hw/misc/imx7_snvs.h +++ b/include/hw/misc/imx7_snvs.h @@ -20,7 +20,9 @@ enum IMX7SNVSRegisters { SNVS_LPCR =3D 0x38, SNVS_LPCR_TOP =3D BIT(6), - SNVS_LPCR_DP_EN =3D BIT(5) + SNVS_LPCR_DP_EN =3D BIT(5), + SNVS_LPSRTCMR =3D 0x050, /* Secure Real Time Counter MSB Register */ + SNVS_LPSRTCLR =3D 0x054, /* Secure Real Time Counter LSB Register */ }; =20 #define TYPE_IMX7_SNVS "imx7.snvs" @@ -31,6 +33,9 @@ struct IMX7SNVSState { SysBusDevice parent_obj; =20 MemoryRegion mmio; + + uint64_t tick_offset; + uint64_t lpcr; }; =20 #endif /* IMX7_SNVS_H */ --=20 2.34.1