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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231213-riscv-v7-1-a760156a337f@daynix.com> References: <20231213-riscv-v7-0-a760156a337f@daynix.com> In-Reply-To: <20231213-riscv-v7-0-a760156a337f@daynix.com> To: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , =?utf-8?q?Alex_Benn=C3=A9e?= , Mikhail Tyutin , Aleksandr Anenkov , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Fabiano Rosas Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::636; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1702444853554100001 The effective MXL value matters when booting. Signed-off-by: Akihiko Odaki --- hw/riscv/boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 0ffca05189f0..bc67c0bd1890 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -36,7 +36,7 @@ =20 bool riscv_is_32bit(RISCVHartArrayState *harts) { - return harts->harts[0].env.misa_mxl_max =3D=3D MXL_RV32; + return harts->harts[0].env.misa_mxl =3D=3D MXL_RV32; } =20 /* --=20 2.43.0 From nobody Wed Nov 19 18:38:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1702444840; cv=none; d=zohomail.com; s=zohoarc; b=XizMDDBbVAOYRJ7vh5nToIsJhUm5l3HgkYuRPGgELyV1Ec8LGc94+VHirDv7U54PRq1ZAZ14HAPp0HN2efoaOm0QeGU0DWsZJVLvV4AQyaHq3KfUes24bafbnk4xsSNczOLH3bJIlApekCWxG2mX9yqcTlqHVPueAVD0DACCzrw= ARC-Message-Signature: i=1; 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Tue, 12 Dec 2023 21:19:53 -0800 (PST) From: Akihiko Odaki Date: Wed, 13 Dec 2023 14:19:30 +0900 Subject: [PATCH v7 2/4] target/riscv: Remove misa_mxl validation MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231213-riscv-v7-2-a760156a337f@daynix.com> References: <20231213-riscv-v7-0-a760156a337f@daynix.com> In-Reply-To: <20231213-riscv-v7-0-a760156a337f@daynix.com> To: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , =?utf-8?q?Alex_Benn=C3=A9e?= , Mikhail Tyutin , Aleksandr Anenkov , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Fabiano Rosas Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::d36; envelope-from=akihiko.odaki@daynix.com; helo=mail-io1-xd36.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1702444841267100005 It is initialized with a simple assignment and there is little room for error. In fact, the validation is even more complex. Signed-off-by: Akihiko Odaki Acked-by: LIU Zhiwei Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8a35683a345d..ee17f65afb60 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -148,7 +148,7 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState = *env, Error **errp) } } =20 -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); CPUClass *cc =3D CPU_CLASS(mcc); @@ -168,11 +168,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu,= Error **errp) default: g_assert_not_reached(); } - - if (env->misa_mxl_max !=3D env->misa_mxl) { - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); - return; - } } =20 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) @@ -673,7 +668,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) static bool tcg_cpu_realize(CPUState *cs, Error **errp) { RISCVCPU *cpu =3D RISCV_CPU(cs); - Error *local_err =3D NULL; =20 if (!riscv_cpu_tcg_compatible(cpu)) { g_autofree char *name =3D riscv_cpu_get_name(cpu); @@ -682,14 +676,11 @@ static bool tcg_cpu_realize(CPUState *cs, Error **err= p) return false; } =20 - riscv_cpu_validate_misa_mxl(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return false; - } + riscv_cpu_validate_misa_mxl(cpu); =20 #ifndef CONFIG_USER_ONLY CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; =20 CPU(cs)->tcg_cflags |=3D CF_PCREL; =20 --=20 2.43.0 From nobody Wed Nov 19 18:38:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1702444841; cv=none; d=zohomail.com; s=zohoarc; b=OOk/dE65tghVuKysMnNyfusC12eqcI0QYhXaNopEaH+0L3gP7hzxyuPgEq5OdPI1nZTUBb5wpKA0hD/WzhmoOd8iKF8UrM5bhoRivH2fI8KN134GdDKc6dAZpKVkCy+5cp8H7i4O4chI5XA/vamUolTlZOVr0Syb+91NxTmNS9A= ARC-Message-Signature: i=1; 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Tue, 12 Dec 2023 21:19:58 -0800 (PST) From: Akihiko Odaki Date: Wed, 13 Dec 2023 14:19:31 +0900 Subject: [PATCH v7 3/4] target/riscv: Move misa_mxl_max to class MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231213-riscv-v7-3-a760156a337f@daynix.com> References: <20231213-riscv-v7-0-a760156a337f@daynix.com> In-Reply-To: <20231213-riscv-v7-0-a760156a337f@daynix.com> To: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , =?utf-8?q?Alex_Benn=C3=A9e?= , Mikhail Tyutin , Aleksandr Anenkov , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Fabiano Rosas Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::c31; envelope-from=akihiko.odaki@daynix.com; helo=mail-oo1-xc31.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1702444843318100011 misa_mxl_max is common for all instances of a RISC-V CPU class so they are better put into class. Signed-off-by: Akihiko Odaki Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 4 +- target/riscv/cpu.c | 118 +++++++++++++++++++++++------------------= ---- target/riscv/gdbstub.c | 12 +++-- target/riscv/kvm/kvm-cpu.c | 10 ++-- target/riscv/machine.c | 7 ++- target/riscv/tcg/tcg-cpu.c | 12 ++--- target/riscv/translate.c | 3 +- 7 files changed, 87 insertions(+), 79 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d74b361be641..060b7f69a743 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -169,7 +169,6 @@ struct CPUArchState { =20 /* RISCVMXL, but uint32_t for vmstate migration */ uint32_t misa_mxl; /* current mxl */ - uint32_t misa_mxl_max; /* max mxl for this cpu */ uint32_t misa_ext; /* current extensions */ uint32_t misa_ext_mask; /* max ext for this cpu */ uint32_t xl; /* current xlen */ @@ -450,6 +449,7 @@ struct RISCVCPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; + uint32_t misa_mxl_max; /* max mxl for this cpu */ }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) @@ -756,7 +756,7 @@ enum riscv_pmu_event_idx { /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); -void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); +void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); =20 typedef struct RISCVCPUMultiExtConfig { const char *name; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 83c7c0cf07be..2ab61df2217e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -274,9 +274,8 @@ const char *riscv_cpu_get_trap_name(target_ulong cause,= bool async) } } =20 -void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext) { - env->misa_mxl_max =3D env->misa_mxl =3D mxl; env->misa_ext_mask =3D env->misa_ext =3D ext; } =20 @@ -378,11 +377,7 @@ static void riscv_any_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; -#if defined(TARGET_RISCV32) - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | = RVU); -#elif defined(TARGET_RISCV64) - riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | = RVU); -#endif + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU); =20 #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), @@ -403,16 +398,14 @@ static void riscv_max_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - RISCVMXL mlx =3D MXL_RV64; =20 -#ifdef TARGET_RISCV32 - mlx =3D MXL_RV32; -#endif - riscv_cpu_set_misa(env, mlx, 0); env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), mlx =3D=3D MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); +#ifdef TARGET_RISCV32 + set_satp_mode_max_supported(cpu, VM_1_10_SV32); +#else + set_satp_mode_max_supported(cpu, VM_1_10_SV57); +#endif #endif } =20 @@ -420,8 +413,6 @@ static void riscv_max_cpu_init(Object *obj) static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV64, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -433,8 +424,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - riscv_cpu_set_misa(env, MXL_RV64, - RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | = RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -452,7 +442,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -469,7 +459,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_11_0; =20 cpu->cfg.ext_zfa =3D true; @@ -500,7 +490,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); env->priv_ver =3D PRIV_VERSION_1_12_0; =20 /* Enable ISA extensions */ @@ -544,8 +534,6 @@ static void rv128_base_cpu_init(Object *obj) exit(EXIT_FAILURE); } CPURISCVState *env =3D &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV128, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -556,8 +544,6 @@ static void rv128_base_cpu_init(Object *obj) static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV32, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -569,8 +555,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - riscv_cpu_set_misa(env, MXL_RV32, - RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | = RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -588,7 +573,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -605,7 +590,7 @@ static void rv32_ibex_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -622,7 +607,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -845,7 +830,7 @@ static void riscv_cpu_reset_hold(Object *obj) mcc->parent_phases.hold(obj); } #ifndef CONFIG_USER_ONLY - env->misa_mxl =3D env->misa_mxl_max; + env->misa_mxl =3D mcc->misa_mxl_max; env->priv =3D PRV_M; env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); if (env->misa_mxl > MXL_RV32) { @@ -1213,6 +1198,12 @@ static void riscv_cpu_post_init(Object *obj) =20 static void riscv_cpu_init(Object *obj) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(obj); + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + + env->misa_mxl =3D mcc->misa_mxl_max; + #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); @@ -1657,7 +1648,7 @@ static void cpu_get_marchid(Object *obj, Visitor *v, = const char *name, visit_type_bool(v, name, &value, errp); } =20 -static void riscv_cpu_class_init(ObjectClass *c, void *data) +static void riscv_cpu_common_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); CPUClass *cc =3D CPU_CLASS(c); @@ -1699,6 +1690,13 @@ static void riscv_cpu_class_init(ObjectClass *c, voi= d *data) device_class_set_props(dc, riscv_cpu_properties); } =20 +static void riscv_cpu_class_init(ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + + mcc->misa_mxl_max =3D (uint32_t)(uintptr_t)data; +} + static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) { @@ -1764,18 +1762,22 @@ void riscv_cpu_list(void) g_slist_free(list); } =20 -#define DEFINE_CPU(type_name, initfn) \ - { \ - .name =3D type_name, \ - .parent =3D TYPE_RISCV_CPU, \ - .instance_init =3D initfn \ +#define DEFINE_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name =3D (type_name), \ + .parent =3D TYPE_RISCV_CPU, \ + .instance_init =3D (initfn), \ + .class_init =3D riscv_cpu_class_init, \ + .class_data =3D (void *)(misa_mxl_max) \ } =20 -#define DEFINE_DYNAMIC_CPU(type_name, initfn) \ - { \ - .name =3D type_name, \ - .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ - .instance_init =3D initfn \ +#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name =3D (type_name), \ + .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ + .instance_init =3D (initfn), \ + .class_init =3D riscv_cpu_class_init, \ + .class_data =3D (void *)(misa_mxl_max) \ } =20 static const TypeInfo riscv_cpu_type_infos[] =3D { @@ -1788,29 +1790,31 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .instance_post_init =3D riscv_cpu_post_init, .abstract =3D true, .class_size =3D sizeof(RISCVCPUClass), - .class_init =3D riscv_cpu_class_init, + .class_init =3D riscv_cpu_common_class_init, }, { .name =3D TYPE_RISCV_DYNAMIC_CPU, .parent =3D TYPE_RISCV_CPU, .abstract =3D true, }, - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init= ), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32, riscv_any_cpu_in= it), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_in= it), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cp= u_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nomm= u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cp= u_init), #elif defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_in= it), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_in= it), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cp= u_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cp= u_init), + DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cp= u_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_= cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_c= pu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_i= nit), #endif }; =20 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 58b3ace0fe92..365040228a12 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -49,6 +49,7 @@ static const struct TypeSize vec_lanes[] =3D { =20 int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; target_ulong tmp; @@ -61,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) return 0; } =20 - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: return gdb_get_reg32(mem_buf, tmp); case MXL_RV64: @@ -75,12 +76,13 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) =20 int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; int length =3D 0; target_ulong tmp; =20 - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: tmp =3D (int32_t)ldl_p(mem_buf); length =3D 4; @@ -214,11 +216,12 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, u= int8_t *mem_buf, int n) =20 static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; GString *s =3D g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize =3D 16 << env->misa_mxl_max; + int bitsize =3D 16 << mcc->misa_mxl_max; int i; =20 #if !defined(CONFIG_USER_ONLY) @@ -310,6 +313,7 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, i= nt base_reg) =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; if (env->misa_ext & RVD) { @@ -326,7 +330,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) ricsv_gen_dynamic_vector_xml(cs, base_reg= ), "riscv-vector.xml", 0); } - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 45b6cf1cfa04..f5624e553b65 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1501,14 +1501,14 @@ static void kvm_cpu_accel_register_types(void) } type_init(kvm_cpu_accel_register_types); =20 -static void riscv_host_cpu_init(Object *obj) +static void riscv_host_cpu_class_init(ObjectClass *c, void *data) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); =20 #if defined(TARGET_RISCV32) - env->misa_mxl_max =3D env->misa_mxl =3D MXL_RV32; + mcc->misa_mxl_max =3D MXL_RV32; #elif defined(TARGET_RISCV64) - env->misa_mxl_max =3D env->misa_mxl =3D MXL_RV64; + mcc->misa_mxl_max =3D MXL_RV64; #endif } =20 @@ -1516,7 +1516,7 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU_HOST, .parent =3D TYPE_RISCV_CPU, - .instance_init =3D riscv_host_cpu_init, + .class_init =3D riscv_host_cpu_class_init, } }; =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index fdde243e0409..4c8d9a665952 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -178,10 +178,9 @@ static const VMStateDescription vmstate_pointermasking= =3D { =20 static bool rv128_needed(void *opaque) { - RISCVCPU *cpu =3D opaque; - CPURISCVState *env =3D &cpu->env; + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(opaque); =20 - return env->misa_mxl_max =3D=3D MXL_RV128; + return mcc->misa_mxl_max =3D=3D MXL_RV128; } =20 static const VMStateDescription vmstate_rv128 =3D { @@ -372,7 +371,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.vext_ver, RISCVCPU), VMSTATE_UINT32(env.misa_mxl, RISCVCPU), VMSTATE_UINT32(env.misa_ext, RISCVCPU), - VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), + VMSTATE_UNUSED(4), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_BOOL(env.virt_enabled, RISCVCPU), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ee17f65afb60..7f6712c81a49 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -152,10 +152,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); CPUClass *cc =3D CPU_CLASS(mcc); - CPURISCVState *env =3D &cpu->env; =20 /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { #ifdef TARGET_RISCV64 case MXL_RV64: case MXL_RV128: @@ -274,6 +273,7 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVC= PU *cpu) */ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 @@ -454,7 +454,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } } @@ -462,7 +462,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } if (riscv_has_ext(env, RVD)) { @@ -470,7 +470,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) } } =20 - if (env->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { + if (mcc->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension is only relevant to RV32"); return; } @@ -956,7 +956,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) const RISCVCPUMultiExtConfig *prop; =20 /* Enable RVG, RVJ and RVV that are disabled by default */ - riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV= ); + riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { isa_ext_update_enabled(cpu, prop->offset, true); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f0be79bb160b..7e383c5eebfd 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1167,6 +1167,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPURISCVState *env =3D cpu_env(cs); + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); uint32_t tb_flags =3D ctx->base.tb->flags; =20 @@ -1188,7 +1189,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->cfg_vta_all_1s =3D cpu->cfg.rvv_ta_all_1s; ctx->vstart_eq_zero =3D FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); - ctx->misa_mxl_max =3D env->misa_mxl_max; + ctx->misa_mxl_max =3D mcc->misa_mxl_max; ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; --=20 2.43.0 From nobody Wed Nov 19 18:38:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1702444848; cv=none; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::32b; envelope-from=akihiko.odaki@daynix.com; helo=mail-ot1-x32b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1702444849465100001 misa_mxl_max is now a class member and initialized only once for each class. This also moves the initialization of gdb_core_xml_file which will be referenced before realization in the future. Signed-off-by: Akihiko Odaki Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 21 +++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 23 ----------------------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2ab61df2217e..b799f1336041 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1247,6 +1247,26 @@ static const MISAExtInfo misa_ext_info_arr[] =3D { MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), }; =20 +static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc) +{ + CPUClass *cc =3D CPU_CLASS(mcc); + + /* Validate that MISA_MXL is set properly. */ + switch (mcc->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } +} + static int riscv_validate_misa_info_idx(uint32_t bit) { int idx; @@ -1695,6 +1715,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); =20 mcc->misa_mxl_max =3D (uint32_t)(uintptr_t)data; + riscv_cpu_validate_misa_mxl(mcc); } =20 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 7f6712c81a49..eb243e011ca3 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -148,27 +148,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState= *env, Error **errp) } } =20 -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); - CPUClass *cc =3D CPU_CLASS(mcc); - - /* Validate that MISA_MXL is set properly. */ - switch (mcc->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } -} - static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; @@ -676,8 +655,6 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) return false; } =20 - riscv_cpu_validate_misa_mxl(cpu); - #ifndef CONFIG_USER_ONLY CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; --=20 2.43.0