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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 30/33] hw/arm/npcm7xx: Let the A9MPcore create/wire the CPU cores Date: Tue, 12 Dec 2023 17:29:30 +0100 Message-ID: <20231212162935.42910-31-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212162935.42910-1-philmd@linaro.org> References: <20231212162935.42910-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1702398851357100007 Set the properties on the mpcore object to let it create and wire the CPU cores. Remove the redundant code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/npcm7xx.h | 1 - hw/arm/npcm7xx.c | 48 ++++++++++------------------------------ 2 files changed, 12 insertions(+), 37 deletions(-) diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 7abbf85cbf..e0737fa4de 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -80,7 +80,6 @@ typedef struct NPCM7xxMachineClass { struct NPCM7xxState { DeviceState parent; =20 - ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS]; A9MPPrivState a9mpcore; =20 MemoryRegion sram; diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 5b6e968fa9..1154a0f0a5 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -363,9 +363,11 @@ static struct arm_boot_info npcm7xx_binfo =3D { =20 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc) { + CortexMPPrivState *mp =3D CORTEX_MPCORE_PRIV(&soc->a9mpcore); + npcm7xx_binfo.ram_size =3D machine->ram_size; =20 - arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo); + arm_load_kernel(mp->cpu[0], machine, &npcm7xx_binfo); } =20 static void npcm7xx_init_fuses(NPCM7xxState *s) @@ -400,11 +402,6 @@ static void npcm7xx_init(Object *obj) NPCM7xxState *s =3D NPCM7XX(obj); int i; =20 - for (i =3D 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { - object_initialize_child(obj, "cpu[*]", &s->cpu[i], - ARM_CPU_TYPE_NAME("cortex-a9")); - } - object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_P= RIV); object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR); object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), @@ -471,40 +468,19 @@ static void npcm7xx_realize(DeviceState *dev, Error *= *errp) return; } =20 - /* CPUs */ - for (i =3D 0; i < nc->num_cpus; i++) { - object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", - arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPU= S), - &error_abort); - object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", - NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); - object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, - &error_abort); - - /* Disable security extensions. */ - object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, - &error_abort); - - if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { - return; - } - } - /* A9MPCORE peripherals. Can only fail if we pass bad parameters here.= */ - object_property_set_int(OBJECT(&s->a9mpcore), "num-cores", nc->num_cpu= s, - &error_abort); - object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_I= RQ, - &error_abort); + qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cores", nc->num_cpus); + qdev_prop_set_string(DEVICE(&s->a9mpcore), "cpu-type", + ARM_CPU_TYPE_NAME("cortex-a9")); + /* Disable security extensions. */ + qdev_prop_set_bit(DEVICE(&s->a9mpcore), "cpu-has-el3", false); + qdev_prop_set_uint64(DEVICE(&s->a9mpcore), "cpu-reset-cbar", + NPCM7XX_GIC_CPU_IF_ADDR); + qdev_prop_set_bit(DEVICE(&s->a9mpcore), "cpu-reset-hivecs", true); + qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "gic-spi-num", NPCM7XX_NUM_= IRQ); sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA); =20 - for (i =3D 0; i < nc->num_cpus; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, - qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IR= Q)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus, - qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FI= Q)); - } - /* L2 cache controller */ sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL); =20 --=20 2.41.0