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([152.234.124.8]) by smtp.gmail.com with ESMTPSA id sk13-20020a17090b2dcd00b002864c14063fsm2190709pjb.20.2023.12.08.10.38.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 10:38:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1702060738; x=1702665538; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3JyIYvn4p8JdAgrQKCIVuzNkyuz3/M0LL3H7xDfwCk8=; b=U+xDpXGU3Pb+Egbo9hW+mjrjro29lG1OAkefTXeEMkNmSmR/QLfzw+4FAWr/B7Ij8X s5l9tYes5jQ+N4apvL2/5at52FQGNp8a4d9GCP+spE8CvolZRljoIyU3M6eD3VdRJg+2 Q3oDPMK4+4K//Nic3ReRV6uAmOYOElE4Z08ivaWi5wRhEus3Hy52bHnWAl5cmsK05Vg/ bosa9HZX+qiTLbEz6FgupQLw0F30AcPSWCAVz3WVG0p4GbpTd8LXatHe61ScrmO+KIXW Gic/oXrLOl4R3mXPMFaj5qPSeKmkcCV9RcCSOPwUA+umowvpwXX0wtSRa0IyhXb5DKSA By9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702060738; x=1702665538; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3JyIYvn4p8JdAgrQKCIVuzNkyuz3/M0LL3H7xDfwCk8=; b=d8ocjEMCp0wbcsGxWa5ydZcAGtdtXMAxecedzF0xiD0HfzftFM8xOQJKcOA2TxSJAk yHVkUtimRY0jWjfIkMtlqEtK4AAMakqbS1ryv9gbL1Xe20OEyIF9f0qHkwn6JlGi2XkR FYjBifEm3ogVvOcqE6qiVcd1zKZPEXdylo0pZBj1VeX7QhqONL9gKsYYZapiCPpM8mLM WhbUQLQJX+QdlOcCU2wy8kA+7cK3TTG58p2JuXNJKRNmHxk1LlUXGNNf128bnjnr1zBL 0nPmIo2KIx4+6h1beGNqdvhg2OC0Cd6ABUJu10BHUZ//SGWQNVJRPXa4/rPgIf9XzIWu y0Ow== X-Gm-Message-State: AOJu0YwR0aV4q16F0wtxxgIkpJEnON9shLWeb+2Dev9CdkmCR283bStn x8z2g9hYZUSAc6UZ/6WrOpZoVhMDffQJ31e5on4= X-Google-Smtp-Source: AGHT+IEyMRi3iIzHH3aoWnmsNGAjG2AFYPHP64TxiSSDk+a/qxINo8w2yNZRA8N1wVL1BbhHS6Uy3w== X-Received: by 2002:a17:90b:3591:b0:286:f040:3a13 with SMTP id mm17-20020a17090b359100b00286f0403a13mr500454pjb.19.1702060738424; Fri, 08 Dec 2023 10:38:58 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 5/5] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong() Date: Fri, 8 Dec 2023 15:38:35 -0300 Message-ID: <20231208183835.2411523-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231208183835.2411523-1-dbarboza@ventanamicro.com> References: <20231208183835.2411523-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1702060807932100016 Content-Type: text/plain; charset="utf-8" kvm_riscv_reg_id() returns an id encoded with an ulong size, i.e. an u32 size when running TARGET_RISCV32 and u64 when running TARGET_RISCV64. Rename it to kvm_riscv_reg_id_ulong() to enhance code readability. It'll be in line with the existing kvm_riscv_reg_id_() helpers. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 40 ++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 19 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 11797338ec..62a1e51f0a 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -54,7 +54,7 @@ void riscv_kvm_aplic_request(void *opaque, int irq, int l= evel) =20 static bool cap_has_mp_state; =20 -static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, +static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type, uint64_t idx) { uint64_t id =3D KVM_REG_RISCV | type | idx; @@ -82,15 +82,17 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uin= t64_t idx) return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; } =20 -#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_COR= E, \ - KVM_REG_RISCV_CORE_REG(name)) +#define RISCV_CORE_REG(env, name) \ + kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \ + KVM_REG_RISCV_CORE_REG(name)) =20 -#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR,= \ - KVM_REG_RISCV_CSR_REG(name)) +#define RISCV_CSR_REG(env, name) \ + kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \ + KVM_REG_RISCV_CSR_REG(name)) =20 #define RISCV_CONFIG_REG(env, name) \ - kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, \ - KVM_REG_RISCV_CONFIG_REG(name)) + kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \ + KVM_REG_RISCV_CONFIG_REG(name)) =20 #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ KVM_REG_RISCV_TIMER_REG(name)) @@ -216,8 +218,8 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu= , CPUState *cs) =20 /* If we're here we're going to disable the MISA bit */ reg =3D 0; - id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, - misa_cfg->kvm_reg_id); + id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, + misa_cfg->kvm_reg_id); ret =3D kvm_set_one_reg(cs, id, ®); if (ret !=3D 0) { /* @@ -378,8 +380,8 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *= cpu, CPUState *cs) continue; } =20 - id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, - multi_ext_cfg->kvm_reg_id); + id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, + multi_ext_cfg->kvm_reg_id); reg =3D kvm_cpu_cfg_get(cpu, multi_ext_cfg); ret =3D kvm_set_one_reg(cs, id, ®); if (ret !=3D 0) { @@ -509,7 +511,7 @@ static int kvm_riscv_get_regs_core(CPUState *cs) env->pc =3D reg; =20 for (i =3D 1; i < 32; i++) { - uint64_t id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); + uint64_t id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); ret =3D kvm_get_one_reg(cs, id, ®); if (ret) { return ret; @@ -534,7 +536,7 @@ static int kvm_riscv_put_regs_core(CPUState *cs) } =20 for (i =3D 1; i < 32; i++) { - uint64_t id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i); + uint64_t id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i); reg =3D env->gpr[i]; ret =3D kvm_set_one_reg(cs, id, ®); if (ret) { @@ -810,8 +812,8 @@ static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu,= KVMScratchCPU *kvmcpu, struct kvm_one_reg reg; int ret; =20 - reg.id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, - cbomz_cfg->kvm_reg_id); + reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, + cbomz_cfg->kvm_reg_id); reg.addr =3D (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg); ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { @@ -832,8 +834,8 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU *cp= u, KVMCPUConfig *multi_ext_cfg =3D &kvm_multi_ext_cfgs[i]; struct kvm_one_reg reg; =20 - reg.id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT, - multi_ext_cfg->kvm_reg_id); + reg.id =3D kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT, + multi_ext_cfg->kvm_reg_id); reg.addr =3D (uint64_t)&val; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { @@ -925,8 +927,8 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, = KVMScratchCPU *kvmcpu) =20 for (i =3D 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { multi_ext_cfg =3D &kvm_multi_ext_cfgs[i]; - reg_id =3D kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT, - multi_ext_cfg->kvm_reg_id); + reg_id =3D kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT, + multi_ext_cfg->kvm_reg_id); reg_search =3D bsearch(®_id, reglist->reg, reglist->n, sizeof(uint64_t), uint64_cmp); if (!reg_search) { --=20 2.41.0