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([152.234.124.8]) by smtp.gmail.com with ESMTPSA id sk13-20020a17090b2dcd00b002864c14063fsm2190709pjb.20.2023.12.08.10.38.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 10:38:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1702060735; x=1702665535; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NDUfXfcWCozOr3YgPfrQcgZ6dHfOfa/IJlJz1rUOmVs=; b=Lh4uGZHE7CCxi8LRDEOsVbSVjUKk0U79gztgTYBR1/vIdCAuoPfmQxENj04fiRAN/8 ErL8m4tqtGUwie7daQqO+KAtCG3whu0mDRSxOvV7Vkz5HS1vUfgV7XJGUH8l1zjeBHIY LggUnV2oKU87EYeBxKOb2RDYSvBgvUvOr8b08wxRsbxkJBTyq4CuhZVUmxvwLcGxmiRs N2vR3705uawMkH4kg3quZuZl95RaDm0EtU288+2XDpPe6BBfkE07jGF84vSgHlvZYatx mv8Nxg+lS310CdqotRvSR0/9RTS7DGBQ02NeblzpKC6eWEM0Sy2j/fKNiOziJPAwgjkV RuJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702060735; x=1702665535; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NDUfXfcWCozOr3YgPfrQcgZ6dHfOfa/IJlJz1rUOmVs=; b=TdURLj2V8d01337+URNdmSCGLI6t83fXl2Bs+6XX2wEByYoNZhFmdN/eIaImM/+xCb tGKjNuUPiZ+A8tGYoPFVkX+IGRtVnTw48qavGQPLcWb2kYEPRHvATp3tlmTqrv4tfyvA AE0ZjbQqCN7zuZn8l+zxxYK0/H+jJ1oH6SqplPYlP0ICidijSVX+yXg9FMfGCaINjyKA UyPNVRonfzyZogJT9JQQrMrmukABW9olhSYVD9YsUiWa+BUcyzJ6RHID6EFY4mbPuUx+ Trwds2OE1vLlalh3tKryt4icPX+vokBxVY7nN7/sEx9AghJc06MGfoIWqbzGvA59P1MW Z7Ag== X-Gm-Message-State: AOJu0YyRudI7crgZIDsYqQtba4C+tgf6W2uyVgkn2AxKutOhOwW2QBgI JJoJR/81dAWttMjzokX4tmyRgVNl6N3JYrdiOQc= X-Google-Smtp-Source: AGHT+IF5vNV7Ckzv3fFEibjYzWgBzqp+D4YZC+h1rf/ORom4P6rwIkG+3vr2+xs783PpYkpqrTZtOQ== X-Received: by 2002:a17:90a:3482:b0:286:6cc1:8670 with SMTP id p2-20020a17090a348200b002866cc18670mr446596pjb.85.1702060735222; Fri, 08 Dec 2023 10:38:55 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH for-9.0 4/5] target/riscv/kvm: add RISCV_CONFIG_REG() Date: Fri, 8 Dec 2023 15:38:34 -0300 Message-ID: <20231208183835.2411523-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231208183835.2411523-1-dbarboza@ventanamicro.com> References: <20231208183835.2411523-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1702060822349100001 Content-Type: text/plain; charset="utf-8" Create a RISCV_CONFIG_REG() macro, similar to what other regs use, to hide away some of the boilerplate. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 476e5d4b3d..11797338ec 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -88,6 +88,10 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint= 64_t idx) #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR,= \ KVM_REG_RISCV_CSR_REG(name)) =20 +#define RISCV_CONFIG_REG(env, name) \ + kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, \ + KVM_REG_RISCV_CONFIG_REG(name)) + #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ KVM_REG_RISCV_TIMER_REG(name)) =20 @@ -756,24 +760,21 @@ static void kvm_riscv_init_machine_ids(RISCVCPU *cpu,= KVMScratchCPU *kvmcpu) struct kvm_one_reg reg; int ret; =20 - reg.id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, - KVM_REG_RISCV_CONFIG_REG(mvendorid)); + reg.id =3D RISCV_CONFIG_REG(env, mvendorid); reg.addr =3D (uint64_t)&cpu->cfg.mvendorid; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { error_report("Unable to retrieve mvendorid from host, error %d", r= et); } =20 - reg.id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, - KVM_REG_RISCV_CONFIG_REG(marchid)); + reg.id =3D RISCV_CONFIG_REG(env, marchid); reg.addr =3D (uint64_t)&cpu->cfg.marchid; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { error_report("Unable to retrieve marchid from host, error %d", ret= ); } =20 - reg.id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, - KVM_REG_RISCV_CONFIG_REG(mimpid)); + reg.id =3D RISCV_CONFIG_REG(env, mimpid); reg.addr =3D (uint64_t)&cpu->cfg.mimpid; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); if (ret !=3D 0) { @@ -788,8 +789,7 @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, struct kvm_one_reg reg; int ret; =20 - reg.id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, - KVM_REG_RISCV_CONFIG_REG(isa)); + reg.id =3D RISCV_CONFIG_REG(env, isa); reg.addr =3D (uint64_t)&env->misa_ext_mask; ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); =20 @@ -1094,8 +1094,7 @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CP= UState *cs) uint64_t id; int ret; =20 - id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, - KVM_REG_RISCV_CONFIG_REG(mvendorid)); + id =3D RISCV_CONFIG_REG(env, mvendorid); /* * cfg.mvendorid is an uint32 but a target_ulong will * be written. Assign it to a target_ulong var to avoid @@ -1107,15 +1106,13 @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, = CPUState *cs) return ret; } =20 - id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, - KVM_REG_RISCV_CONFIG_REG(marchid)); + id =3D RISCV_CONFIG_REG(env, marchid); ret =3D kvm_set_one_reg(cs, id, &cpu->cfg.marchid); if (ret !=3D 0) { return ret; } =20 - id =3D kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, - KVM_REG_RISCV_CONFIG_REG(mimpid)); + id =3D RISCV_CONFIG_REG(env, mimpid); ret =3D kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); =20 return ret; --=20 2.41.0