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Fri, 08 Dec 2023 03:35:50 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi , Peter Maydell , qemu-block@nongnu.org, Pavel Dovgalyuk , Fam Zheng , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 3/6] sysemu/cpu-timers: Introduce ICountMode enumerator Date: Fri, 8 Dec 2023 12:35:25 +0100 Message-ID: <20231208113529.74067-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231208113529.74067-1-philmd@linaro.org> References: <20231208113529.74067-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1702035489977100005 Rather than having to lookup for what the 0, 1, 2, ... icount values are, use a enum definition. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/sysemu/cpu-timers.h | 20 +++++++++++++------- accel/tcg/icount-common.c | 16 +++++++--------- stubs/icount.c | 2 +- system/cpu-timers.c | 2 +- target/arm/helper.c | 3 ++- 5 files changed, 24 insertions(+), 19 deletions(-) diff --git a/include/sysemu/cpu-timers.h b/include/sysemu/cpu-timers.h index b70dc7692d..3f05f29b10 100644 --- a/include/sysemu/cpu-timers.h +++ b/include/sysemu/cpu-timers.h @@ -17,18 +17,24 @@ void cpu_timers_init(void); =20 /* icount - Instruction Counter API */ =20 -/* - * icount enablement state: +/** + * ICountMode: icount enablement state: * - * 0 =3D Disabled - Do not count executed instructions. - * 1 =3D Enabled - Fixed conversion of insn to ns via "shift" option - * 2 =3D Enabled - Runtime adaptive algorithm to compute shift + * @ICOUNT_DISABLED: Disabled - Do not count executed instructions. + * @ICOUNT_PRECISE: Enabled - Fixed conversion of insn to ns via "shift" o= ption + * @ICOUNT_ADAPTATIVE: Enabled - Runtime adaptive algorithm to compute shi= ft */ +typedef enum { + ICOUNT_DISABLED =3D 0, + ICOUNT_PRECISE, + ICOUNT_ADAPTATIVE, +} ICountMode; + #ifdef CONFIG_TCG -extern int use_icount; +extern ICountMode use_icount; #define icount_enabled() (use_icount) #else -#define icount_enabled() 0 +#define icount_enabled() ICOUNT_DISABLED #endif =20 /* diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c index dc69d6a4c6..f0f8fc7f1c 100644 --- a/accel/tcg/icount-common.c +++ b/accel/tcg/icount-common.c @@ -49,21 +49,19 @@ static bool icount_sleep =3D true; /* Arbitrarily pick 1MIPS as the minimum allowable speed. */ #define MAX_ICOUNT_SHIFT 10 =20 -/* - * 0 =3D Do not count executed instructions. - * 1 =3D Fixed conversion of insn to ns via "shift" option - * 2 =3D Runtime adaptive algorithm to compute shift - */ -int use_icount; +/* Do not count executed instructions */ +ICountMode use_icount =3D ICOUNT_DISABLED; =20 static void icount_enable_precise(void) { - use_icount =3D 1; + /* Fixed conversion of insn to ns via "shift" option */ + use_icount =3D ICOUNT_PRECISE; } =20 static void icount_enable_adaptive(void) { - use_icount =3D 2; + /* Runtime adaptive algorithm to compute shift */ + use_icount =3D ICOUNT_ADAPTATIVE; } =20 /* @@ -256,7 +254,7 @@ static void icount_warp_rt(void) int64_t warp_delta; =20 warp_delta =3D clock - timers_state.vm_clock_warp_start; - if (icount_enabled() =3D=3D 2) { + if (icount_enabled() =3D=3D ICOUNT_ADAPTATIVE) { /* * In adaptive mode, do not let QEMU_CLOCK_VIRTUAL run too far * ahead of real time (it might already be ahead so careful not diff --git a/stubs/icount.c b/stubs/icount.c index 014ae5d8e4..7055c13725 100644 --- a/stubs/icount.c +++ b/stubs/icount.c @@ -3,7 +3,7 @@ =20 /* icount - Instruction Counter API */ =20 -int use_icount; +ICountMode use_icount =3D ICOUNT_DISABLED; =20 void icount_update(CPUState *cpu) { diff --git a/system/cpu-timers.c b/system/cpu-timers.c index 7452d97b67..6befb82e48 100644 --- a/system/cpu-timers.c +++ b/system/cpu-timers.c @@ -154,7 +154,7 @@ static bool adjust_timers_state_needed(void *opaque) =20 static bool icount_shift_state_needed(void *opaque) { - return icount_enabled() =3D=3D 2; + return icount_enabled() =3D=3D ICOUNT_ADAPTATIVE; } =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 2746d3fdac..adb0960bba 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -934,7 +934,8 @@ static int64_t cycles_ns_per(uint64_t cycles) =20 static bool instructions_supported(CPUARMState *env) { - return icount_enabled() =3D=3D 1; /* Precise instruction counting */ + /* Precise instruction counting */ + return icount_enabled() =3D=3D ICOUNT_PRECISE; } =20 static uint64_t instructions_get_count(CPUARMState *env) --=20 2.41.0