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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=serg.oker@gmail.com; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1702003145712100001 Content-Type: text/plain; charset="utf-8" Pre setup for BCM2838 introduction Signed-off-by: Sergey Kambalin Reviewed-by: Peter Maydell --- hw/arm/bcm2836.c | 102 ++++++++++++++++++++++----------------- hw/arm/raspi.c | 2 +- include/hw/arm/bcm2836.h | 26 +++++++++- 3 files changed, 83 insertions(+), 47 deletions(-) diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 166dc896c0..66a2b57b38 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -29,12 +29,12 @@ struct BCM283XClass { }; =20 static Property bcm2836_enabled_cores_property =3D - DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, 0); + DEFINE_PROP_UINT32("enabled-cpus", BCM283XBaseState, enabled_cpus, 0); =20 -static void bcm2836_init(Object *obj) +static void bcm283x_base_init(Object *obj) { - BCM283XState *s =3D BCM283X(obj); - BCM283XClass *bc =3D BCM283X_GET_CLASS(obj); + BCM283XBaseState *s =3D BCM283X_BASE(obj); + BCM283XBaseClass *bc =3D BCM283X_BASE_GET_CLASS(obj); int n; =20 for (n =3D 0; n < bc->core_count; n++) { @@ -50,6 +50,11 @@ static void bcm2836_init(Object *obj) object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL); } +} + +static void bcm283x_init(Object *obj) +{ + BCM283XState *s =3D BCM283X(obj); =20 object_initialize_child(obj, "peripherals", &s->peripherals, TYPE_BCM2835_PERIPHERALS); @@ -61,10 +66,11 @@ static void bcm2836_init(Object *obj) "vcram-size"); } =20 -static bool bcm283x_common_realize(DeviceState *dev, Error **errp) +bool bcm283x_common_realize(DeviceState *dev, Error **errp) { BCM283XState *s =3D BCM283X(dev); - BCM283XClass *bc =3D BCM283X_GET_CLASS(dev); + BCM283XBaseState *s_base =3D BCM283X_BASE(dev); + BCM283XBaseClass *bc =3D BCM283X_BASE_GET_CLASS(dev); Object *obj; =20 /* common peripherals from bcm2835 */ @@ -77,96 +83,98 @@ static bool bcm283x_common_realize(DeviceState *dev, Er= ror **errp) return false; } =20 - object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->peripherals), - "sd-bus"); + object_property_add_alias(OBJECT(s_base), "sd-bus", + OBJECT(&s->peripherals), "sd-bus"); =20 - sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, - bc->peri_base, 1); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), + 0, bc->peri_base, 1); return true; } =20 static void bcm2835_realize(DeviceState *dev, Error **errp) { BCM283XState *s =3D BCM283X(dev); + BCM283XBaseState *s_base =3D BCM283X_BASE(dev); =20 if (!bcm283x_common_realize(dev, errp)) { return; } =20 - if (!qdev_realize(DEVICE(&s->cpu[0].core), NULL, errp)) { + if (!qdev_realize(DEVICE(&s_base->cpu[0].core), NULL, errp)) { return; } =20 /* Connect irq/fiq outputs from the interrupt controller. */ sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, - qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_IRQ)); + qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, - qdev_get_gpio_in(DEVICE(&s->cpu[0].core), ARM_CPU_FIQ)); + qdev_get_gpio_in(DEVICE(&s_base->cpu[0].core), ARM_CPU_FIQ)); } =20 static void bcm2836_realize(DeviceState *dev, Error **errp) { - BCM283XState *s =3D BCM283X(dev); - BCM283XClass *bc =3D BCM283X_GET_CLASS(dev); int n; + BCM283XState *s =3D BCM283X(dev); + BCM283XBaseState *s_base =3D BCM283X_BASE(dev); + BCM283XBaseClass *bc =3D BCM283X_BASE_GET_CLASS(dev); =20 if (!bcm283x_common_realize(dev, errp)) { return; } =20 /* bcm2836 interrupt controller (and mailboxes, etc.) */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) { + if (!sysbus_realize(SYS_BUS_DEVICE(&s_base->control), errp)) { return; } =20 - sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s_base->control), 0, bc->ctrl_base); =20 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 0, - qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-irq", 0)); + qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-irq", 0)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, - qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); + qdev_get_gpio_in_named(DEVICE(&s_base->control), "gpu-fiq", 0)); =20 for (n =3D 0; n < BCM283X_NCPUS; n++) { /* TODO: this should be converted to a property of ARM_CPU */ - s->cpu[n].core.mp_affinity =3D (bc->clusterid << 8) | n; + s_base->cpu[n].core.mp_affinity =3D (bc->clusterid << 8) | n; =20 /* set periphbase/CBAR value for CPU-local registers */ - if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", + if (!object_property_set_int(OBJECT(&s_base->cpu[n].core), "reset-= cbar", bc->peri_base, errp)) { return; } =20 /* start powered off if not enabled */ - if (!object_property_set_bool(OBJECT(&s->cpu[n].core), + if (!object_property_set_bool(OBJECT(&s_base->cpu[n].core), "start-powered-off", - n >=3D s->enabled_cpus, + n >=3D s_base->enabled_cpus, errp)) { return; } =20 - if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { + if (!qdev_realize(DEVICE(&s_base->cpu[n].core), NULL, errp)) { return; } =20 /* Connect irq/fiq outputs from the interrupt controller. */ - qdev_connect_gpio_out_named(DEVICE(&s->control), "irq", n, - qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_IRQ)); - qdev_connect_gpio_out_named(DEVICE(&s->control), "fiq", n, - qdev_get_gpio_in(DEVICE(&s->cpu[n].core), ARM_CPU_FIQ)); + qdev_connect_gpio_out_named(DEVICE(&s_base->control), "irq", n, + qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_IRQ)); + qdev_connect_gpio_out_named(DEVICE(&s_base->control), "fiq", n, + qdev_get_gpio_in(DEVICE(&s_base->cpu[n].core), ARM_CPU_FIQ)); =20 /* Connect timers from the CPU to the interrupt controller */ - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_PHYS, - qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n= )); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_VIRT, - qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n)); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_HYP, - qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n)= ); - qdev_connect_gpio_out(DEVICE(&s->cpu[n].core), GTIMER_SEC, - qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n)= ); + qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_PHYS, + qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntpnsirq", = n)); + qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_VIRT, + qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntvirq", n)= ); + qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_HYP, + qdev_get_gpio_in_named(DEVICE(&s_base->control), "cnthpirq", n= )); + qdev_connect_gpio_out(DEVICE(&s_base->cpu[n].core), GTIMER_SEC, + qdev_get_gpio_in_named(DEVICE(&s_base->control), "cntpsirq", n= )); } } =20 -static void bcm283x_class_init(ObjectClass *oc, void *data) +static void bcm283x_base_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); =20 @@ -177,7 +185,7 @@ static void bcm283x_class_init(ObjectClass *oc, void *d= ata) static void bcm2835_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); - BCM283XClass *bc =3D BCM283X_CLASS(oc); + BCM283XBaseClass *bc =3D BCM283X_BASE_CLASS(oc); =20 bc->cpu_type =3D ARM_CPU_TYPE_NAME("arm1176"); bc->core_count =3D 1; @@ -188,7 +196,7 @@ static void bcm2835_class_init(ObjectClass *oc, void *d= ata) static void bcm2836_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); - BCM283XClass *bc =3D BCM283X_CLASS(oc); + BCM283XBaseClass *bc =3D BCM283X_BASE_CLASS(oc); =20 bc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7"); bc->core_count =3D BCM283X_NCPUS; @@ -202,7 +210,7 @@ static void bcm2836_class_init(ObjectClass *oc, void *d= ata) static void bcm2837_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); - BCM283XClass *bc =3D BCM283X_CLASS(oc); + BCM283XBaseClass *bc =3D BCM283X_BASE_CLASS(oc); =20 bc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a53"); bc->core_count =3D BCM283X_NCPUS; @@ -230,11 +238,17 @@ static const TypeInfo bcm283x_types[] =3D { #endif }, { .name =3D TYPE_BCM283X, - .parent =3D TYPE_DEVICE, + .parent =3D TYPE_BCM283X_BASE, .instance_size =3D sizeof(BCM283XState), - .instance_init =3D bcm2836_init, - .class_size =3D sizeof(BCM283XClass), - .class_init =3D bcm283x_class_init, + .instance_init =3D bcm283x_init, + .abstract =3D true, + }, { + .name =3D TYPE_BCM283X_BASE, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(BCM283XBaseState), + .instance_init =3D bcm283x_base_init, + .class_size =3D sizeof(BCM283XBaseClass), + .class_init =3D bcm283x_base_class_init, .abstract =3D true, } }; diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index cc4c4ec9bf..af866ebce2 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -252,7 +252,7 @@ static void setup_boot(MachineState *machine, RaspiProc= essorId processor_id, s->binfo.firmware_loaded =3D true; } =20 - arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo); + arm_load_kernel(&s->soc.parent_obj.cpu[0].core, machine, &s->binfo); } =20 static void raspi_machine_init(MachineState *machine) diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 6f90cabfa3..5a6717ca91 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -17,8 +17,10 @@ #include "target/arm/cpu.h" #include "qom/object.h" =20 +#define TYPE_BCM283X_BASE "bcm283x-base" +OBJECT_DECLARE_TYPE(BCM283XBaseState, BCM283XBaseClass, BCM283X_BASE) #define TYPE_BCM283X "bcm283x" -OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X) +OBJECT_DECLARE_SIMPLE_TYPE(BCM283XState, BCM283X) =20 #define BCM283X_NCPUS 4 =20 @@ -30,7 +32,7 @@ OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X) #define TYPE_BCM2836 "bcm2836" #define TYPE_BCM2837 "bcm2837" =20 -struct BCM283XState { +struct BCM283XBaseState { /*< private >*/ DeviceState parent_obj; /*< public >*/ @@ -41,7 +43,27 @@ struct BCM283XState { ARMCPU core; } cpu[BCM283X_NCPUS]; BCM2836ControlState control; +}; + +struct BCM283XBaseClass { + /*< private >*/ + DeviceClass parent_class; + /*< public >*/ + const char *name; + const char *cpu_type; + unsigned core_count; + hwaddr peri_base; /* Peripheral base address seen by the CPU */ + hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ + int clusterid; +}; + +struct BCM283XState { + /*< private >*/ + BCM283XBaseState parent_obj; + /*< public >*/ BCM2835PeripheralState peripherals; }; =20 +bool bcm283x_common_realize(DeviceState *dev, Error **errp); + #endif /* BCM2836_H */ --=20 2.34.1