From nobody Wed Nov 27 00:47:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1701963589; cv=none; d=zohomail.com; s=zohoarc; b=Q7Dbnq2pURuYvuJROAv+hQ6AF1t2eqALJ+CaQhb5F2x9X7S3l2i2AEPVdD59p029V66rtpQ105toDt+XwfIMQmkF6bTE2vui3wostfUb+p0TcU/HldbHAHjM4PDWEt3dr62gMky8rpypiInRgelJ/oHv8WYr8cH1JZ/uDc+T7BM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701963589; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EZsOkKVCnzEhASDCWsz+6dz3ib59l8sYS8/bHQwNiqk=; b=MIsIbEUPF6Hh4cRhW8/O53rN3aENL+NR20wwgutBau6wrcKAZV+Z6WSYeZ2fMoADkTZVdm7uc1EBvrin5c1LF/pid4S0e2W5AnXjSJohBhjZqb19H8sDz6iYc/4bLV5/qwS/dcNoNP0E7yv56MaxiMDf9cCpBHXY0yshVY7cwTs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1701963589294962.4388947401903; Thu, 7 Dec 2023 07:39:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rBGSp-0005zo-ND; Thu, 07 Dec 2023 10:38:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rBGSo-0005zD-LB for qemu-devel@nongnu.org; Thu, 07 Dec 2023 10:38:58 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rBGSh-00087d-Ll for qemu-devel@nongnu.org; Thu, 07 Dec 2023 10:38:58 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-3333a3a599fso1179025f8f.0 for ; Thu, 07 Dec 2023 07:38:51 -0800 (PST) Received: from rockhopper.ba.rivosinc.com (214.11.169.217.in-addr.arpa. [217.169.11.214]) by smtp.gmail.com with ESMTPSA id b16-20020a5d4b90000000b0033339e03a60sm1711399wrt.59.2023.12.07.07.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 07:38:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1701963529; x=1702568329; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EZsOkKVCnzEhASDCWsz+6dz3ib59l8sYS8/bHQwNiqk=; b=2dMy5fn37tw76ytfe6MCjDUW2PL4Ncb3nF13pR2zi8wt4rXM+rnkz8cO7Q5oNPoG7k 07pBSVVgx7bdCrZLnGF5qaMQTgteNH7Br+4q+bS42+gWvvRPqZVydiTFNln/qdc73eOc HpyWEEfUspxIl60MSRlQQMbu5sjQFNirP4Qur+qF58UTLspZr97HOnNZDbwcKBoHIUnA sUuWMc04L5Fz28vLgZI9XOZBwjG3iQgeZgEpGAkhy9FZxP4KBguB/DwC7pemzT0e4zLF jMsf5LMpeARYverJ/BeEMWn8kWrEynYyKc3Eg0Xk+cqkSaZk7fwAWzBpPB+nGTnHrDlZ ukGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701963529; x=1702568329; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EZsOkKVCnzEhASDCWsz+6dz3ib59l8sYS8/bHQwNiqk=; b=qPK69arTQal7rvWBVmZMc1VfK82TN5qmawCGkYfxEDSz37d/PP3PHdQmW89zbSJ/jj 2K800zhuiE5t4YCW2mEIm/JZgj1C8uqFiw6CcY3Fn+wGXT7wDPHzy4seqsjPlslYANpW LVxs6cWVoIqBfxvrQrchHAzxhLC3oCOuB5Gf+GRDVK9LWh1Dy5tA09eG/vxveU2ceJb2 I612OUwV3w8zM7MJuT0b/3V1tGKD9yaK1Cv0Fc7xYdjF3Y3FVTRgxw7ylSSolX5YK9Tj QV+3Ng+mcMdxlBb6wKcB8ubpyBEu0BtQrkI92ktNH0MpQ9YgbUD+NhyDgNqo66fzlXAr GIQQ== X-Gm-Message-State: AOJu0YzVizn1mK7S6Qn4keBbqgS65UFahiEIfG1TTXoEVENnyy2xvSvt N96o2MTB/2981aXgFpcf4Uc8zn6rSkd5AJatOllulA== X-Google-Smtp-Source: AGHT+IHHYhNYbaEsHGnrXWSoS+nhfKwiDg3dToAGRW2cuifgsKa3lfGlWHBlxoouXBbK9DkK3VOZyA== X-Received: by 2002:a05:600c:138e:b0:40b:5533:ceb9 with SMTP id u14-20020a05600c138e00b0040b5533ceb9mr2724799wmf.7.1701963529064; Thu, 07 Dec 2023 07:38:49 -0800 (PST) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford , Weiwei Li , Junqiang Wang Subject: [PATCH 1/2] target/riscv: Add support for Zacas extension Date: Thu, 7 Dec 2023 15:32:30 +0000 Message-ID: <20231207153842.32401-2-rbradford@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231207153842.32401-1-rbradford@rivosinc.com> References: <20231207153842.32401-1-rbradford@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=rbradford@rivosinc.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1701963591314100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Add support for amocas.w/d/q instructions which are part of the ratified Zacas extension: https://github.com/riscv/riscv-zacas Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 2 + target/riscv/cpu_cfg.h | 1 + target/riscv/insn32.decode | 6 + target/riscv/insn_trans/trans_rvzacas.c.inc | 150 ++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 5 + target/riscv/translate.c | 1 + 6 files changed, 165 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzacas.c.inc diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 83c7c0cf07..a265833b17 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -87,6 +87,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm), ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), + ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas), ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), @@ -1300,6 +1301,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true), + MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false), MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true), MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true), MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index f4605fb190..d516de4a44 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -77,6 +77,7 @@ struct RISCVCPUConfig { bool ext_svnapot; bool ext_svpbmt; bool ext_zdinx; + bool ext_zacas; bool ext_zawrs; bool ext_zfa; bool ext_zfbfmin; diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 33597fe2bb..f22df04cfd 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -1004,3 +1004,9 @@ vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r= 2_vm_1 vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1 vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1 + +# *** RV32 Zacas Standard Extension *** +amocas_w 00101 . . ..... ..... 010 ..... 0101111 @atom_st +amocas_d 00101 . . ..... ..... 011 ..... 0101111 @atom_st +# *** RV64 Zacas Standard Extension *** +amocas_q 00101 . . ..... ..... 100 ..... 0101111 @atom_st diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc b/target/riscv/ins= n_trans/trans_rvzacas.c.inc new file mode 100644 index 0000000000..5d274d4c08 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzacas.c.inc @@ -0,0 +1,150 @@ +/* + * RISC-V translation routines for the RV64 Zacas Standard Extension. + * + * Copyright (c) 2020-2023 PLCT Lab + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#define REQUIRE_ZACAS(ctx) do { \ + if (!ctx->cfg_ptr->ext_zacas) { \ + return false; \ + } \ +} while (0) + +static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop) +{ + TCGv dest =3D get_gpr(ctx, a->rd, EXT_NONE); + TCGv src1 =3D get_address(ctx, a->rs1, 0); + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); + + decode_save_opc(ctx); + tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop); + + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_amocas_w(DisasContext *ctx, arg_amocas_w *a) +{ + REQUIRE_ZACAS(ctx); + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TESL); +} + +static TCGv_i64 get_gpr_pair(DisasContext *ctx, int reg_num) +{ + TCGv_i64 t; + + assert(get_ol(ctx) =3D=3D MXL_RV32); + + if (reg_num =3D=3D 0) { + return tcg_constant_i64(0); + } + + t =3D tcg_temp_new_i64(); + tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); + return t; +} + +static void gen_set_gpr_pair(DisasContext *ctx, int reg_num, TCGv_i64 t) +{ + assert(get_ol(ctx) =3D=3D MXL_RV32); + + if (reg_num !=3D 0) { +#ifdef TARGET_RISCV32 + tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); +#else + tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); + tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); +#endif + + if (get_xl_max(ctx) =3D=3D MXL_RV128) { + tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); + tcg_gen_sari_tl(cpu_gprh[reg_num + 1], cpu_gpr[reg_num + 1], 6= 3); + } + } +} + +static bool gen_cmpxchg64(DisasContext *ctx, arg_atomic *a, MemOp mop) +{ + /* + * Encodings with odd numbered registers specified in rs2 and rd are + * reserved. + */ + if ((a->rs2 | a->rd) & 1) { + return false; + } + + TCGv_i64 dest =3D get_gpr_pair(ctx, a->rd); + TCGv src1 =3D get_address(ctx, a->rs1, 0); + TCGv_i64 src2 =3D get_gpr_pair(ctx, a->rs2); + + decode_save_opc(ctx); + tcg_gen_atomic_cmpxchg_i64(dest, src1, dest, src2, ctx->mem_idx, mop); + + gen_set_gpr_pair(ctx, a->rd, dest); + return true; +} + +static bool trans_amocas_d(DisasContext *ctx, arg_amocas_d *a) +{ + REQUIRE_ZACAS(ctx); + switch (get_ol(ctx)) { + case MXL_RV32: + return gen_cmpxchg64(ctx, a, MO_ALIGN | MO_TEUQ); + case MXL_RV64: + case MXL_RV128: + return gen_cmpxchg(ctx, a, MO_ALIGN | MO_TEUQ); + default: + g_assert_not_reached(); + } +} + +static bool trans_amocas_q(DisasContext *ctx, arg_amocas_q *a) +{ + REQUIRE_ZACAS(ctx); + REQUIRE_64BIT(ctx); + + /* + * Encodings with odd numbered registers specified in rs2 and rd are + * reserved. + */ + if ((a->rs2 | a->rd) & 1) { + return false; + } + +#ifdef TARGET_RISCV64 + TCGv_i128 dest =3D tcg_temp_new_i128(); + TCGv src1 =3D get_address(ctx, a->rs1, 0); + TCGv_i128 src2 =3D tcg_temp_new_i128(); + TCGv_i64 src2l =3D get_gpr(ctx, a->rs2, EXT_NONE); + TCGv_i64 src2h =3D get_gpr(ctx, a->rs2 =3D=3D 0 ? 0 : a->rs2 + 1, EXT_= NONE); + TCGv_i64 destl =3D get_gpr(ctx, a->rd, EXT_NONE); + TCGv_i64 desth =3D get_gpr(ctx, a->rd =3D=3D 0 ? 0 : a->rd + 1, EXT_NO= NE); + + tcg_gen_concat_i64_i128(src2, src2l, src2h); + tcg_gen_concat_i64_i128(dest, destl, desth); + decode_save_opc(ctx); + tcg_gen_atomic_cmpxchg_i128(dest, src1, dest, src2, ctx->mem_idx, + (MO_ALIGN | MO_TEUO)); + + tcg_gen_extr_i128_i64(destl, desth, dest); + + if (a->rd !=3D 0) { + gen_set_gpr(ctx, a->rd, destl); + gen_set_gpr(ctx, a->rd + 1, desth); + } +#endif + + return true; +} diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8a35683a34..29b5a88931 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -343,6 +343,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 + if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { + error_setg(errp, "Zacas extension requires A extension"); + return; + } + if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { error_setg(errp, "Zawrs extension requires A extension"); return; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f0be79bb16..071fbad7ef 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1089,6 +1089,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvv.c.inc" #include "insn_trans/trans_rvb.c.inc" #include "insn_trans/trans_rvzicond.c.inc" +#include "insn_trans/trans_rvzacas.c.inc" #include "insn_trans/trans_rvzawrs.c.inc" #include "insn_trans/trans_rvzicbo.c.inc" #include "insn_trans/trans_rvzfa.c.inc" --=20 2.43.0 From nobody Wed Nov 27 00:47:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1701963586; cv=none; d=zohomail.com; s=zohoarc; b=ni1VeLYoZ+86AvpiD7Lfv4pEIJmHRWgP5rZSpMrj4myAwEJagSOuwbGInNCZ/PDeSlJTnYT7ECkv9PtELvs8q3MDuPL+58/7KL9K2nV7pwwJwmn0pmGSnT/tOSnGQa94TwphMe/CaSaq95BRyjXdkxQxcaUsmylU7A+wY/WSY7A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701963586; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fZw+JUiGsn+h8Ah0eCoapNTG4nn0tiSq/PIPn2r1QhI=; b=dgnrP/KRoiJeyNmvcmui6v6WrDkOL8lk/ic2h23nc9a6Dh+i/e1UdzKu/+YPO/rIQaDMoGEWRInCcfWVU9Emrn8k2AtLnnejmrPUEDeCMcjPvc6BAnFLA4xTSzVppAWiH8a6QYDey8kb3zxyQ1mJuy9S8WPKyGnXbKF2H9O8gc4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1701963586654995.9162051956247; Thu, 7 Dec 2023 07:39:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rBGSp-0005zX-JS; Thu, 07 Dec 2023 10:38:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rBGSn-0005yu-UJ for qemu-devel@nongnu.org; Thu, 07 Dec 2023 10:38:58 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rBGSi-00087y-17 for qemu-devel@nongnu.org; Thu, 07 Dec 2023 10:38:57 -0500 Received: by mail-wr1-x42e.google.com with SMTP id ffacd0b85a97d-333536432e0so989567f8f.3 for ; Thu, 07 Dec 2023 07:38:51 -0800 (PST) Received: from rockhopper.ba.rivosinc.com (214.11.169.217.in-addr.arpa. [217.169.11.214]) by smtp.gmail.com with ESMTPSA id b16-20020a5d4b90000000b0033339e03a60sm1711399wrt.59.2023.12.07.07.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 07:38:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1701963530; x=1702568330; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fZw+JUiGsn+h8Ah0eCoapNTG4nn0tiSq/PIPn2r1QhI=; b=eNxKexhAaD61RhpV5iX/XKY3+lvwnjsJefRzXZT3QQOD9piw5NcWbuwum5TCP7xT0b AMOkKYU8yQcB+cJw+OAvyrwy5+KIBFQyWybqWo613L7+eD7nSmctpxti+FV3QGfXWplC 6svxbeURx4KT9i4bo475d/xTRUavRxG+qFRxhbq4ZIPiRgeimvTMeFp1Iu5hT/9YJXQJ Al7dvQ1QVsCK6apecbzRzUYAJUEJY0xeLP7gQ6KFTowH0pRUUMPWWhr0LdFTeGHqOrsi OWOhSrpkNBfaHgOR38chXq1FB6X0hXVmDXmW/zlUcQg4nPiYvbSthbu7I0ZuUJbmHdTg df5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701963530; x=1702568330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fZw+JUiGsn+h8Ah0eCoapNTG4nn0tiSq/PIPn2r1QhI=; b=PX7sjOAjsYUCE8opBDuQRIXsiNWAMgQqxtsCjBK1vxn4805Nbi81S85MIXsz26jR98 YCcY8i+baGJluKGsiQdQhuOQZW2ga7gjzCFRlzeuyiqAqLX1phBkaQWE8ZMNEzkoG82p JQOk6Efsp9NKkWshL8lNzRod3cM5YyDgHDdPGGldLZjKPwJTnVtkWB0SWtRiCn3Pu4gc IUV9Hwi9bWXYqnblwUoBl2qvDvsVBmglJ7LjQZDlYeUJ0Pjg7GThc0LQW317gTvB1ZGq 035BoZcSzMTxlGmLP53IUbuqJNGqRwxMwMaYFnYhlLnwUPoqUXdcfRcbBbcpeSy2Y5yN 0MbQ== X-Gm-Message-State: AOJu0YyEVxQo7N2VF2ycAjsscnSmQVgNjTTfp5BE2/CfvBW1dF1yT6AQ qJlF3D2JlNepaZUZVrYas2fVG7jIqNQeYS3vrbfDMg== X-Google-Smtp-Source: AGHT+IEcWRDde5CeNOytCjA1B141772By2Dy/wAdEiAkT1pYlQr+PtIHoswvHU96QQc/kZI8LqT1ag== X-Received: by 2002:adf:f10f:0:b0:333:2fd2:6f74 with SMTP id r15-20020adff10f000000b003332fd26f74mr1549114wro.126.1701963530345; Thu, 07 Dec 2023 07:38:50 -0800 (PST) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford , Alistair Francis Subject: [PATCH 2/2] disas/riscv: Add amocas.[w,d,q] instructions Date: Thu, 7 Dec 2023 15:32:31 +0000 Message-ID: <20231207153842.32401-3-rbradford@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231207153842.32401-1-rbradford@rivosinc.com> References: <20231207153842.32401-1-rbradford@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=rbradford@rivosinc.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1701963587088100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- disas/riscv.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index e9458e574b..8a546d5ea5 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -903,6 +903,9 @@ typedef enum { rv_op_vwsll_vv =3D 872, rv_op_vwsll_vx =3D 873, rv_op_vwsll_vi =3D 874, + rv_op_amocas_w =3D 875, + rv_op_amocas_d =3D 876, + rv_op_amocas_q =3D 877, } rv_op; =20 /* register names */ @@ -2090,6 +2093,9 @@ const rv_opcode_data rvi_opcode_data[] =3D { { "vwsll.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm, NULL, 0, 0, 0 }, { "vwsll.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, NULL, 0, 0, 0 }, { "vwsll.vi", rv_codec_v_i, rv_fmt_vd_vs2_uimm_vm, NULL, 0, 0, 0 }, + { "amocas.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, + { "amocas.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, + { "amocas.q", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, }; =20 /* CSR names */ @@ -2841,6 +2847,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa= isa) case 34: op =3D rv_op_amoxor_w; break; case 35: op =3D rv_op_amoxor_d; break; case 36: op =3D rv_op_amoxor_q; break; + case 42: op =3D rv_op_amocas_w; break; + case 43: op =3D rv_op_amocas_d; break; + case 44: op =3D rv_op_amocas_q; break; case 66: op =3D rv_op_amoor_w; break; case 67: op =3D rv_op_amoor_d; break; case 68: op =3D rv_op_amoor_q; break; --=20 2.43.0