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qemu-devel@nongnu.org Cc: bcain@quicinc.com, quic_mathbern@quicinc.com, sidneym@quicinc.com, quic_mliebel@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, ltaylorsimpson@gmail.com Subject: [PATCH 4/9] Hexagon (target/hexagon) Make generators object oriented - gen_helper_funcs Date: Mon, 4 Dec 2023 18:52:58 -0700 Message-Id: <20231205015303.575807-5-ltaylorsimpson@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231205015303.575807-1-ltaylorsimpson@gmail.com> References: <20231205015303.575807-1-ltaylorsimpson@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=ltaylorsimpson@gmail.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1701741305817100006 Signed-off-by: Taylor Simpson --- target/hexagon/gen_helper_funcs.py | 400 +++++++---------------------- target/hexagon/hex_common.py | 58 ++++- 2 files changed, 151 insertions(+), 307 deletions(-) diff --git a/target/hexagon/gen_helper_funcs.py b/target/hexagon/gen_helper= _funcs.py index ce21d3b688..60b7e95e8c 100755 --- a/target/hexagon/gen_helper_funcs.py +++ b/target/hexagon/gen_helper_funcs.py @@ -23,181 +23,14 @@ import hex_common =20 =20 -## -## Helpers for gen_helper_function -## -def gen_decl_ea(f): - f.write(" uint32_t EA;\n") - - -def gen_helper_return_type(f, regtype, regid, regno): - if regno > 1: - f.write(", ") - f.write("int32_t") - - -def gen_helper_return_type_pair(f, regtype, regid, regno): - if regno > 1: - f.write(", ") - f.write("int64_t") - - -def gen_helper_arg(f, regtype, regid, regno): - if regno > 0: - f.write(", ") - f.write(f"int32_t {regtype}{regid}V") - - -def gen_helper_arg_new(f, regtype, regid, regno): - if regno >=3D 0: - f.write(", ") - f.write(f"int32_t {regtype}{regid}N") - - -def gen_helper_arg_pair(f, regtype, regid, regno): - if regno >=3D 0: - f.write(", ") - f.write(f"int64_t {regtype}{regid}V") - - -def gen_helper_arg_ext(f, regtype, regid, regno): - if regno > 0: - f.write(", ") - f.write(f"void *{regtype}{regid}V_void") - - -def gen_helper_arg_ext_pair(f, regtype, regid, regno): - if regno > 0: - f.write(", ") - f.write(f"void *{regtype}{regid}V_void") - - -def gen_helper_arg_opn(f, regtype, regid, i, tag): - if hex_common.is_pair(regid): - if hex_common.is_hvx_reg(regtype): - gen_helper_arg_ext_pair(f, regtype, regid, i) - else: - gen_helper_arg_pair(f, regtype, regid, i) - elif hex_common.is_single(regid): - if hex_common.is_old_val(regtype, regid, tag): - if hex_common.is_hvx_reg(regtype): - gen_helper_arg_ext(f, regtype, regid, i) - else: - gen_helper_arg(f, regtype, regid, i) - elif hex_common.is_new_val(regtype, regid, tag): - gen_helper_arg_new(f, regtype, regid, i) - else: - hex_common.bad_register(regtype, regid) - else: - hex_common.bad_register(regtype, regid) - - -def gen_helper_arg_imm(f, immlett): - f.write(f", int32_t {hex_common.imm_name(immlett)}") - - -def gen_helper_dest_decl(f, regtype, regid, regno, subfield=3D""): - f.write(f" int32_t {regtype}{regid}V{subfield} =3D 0;\n") - - -def gen_helper_dest_decl_pair(f, regtype, regid, regno, subfield=3D""): - f.write(f" int64_t {regtype}{regid}V{subfield} =3D 0;\n") - - -def gen_helper_dest_decl_ext(f, regtype, regid): - if regtype =3D=3D "Q": - f.write( - f" /* {regtype}{regid}V is *(MMQReg *)" f"({regtype}{regid}= V_void) */\n" - ) - else: - f.write( - f" /* {regtype}{regid}V is *(MMVector *)" - f"({regtype}{regid}V_void) */\n" - ) - - -def gen_helper_dest_decl_ext_pair(f, regtype, regid, regno): - f.write( - f" /* {regtype}{regid}V is *(MMVectorPair *))" - f"{regtype}{regid}V_void) */\n" - ) - - -def gen_helper_dest_decl_opn(f, regtype, regid, i): - if hex_common.is_pair(regid): - if hex_common.is_hvx_reg(regtype): - gen_helper_dest_decl_ext_pair(f, regtype, regid, i) - else: - gen_helper_dest_decl_pair(f, regtype, regid, i) - elif hex_common.is_single(regid): - if hex_common.is_hvx_reg(regtype): - gen_helper_dest_decl_ext(f, regtype, regid) - else: - gen_helper_dest_decl(f, regtype, regid, i) - else: - hex_common.bad_register(regtype, regid) - - -def gen_helper_src_var_ext(f, regtype, regid): - if regtype =3D=3D "Q": - f.write( - f" /* {regtype}{regid}V is *(MMQReg *)" f"({regtype}{regid}= V_void) */\n" - ) - else: - f.write( - f" /* {regtype}{regid}V is *(MMVector *)" - f"({regtype}{regid}V_void) */\n" - ) - - -def gen_helper_src_var_ext_pair(f, regtype, regid, regno): - f.write( - f" /* {regtype}{regid}V{regno} is *(MMVectorPair *)" - f"({regtype}{regid}V{regno}_void) */\n" - ) - - -def gen_helper_return(f, regtype, regid, regno): - f.write(f" return {regtype}{regid}V;\n") - - -def gen_helper_return_pair(f, regtype, regid, regno): - f.write(f" return {regtype}{regid}V;\n") - - -def gen_helper_dst_write_ext(f, regtype, regid): - return - - -def gen_helper_dst_write_ext_pair(f, regtype, regid): - return - - -def gen_helper_return_opn(f, regtype, regid, i): - if hex_common.is_pair(regid): - if hex_common.is_hvx_reg(regtype): - gen_helper_dst_write_ext_pair(f, regtype, regid) - else: - gen_helper_return_pair(f, regtype, regid, i) - elif hex_common.is_single(regid): - if hex_common.is_hvx_reg(regtype): - gen_helper_dst_write_ext(f, regtype, regid) - else: - gen_helper_return(f, regtype, regid, i) - else: - hex_common.bad_register(regtype, regid) - - ## ## Generate the TCG code to call the helper ## For A2_add: Rd32=3Dadd(Rs32,Rt32), { RdV=3DRsV+RtV;} ## We produce: ## int32_t HELPER(A2_add)(CPUHexagonState *env, int32_t RsV, int32_t= RtV) ## { -## uint32_t slot __attribute__(unused)) =3D 4; ## int32_t RdV =3D 0; ## { RdV=3DRsV+RtV;} -## COUNT_HELPER(A2_add); ## return RdV; ## } ## @@ -205,151 +38,111 @@ def gen_helper_function(f, tag, tagregs, tagimms): regs =3D tagregs[tag] imms =3D tagimms[tag] =20 - numresults =3D 0 + ## If there is a scalar result, it is the return type + return_type =3D "" numscalarresults =3D 0 - numscalarreadwrite =3D 0 for regtype, regid in regs: - if hex_common.is_written(regid): - numresults +=3D 1 - if hex_common.is_scalar_reg(regtype): - numscalarresults +=3D 1 - if hex_common.is_readwrite(regid): - if hex_common.is_scalar_reg(regtype): - numscalarreadwrite +=3D 1 + reg =3D hex_common.get_register(tag, regtype, regid) + if reg.is_written() and reg.is_scalar_reg(): + return_type =3D reg.helper_arg_type() + numscalarresults +=3D 1 + if numscalarresults =3D=3D 0: + return_type =3D "void" =20 if numscalarresults > 1: - ## The helper is bogus when there is more than one result - f.write( - f"void HELPER({tag})(CPUHexagonState *env) " f"{{ BOGUS_HELPER= ({tag}); }}\n" - ) - else: - ## The return type of the function is the type of the destination - ## register (if scalar) - i =3D 0 - for regtype, regid in regs: - if hex_common.is_written(regid): - if hex_common.is_pair(regid): - if hex_common.is_hvx_reg(regtype): - continue - else: - gen_helper_return_type_pair(f, regtype, regid, i) - elif hex_common.is_single(regid): - if hex_common.is_hvx_reg(regtype): - continue - else: - gen_helper_return_type(f, regtype, regid, i) - else: - hex_common.bad_register(regtype, regid) - i +=3D 1 + raise Exception("numscalarresults > 1") =20 - if numscalarresults =3D=3D 0: - f.write("void") - f.write(f" HELPER({tag})(CPUHexagonState *env") - - ## Arguments include the vector destination operands - i =3D 1 - for regtype, regid in regs: - if hex_common.is_written(regid): - if hex_common.is_pair(regid): - if hex_common.is_hvx_reg(regtype): - gen_helper_arg_ext_pair(f, regtype, regid, i) - else: - continue - elif hex_common.is_single(regid): - if hex_common.is_hvx_reg(regtype): - gen_helper_arg_ext(f, regtype, regid, i) - else: - # This is the return value of the function - continue - else: - hex_common.bad_register(regtype, regid) - i +=3D 1 - - ## For conditional instructions, we pass in the destination regist= er - if "A_CONDEXEC" in hex_common.attribdict[tag]: - for regtype, regid in regs: - if hex_common.is_writeonly(regid) and not hex_common.is_hv= x_reg( - regtype - ): - gen_helper_arg_opn(f, regtype, regid, i, tag) - i +=3D 1 - - ## Arguments to the helper function are the source regs and immedi= ates + declared =3D [] + declared.append("CPUHexagonState *env") + ## For predicated instructions, we pass in the destination register + if hex_common.is_predicated(tag): for regtype, regid in regs: - if hex_common.is_read(regid): - if hex_common.is_hvx_reg(regtype) and hex_common.is_readwr= ite(regid): - continue - gen_helper_arg_opn(f, regtype, regid, i, tag) - i +=3D 1 - for immlett, bits, immshift in imms: - gen_helper_arg_imm(f, immlett) - i +=3D 1 - - if hex_common.need_pkt_has_multi_cof(tag): - f.write(", uint32_t pkt_has_multi_cof") - if (hex_common.need_pkt_need_commit(tag)): - f.write(", uint32_t pkt_need_commit") - - if hex_common.need_PC(tag): - if i > 0: - f.write(", ") - f.write("target_ulong PC") - i +=3D 1 - if hex_common.helper_needs_next_PC(tag): - if i > 0: - f.write(", ") - f.write("target_ulong next_PC") - i +=3D 1 - if hex_common.need_slot(tag): - if i > 0: - f.write(", ") - f.write("uint32_t slotval") - i +=3D 1 - if hex_common.need_part1(tag): - if i > 0: - f.write(", ") - f.write("uint32_t part1") - f.write(")\n{\n") - if hex_common.need_ea(tag): - gen_decl_ea(f) - ## Declare the return variable - i =3D 0 - if "A_CONDEXEC" not in hex_common.attribdict[tag]: - for regtype, regid in regs: - if hex_common.is_writeonly(regid): - gen_helper_dest_decl_opn(f, regtype, regid, i) - i +=3D 1 - + reg =3D hex_common.get_register(tag, regtype, regid) + if reg.is_writeonly() and not reg.is_hvx_reg(): + declared.append(f"{reg.helper_arg_type()} {reg.helper_arg(= )}") + ## Pass the HVX destination operands + for regtype, regid in regs: + reg =3D hex_common.get_register(tag, regtype, regid) + if reg.is_written() and reg.is_hvx_reg(): + declared.append(f"{reg.helper_arg_type()} {reg.helper_arg()}") + ## Pass the source registers + for regtype, regid in regs: + reg =3D hex_common.get_register(tag, regtype, regid) + if reg.is_read() and not (reg.is_hvx_reg() and reg.is_readwrite()): + declared.append(f"{reg.helper_arg_type()} {reg.helper_arg()}") + ## Pass the immediates + for immlett, bits, immshift in imms: + declared.append(f"int32_t {hex_common.imm_name(immlett)}") + + ## Other sutff the helper might need + if hex_common.need_pkt_has_multi_cof(tag): + declared.append("uint32_t pkt_has_multi_cof") + if (hex_common.need_pkt_need_commit(tag)): + declared.append("uint32_t pkt_need_commit") + if hex_common.need_PC(tag): + declared.append("target_ulong PC") + if hex_common.need_next_PC(tag): + declared.append("target_ulong next_PC") + if hex_common.need_slot(tag): + declared.append("uint32_t slotval") + if hex_common.need_part1(tag): + declared.append("uint32_t part1") + + arguments =3D ", ".join(declared) + f.write(f"{return_type} HELPER({tag})({arguments})\n") + f.write("{\n") + if hex_common.need_ea(tag): + f.write(hex_common.code_fmt(f"""\ + uint32_t EA; + """)) + ## Declare the return variable + if not hex_common.is_predicated(tag): for regtype, regid in regs: - if hex_common.is_read(regid): - if hex_common.is_pair(regid): - if hex_common.is_hvx_reg(regtype): - gen_helper_src_var_ext_pair(f, regtype, regid, i) - elif hex_common.is_single(regid): - if hex_common.is_hvx_reg(regtype): - gen_helper_src_var_ext(f, regtype, regid) - else: - hex_common.bad_register(regtype, regid) - - if hex_common.need_slot(tag): - if "A_LOAD" in hex_common.attribdict[tag]: - f.write(" bool pkt_has_store_s1 =3D slotval & 0x1;\n") - f.write(" uint32_t slot =3D slotval >> 1;\n") - - if "A_FPOP" in hex_common.attribdict[tag]: - f.write(" arch_fpop_start(env);\n") - - f.write(f" {hex_common.semdict[tag]}\n") + reg =3D hex_common.get_register(tag, regtype, regid) + if reg.is_writeonly() and not reg.is_hvx_reg(): + f.write(hex_common.code_fmt(f"""\ + {reg.helper_arg_type()} {reg.helper_arg()} =3D 0; + """)) =20 - if "A_FPOP" in hex_common.attribdict[tag]: - f.write(" arch_fpop_end(env);\n") + ## Print useful information about HVX registers + for regtype, regid in regs: + reg =3D hex_common.get_register(tag, regtype, regid) + if reg.is_hvx_reg(): + reg.helper_hvx_desc(f) + + if hex_common.need_slot(tag): + if "A_LOAD" in hex_common.attribdict[tag]: + f.write(hex_common.code_fmt(f"""\ + bool pkt_has_store_s1 =3D slotval & 0x1; + """)) + f.write(hex_common.code_fmt(f"""\ + uint32_t slot =3D slotval >> 1; + """)) + + if "A_FPOP" in hex_common.attribdict[tag]: + f.write(hex_common.code_fmt(f"""\ + arch_fpop_start(env); + """)) + + f.write(hex_common.code_fmt(f"""\ + {hex_common.semdict[tag]} + """)) + + if "A_FPOP" in hex_common.attribdict[tag]: + f.write(hex_common.code_fmt(f"""\ + arch_fpop_end(env); + """)) + + ## Return the scalar result + for regtype, regid in regs: + reg =3D hex_common.get_register(tag, regtype, regid) + if reg.is_written() and not reg.is_hvx_reg(): + f.write(hex_common.code_fmt(f"""\ + return {reg.helper_arg()}; + """)) =20 - ## Save/return the return variable - for regtype, regid in regs: - if hex_common.is_written(regid): - gen_helper_return_opn(f, regtype, regid, i) - f.write("}\n\n") - ## End of the helper definition + f.write("}\n\n") + ## End of the helper definition =20 =20 def main(): @@ -370,6 +163,7 @@ def main(): if is_idef_parser_enabled: hex_common.read_idef_parser_enabled_file(sys.argv[5]) hex_common.calculate_attribs() + hex_common.init_registers() tagregs =3D hex_common.get_tagregs() tagimms =3D hex_common.get_tagimms() =20 diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 4149c2ce91..384f377621 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -275,10 +275,6 @@ def need_PC(tag): return "A_IMPLICIT_READS_PC" in attribdict[tag] =20 =20 -def helper_needs_next_PC(tag): - return "A_CALL" in attribdict[tag] - - def need_next_PC(tag): return "A_CALL" in attribdict[tag] =20 @@ -395,14 +391,20 @@ def is_scalar_reg(self): return True def is_hvx_reg(self): return False + def helper_arg(self): + return self.reg_tcg() =20 class Single(Scalar): def helper_proto_type(self): return "s32" + def helper_arg_type(self): + return "int32_t" =20 class Pair(Scalar): def helper_proto_type(self): return "s64" + def helper_arg_type(self): + return "int64_t" =20 class Hvx: def is_scalar_reg(self): @@ -413,6 +415,10 @@ def hvx_off(self): return f"{self.reg_tcg()}_off" def helper_proto_type(self): return "ptr" + def helper_arg_type(self): + return "void *" + def helper_arg(self): + return f"{self.reg_tcg()}_void" =20 # # Every register is either Dest or OldSource or NewSource or ReadWrite @@ -659,6 +665,10 @@ def decl_tcg(self, f, tag, regno): """)) def log_write(self, f, tag): pass + def helper_hvx_desc(self, f): + f.write(code_fmt(f"""\ + /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg()}) */ + """)) =20 class VRegSource(Register, Hvx, OldSource): def decl_tcg(self, f, tag, regno): @@ -671,6 +681,10 @@ def decl_tcg(self, f, tag, regno): TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); """)) + def helper_hvx_desc(self, f): + f.write(code_fmt(f"""\ + /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg()}) */ + """)) =20 class VRegNewSource(Register, Hvx, NewSource): def decl_tcg(self, f, tag, regno): @@ -680,6 +694,10 @@ def decl_tcg(self, f, tag, regno): const intptr_t {self.hvx_off()} =3D ctx_future_vreg_off(ctx, {self.reg_num}, 1, true); """)) + def helper_hvx_desc(self, f): + f.write(code_fmt(f"""\ + /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg()}) */ + """)) =20 class VRegReadWrite(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): @@ -698,6 +716,10 @@ def decl_tcg(self, f, tag, regno): """)) def log_write(self, f, tag): pass + def helper_hvx_desc(self, f): + f.write(code_fmt(f"""\ + /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg()}) */ + """)) =20 class VRegTmp(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): @@ -718,6 +740,10 @@ def log_write(self, f, tag): gen_log_vreg_write(ctx, {self.hvx_off()}, {self.reg_num}, {hvx_newv(tag)}); """)) + def helper_hvx_desc(self, f): + f.write(code_fmt(f"""\ + /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg()}) */ + """)) =20 class VRegPairDest(Register, Hvx, Dest): def decl_tcg(self, f, tag, regno): @@ -733,6 +759,10 @@ def decl_tcg(self, f, tag, regno): """)) def log_write(self, f, tag): pass + def helper_hvx_desc(self, f): + f.write(code_fmt(f"""\ + /* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg()}) = */ + """)) =20 class VRegPairSource(Register, Hvx, OldSource): def decl_tcg(self, f, tag, regno): @@ -752,6 +782,10 @@ def decl_tcg(self, f, tag, regno): TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); """)) + def helper_hvx_desc(self, f): + f.write(code_fmt(f"""\ + /* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg()}) = */ + """)) =20 class VRegPairReadWrite(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): @@ -776,6 +810,10 @@ def log_write(self, f, tag): gen_log_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num}, {hvx_newv(tag)}); """)) + def helper_hvx_desc(self, f): + f.write(code_fmt(f"""\ + /* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg()}) = */ + """)) =20 class QRegDest(Register, Hvx, Dest): def decl_tcg(self, f, tag, regno): @@ -791,6 +829,10 @@ def decl_tcg(self, f, tag, regno): """)) def log_write(self, f, tag): pass + def helper_hvx_desc(self, f): + f.write(code_fmt(f"""\ + /* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg()}) */ + """)) =20 class QRegSource(Register, Hvx, OldSource): def decl_tcg(self, f, tag, regno): @@ -804,6 +846,10 @@ def decl_tcg(self, f, tag, regno): TCGv_ptr {self.reg_tcg()} =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off(= )}); """)) + def helper_hvx_desc(self, f): + f.write(code_fmt(f"""\ + /* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg()}) */ + """)) =20 class QRegReadWrite(Register, Hvx, ReadWrite): def decl_tcg(self, f, tag, regno): @@ -822,6 +868,10 @@ def decl_tcg(self, f, tag, regno): """)) def log_write(self, f, tag): pass + def helper_hvx_desc(self, f): + f.write(code_fmt(f"""\ + /* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg()}) */ + """)) =20 def init_registers(): regs =3D { --=20 2.34.1