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Mon, 04 Dec 2023 07:26:08 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Palmer Dabbelt , Bin Meng , Weiwei Li , Liu Zhiwei Subject: [PULL 2/4] target/riscv/kvm: fix shadowing in kvm_riscv_(get|put)_regs_csr Date: Mon, 4 Dec 2023 16:25:22 +0100 Message-ID: <20231204152524.37803-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231204152524.37803-1-philmd@linaro.org> References: <20231204152524.37803-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1701703614953100003 From: Daniel Henrique Barboza KVM_RISCV_GET_CSR() and KVM_RISCV_SET_CSR() use an 'int ret' variable that is used to do an early 'return' if ret > 0. Both are being called in functions that are also declaring a 'ret' integer, initialized with '0', and this integer is used as return of the function. The result is that the compiler is less than pleased and is pointing shadowing errors: ../target/riscv/kvm/kvm-cpu.c: In function 'kvm_riscv_get_regs_csr': ../target/riscv/kvm/kvm-cpu.c:90:13: error: declaration of 'ret' shadows a = previous local [-Werror=3Dshadow=3Dcompatible-local] 90 | int ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), &r= eg); \ | ^~~ ../target/riscv/kvm/kvm-cpu.c:539:5: note: in expansion of macro 'KVM_RISCV= _GET_CSR' 539 | KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); | ^~~~~~~~~~~~~~~~~ ../target/riscv/kvm/kvm-cpu.c:536:9: note: shadowed declaration is here 536 | int ret =3D 0; | ^~~ ../target/riscv/kvm/kvm-cpu.c: In function 'kvm_riscv_put_regs_csr': ../target/riscv/kvm/kvm-cpu.c:98:13: error: declaration of 'ret' shadows a = previous local [-Werror=3Dshadow=3Dcompatible-local] 98 | int ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), &r= eg); \ | ^~~ ../target/riscv/kvm/kvm-cpu.c:556:5: note: in expansion of macro 'KVM_RISCV= _SET_CSR' 556 | KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); | ^~~~~~~~~~~~~~~~~ ../target/riscv/kvm/kvm-cpu.c:553:9: note: shadowed declaration is here 553 | int ret =3D 0; | ^~~ The macros are doing early returns for non-zero returns and the local 'ret' variable for both functions is used just to do 'return 0', so remove them from kvm_riscv_get_regs_csr() and kvm_riscv_put_regs_csr() and do a straight 'return 0' in the end. For good measure let's also rename the 'ret' variables in KVM_RISCV_GET_CSR() and KVM_RISCV_SET_CSR() to '_ret' to make them more resilient to these kind of errors. Fixes: 937f0b4512 ("target/riscv: Implement kvm_arch_get_registers") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-ID: <20231123101338.1040134-1-dbarboza@ventanamicro.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/kvm/kvm-cpu.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 78fa1fa162..45b6cf1cfa 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -87,17 +87,17 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, ui= nt64_t type, =20 #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ do { \ - int ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ - if (ret) { \ - return ret; \ + int _ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + if (_ret) { \ + return _ret; \ } \ } while (0) =20 #define KVM_RISCV_SET_CSR(cs, env, csr, reg) \ do { \ - int ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ - if (ret) { \ - return ret; \ + int _ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \ + if (_ret) { \ + return _ret; \ } \ } while (0) =20 @@ -533,7 +533,6 @@ static int kvm_riscv_put_regs_core(CPUState *cs) =20 static int kvm_riscv_get_regs_csr(CPUState *cs) { - int ret =3D 0; CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus); @@ -545,12 +544,12 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) KVM_RISCV_GET_CSR(cs, env, stval, env->stval); KVM_RISCV_GET_CSR(cs, env, sip, env->mip); KVM_RISCV_GET_CSR(cs, env, satp, env->satp); - return ret; + + return 0; } =20 static int kvm_riscv_put_regs_csr(CPUState *cs) { - int ret =3D 0; CPURISCVState *env =3D &RISCV_CPU(cs)->env; =20 KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus); @@ -563,7 +562,7 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) KVM_RISCV_SET_CSR(cs, env, sip, env->mip); KVM_RISCV_SET_CSR(cs, env, satp, env->satp); =20 - return ret; + return 0; } =20 static int kvm_riscv_get_regs_fp(CPUState *cs) --=20 2.41.0