From nobody Wed Nov 27 04:58:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701355073; cv=none; d=zohomail.com; s=zohoarc; b=RS9E8KFvaP7HfMnkDpTYswda8cMt0tteCF1IkpDMUHWI7PWcURNIYTcfQi+5lg1zdFpdGI+oFHqyUrNX687N8t6HDvo/zIypC0Fz3Z19C6tgqrNM5FDKlI0LB6vnsu8osuLpA9Y9d12pM41Tl7hdOIEEmgldBXNspM3hmS/FtnY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701355073; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UqEymSnO2UJ/jOwqPdfEx0Diu6WiaJcggjFVME9na9o=; b=mF0r4HirXMxEQ3n5nhcW9zO0J8a6ujKPXdhy5rqdy5o6fWSyk9VZjivcDwE6tAD/Xfj60leQw1Ao4EeiYI5gNhoKeAVKJmMl+JDqxoTqgwLVVW9hg/G9BdQM9riw0HQoAoJAmy1sPpDiMUtU+UZ6CNvhyoxybanHAsCyer+/vAc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1701355073216251.5429795019412; Thu, 30 Nov 2023 06:37:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r8i9K-0002pz-J1; Thu, 30 Nov 2023 09:36:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i8t-0001gQ-0c; Thu, 30 Nov 2023 09:35:54 -0500 Received: from mgamail.intel.com ([192.55.52.43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i8q-0001tW-SM; Thu, 30 Nov 2023 09:35:50 -0500 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 06:35:45 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga005.jf.intel.com with ESMTP; 30 Nov 2023 06:35:35 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701354948; x=1732890948; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zMs3wimSwFi3OS/xT8fCJCLyivsPCu0OTNgeR6TOgP0=; b=UNDKxkCO8wZu9qJumGgCM6x621nMt5fUsWIH9bYZypa+i9jJ6+U+Jk76 PlrgEIgxpDjr/VAC4ORzqlMdmxEw9tVNlcSfirr9Nze0TvRnj+cPS2zkk BGDzQeZJmbmC/K8x8OYqHNIWerHNNosWoz8Yn4mPWC+6J3Cou5aiRe5UM n9ELpAx+UD4JPc08Hy5vmAHXYBa4p5ohszmw2jZmo3ghSpM96nluCnraI oRaHOsK+7ZfPUbG3tSkRSI4N+St/T97S8/Kgz0xdrTZfL94R8shG+NyuS pPAoJJx1qUjxI1sK1VE0/bJpQz+mPJ4QS2jLL+BTZaF04JnQCMo7bMFMq Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="479532481" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="479532481" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="942730310" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="942730310" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Richard Henderson , "Michael S . Tsirkin" , Jason Wang , Nicholas Piggin , Daniel Henrique Barboza , Igor Mammedov , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , David Gibson , Harsh Prateek Bora , Stefano Stabellini , Anthony Perard , Paul Durrant , Gerd Hoffmann , Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, xen-devel@lists.xenproject.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: Nina Schoetterl-Glausch , Thomas Huth , Zhiyuan Lv , Zhenyu Wang , Yongwei Ma , Zhao Liu Subject: [RFC 33/41] hw/machine: Validate smp topology tree without -smp Date: Thu, 30 Nov 2023 22:41:55 +0800 Message-Id: <20231130144203.2307629-34-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> References: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.43; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1701355073697000001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu QOM topology allows user to create topology tree from cli without -smp, in this case, validate the topology tree to meet the smp requirement. Currently, for compatibility with MachineState.smp, initialize MachineState.smp from topology tree in this case. Signed-off-by: Zhao Liu --- hw/core/cpu-slot.c | 146 +++++++++++++++++++++++++++++++++++++ hw/core/machine.c | 10 +++ include/hw/core/cpu-slot.h | 1 + 3 files changed, 157 insertions(+) diff --git a/hw/core/cpu-slot.c b/hw/core/cpu-slot.c index ade155baf60b..45b6aef0750a 100644 --- a/hw/core/cpu-slot.c +++ b/hw/core/cpu-slot.c @@ -413,3 +413,149 @@ void machine_create_smp_topo_tree(MachineState *ms, E= rror **errp) } slot->smp_parsed =3D true; } + +static void set_smp_child_topo_info(CpuTopology *smp_info, + CPUTopoStat *stat, + CPUTopoLevel child_level) +{ + unsigned int *smp_count; + CPUTopoStatEntry *entry; + + smp_count =3D get_smp_info_by_level(smp_info, child_level); + entry =3D get_topo_stat_entry(stat, child_level); + *smp_count =3D entry->max_units ? entry->max_units : 1; + + return; +} + +typedef struct ValidateCbData { + CPUTopoStat *stat; + CpuTopology *smp_info; + Error **errp; +} ValidateCbData; + +static int validate_topo_children(CPUTopoState *topo, void *opaque) +{ + CPUTopoLevel level =3D CPU_TOPO_LEVEL(topo), next_level; + ValidateCbData *cb =3D opaque; + unsigned int max_children; + CPUTopoStatEntry *entry; + Error **errp =3D cb->errp; + + if (level !=3D CPU_TOPO_THREAD && !topo->num_children && + !topo->max_children) { + error_setg(errp, "Invalid topology: the CPU topology " + "(level: %s, index: %d) isn't completed.", + cpu_topo_level_to_string(level), topo->index); + return TOPO_FOREACH_ERR; + } + + if (level =3D=3D CPU_TOPO_UNKNOWN) { + error_setg(errp, "Invalid CPU topology: unknown topology level."); + return TOPO_FOREACH_ERR; + } + + /* + * Only CPU_TOPO_THREAD level's child_level could be CPU_TOPO_UNKNOWN, + * but machine_validate_cpu_topology() is before CPU creation. + */ + if (topo->child_level =3D=3D CPU_TOPO_UNKNOWN) { + error_setg(errp, "Invalid CPU topology: incomplete topology " + "(level: %s, index: %d), no child?.", + cpu_topo_level_to_string(level), topo->index); + return TOPO_FOREACH_ERR; + } + + /* + * Currently hybrid topology isn't supported, so only SMP topology + * is allowed. + */ + + entry =3D get_topo_stat_entry(cb->stat, topo->child_level); + + /* Max threads per core is pre-configured by "nr-threads". */ + max_children =3D topo->child_level !=3D CPU_TOPO_THREAD ? + topo->num_children : topo->max_children; + + if (entry->max_units !=3D max_children) { + error_setg(errp, "Invalid SMP topology: " + "The %s topology is asymmetric.", + cpu_topo_level_to_string(level)); + return TOPO_FOREACH_ERR; + } + + next_level =3D find_next_bit(cb->stat->curr_levels, USER_AVAIL_LEVEL_N= UM, + topo->child_level + 1); + + if (next_level !=3D level) { + error_setg(errp, "Invalid smp topology: " + "asymmetric CPU topology depth."); + return TOPO_FOREACH_ERR; + } + + set_smp_child_topo_info(cb->smp_info, cb->stat, topo->child_level); + + return TOPO_FOREACH_CONTINUE; +} + +/* + * Only check the case user configures CPU topology via -device + * without -smp. In this case, MachineState.smp also needs to be + * initialized based on topology tree. + */ +bool machine_validate_cpu_topology(MachineState *ms, Error **errp) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + CPUTopoState *slot_topo =3D CPU_TOPO(ms->topo); + CPUTopoStat *stat =3D &ms->topo->stat; + CpuTopology *smp_info =3D &ms->smp; + unsigned int total_cpus; + ValidateCbData cb; + + if (ms->topo->smp_parsed) { + return true; + } else if (!slot_topo->num_children) { + /* + * If there's no -smp nor -device to add topology children, + * then create the default topology. + */ + machine_create_smp_topo_tree(ms, errp); + if (*errp) { + return false; + } + return true; + } + + if (test_bit(CPU_TOPO_CLUSTER, stat->curr_levels)) { + mc->smp_props.has_clusters =3D true; + } + + /* + * The next cpu_topo_child_foreach_recursive() doesn't cover the + * parent topology unit. Update information for root here. + */ + set_smp_child_topo_info(smp_info, stat, slot_topo->child_level); + + cb.stat =3D stat; + cb.smp_info =3D smp_info; + cb.errp =3D errp; + + cpu_topo_child_foreach_recursive(slot_topo, NULL, + validate_topo_children, &cb); + if (*errp) { + return false; + } + + ms->smp.cpus =3D stat->pre_plugged_cpus ? + stat->pre_plugged_cpus : 1; + ms->smp.max_cpus =3D stat->max_cpus ? + stat->max_cpus : 1; + + total_cpus =3D ms->smp.drawers * ms->smp.books * + ms->smp.sockets * ms->smp.dies * + ms->smp.clusters * ms->smp.cores * + ms->smp.threads; + g_assert(total_cpus =3D=3D ms->smp.max_cpus); + + return true; +} diff --git a/hw/core/machine.c b/hw/core/machine.c index 0c1739814124..5fa0c826f35e 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1505,6 +1505,16 @@ void machine_run_board_init(MachineState *machine, c= onst char *mem_path, Error * "on", false); } =20 + /* + * TODO: drop this check and validate topology tree by default + * when all arches support QOM topology. + */ + if (machine_class->smp_props.possible_cpus_qom_granu) { + if (!machine_validate_cpu_topology(machine, errp)) { + return; + } + } + accel_init_interfaces(ACCEL_GET_CLASS(machine->accelerator)); machine_class->init(machine); phase_advance(PHASE_MACHINE_INITIALIZED); diff --git a/include/hw/core/cpu-slot.h b/include/hw/core/cpu-slot.h index de3d08fcb2ac..9e1c6d6b7ff2 100644 --- a/include/hw/core/cpu-slot.h +++ b/include/hw/core/cpu-slot.h @@ -100,5 +100,6 @@ struct CPUSlot { =20 void machine_plug_cpu_slot(MachineState *ms); void machine_create_smp_topo_tree(MachineState *ms, Error **errp); +bool machine_validate_cpu_topology(MachineState *ms, Error **errp); =20 #endif /* CPU_SLOT_H */ --=20 2.34.1