From nobody Wed Nov 27 04:56:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701355013; cv=none; d=zohomail.com; s=zohoarc; b=ngmjK627zl/nQGGhnQDVwqR0kAhQIdPk97C5un0R582HYeFkrtt4+vdXhRMLmKzn64GfdT7Oh/aHcwYS2tni48SKhd7k0AxpwpmSdhf5B34lTgJyCy2Hr0QImCj1v4j5HpfGgExrXWKbNeIj12n1wz8p5JwNsRea5OrbQA4shro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701355013; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Sn66a9bPrp4KNlWbcDoa9kt45YGbbvfHbM1x5RGU4U0=; b=CVIsFgJKItOJRLivlNlPfrF7wJY8rRg6TbKlZqEDWzh+pbW6VZcQX0Re+F19JsSdaupbUDOx7f+GW1rVKsxJlMMh0oo07HrXaGG5OfErRfgHY3lYiAdhYO6YtH4Fc6XjDtb9+IqoBk/obiNmpnVWQigH/q7Z0mMBBbDjrQvRRO0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1701355013985735.3822394645864; Thu, 30 Nov 2023 06:36:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r8i9G-0002PU-J6; Thu, 30 Nov 2023 09:36:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i8d-0001Mn-MP; Thu, 30 Nov 2023 09:35:37 -0500 Received: from mgamail.intel.com ([192.55.52.43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i8Z-0001tW-Iw; Thu, 30 Nov 2023 09:35:34 -0500 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 06:35:24 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga005.jf.intel.com with ESMTP; 30 Nov 2023 06:35:15 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701354931; x=1732890931; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f8dzVIiaV15FUJhTAcShJBTihquI/MGo+GvFSgqbGOs=; b=CGADjJyleEKvWjqLrSJqVu4kQIgphAR6wQBD/Ifbpfz6FaifT2b2RMtv 6RRLZSPtCxGEWieNH3cKDepxb7AIX+Tjv5VkxMn6wovUb+Ac6gfYpCLgr b/d+zRibQg31wk6uOJ685WQbiyMv/Loxx9gskj5FQamRVp3rY5c8oH8Ae +sqzovCYUgjtyVrDM2f9b2rdaMhNnkEXHj5TvkYetiiuIj6bsP0stUYIa xBuasb+QK9N60wOvYZjpcT7wJTUwoYXIyv7/Bf9OWH0cWJ/YwIjXj2LS4 5o85lIY5LDZT/Xe7gf0b3aOZKf8R4meZ4v+lhIkDDZV8RdFVoBvGr4a2C g==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="479532412" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="479532412" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="942730271" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="942730271" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Richard Henderson , "Michael S . Tsirkin" , Jason Wang , Nicholas Piggin , Daniel Henrique Barboza , Igor Mammedov , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , David Gibson , Harsh Prateek Bora , Stefano Stabellini , Anthony Perard , Paul Durrant , Gerd Hoffmann , Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, xen-devel@lists.xenproject.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: Nina Schoetterl-Glausch , Thomas Huth , Zhiyuan Lv , Zhenyu Wang , Yongwei Ma , Zhao Liu Subject: [RFC 31/41] hw/machine: Plug cpu-slot into machine to maintain topology tree Date: Thu, 30 Nov 2023 22:41:53 +0800 Message-Id: <20231130144203.2307629-32-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> References: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.43; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1701355015368000003 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Add a cpu-slot in machine as the root of topology tree to maintain the QOM topology. Signed-off-by: Zhao Liu --- hw/core/cpu-slot.c | 31 +++++++++++++++++++++++++++++++ include/hw/boards.h | 2 ++ include/hw/core/cpu-slot.h | 7 +++++++ system/vl.c | 2 ++ 4 files changed, 42 insertions(+) diff --git a/hw/core/cpu-slot.c b/hw/core/cpu-slot.c index 2a796ad5b6e7..4b148440ed3d 100644 --- a/hw/core/cpu-slot.c +++ b/hw/core/cpu-slot.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" =20 +#include "hw/boards.h" #include "hw/core/cpu-slot.h" #include "qapi/error.h" =20 @@ -165,3 +166,33 @@ static void cpu_slot_register_types(void) } =20 type_init(cpu_slot_register_types) + +void machine_plug_cpu_slot(MachineState *ms) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + + ms->topo =3D CPU_SLOT(qdev_new(TYPE_CPU_SLOT)); + + object_property_add_child(container_get(OBJECT(ms), "/peripheral"), + "cpu-slot", OBJECT(ms->topo)); + DEVICE(ms->topo)->id =3D g_strdup_printf("%s", "cpu-slot"); + + qdev_realize_and_unref(DEVICE(ms->topo), NULL, &error_abort); + ms->topo->ms =3D ms; + + if (!mc->smp_props.clusters_supported) { + clear_bit(CPU_TOPO_CLUSTER, ms->topo->supported_levels); + } + + if (!mc->smp_props.dies_supported) { + clear_bit(CPU_TOPO_DIE, ms->topo->supported_levels); + } + + if (!mc->smp_props.books_supported) { + clear_bit(CPU_TOPO_BOOK, ms->topo->supported_levels); + } + + if (!mc->smp_props.drawers_supported) { + clear_bit(CPU_TOPO_DRAWER, ms->topo->supported_levels); + } +} diff --git a/include/hw/boards.h b/include/hw/boards.h index da85f86efb91..81a7b04ece86 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -10,6 +10,7 @@ #include "qemu/module.h" #include "qom/object.h" #include "hw/core/cpu.h" +#include "hw/core/cpu-slot.h" =20 #define TYPE_MACHINE_SUFFIX "-machine" =20 @@ -398,6 +399,7 @@ struct MachineState { AccelState *accelerator; CPUArchIdList *possible_cpus; CpuTopology smp; + CPUSlot *topo; struct NVDIMMState *nvdimms_state; struct NumaState *numa_state; }; diff --git a/include/hw/core/cpu-slot.h b/include/hw/core/cpu-slot.h index 7bf51988afb3..1361af4ccfc0 100644 --- a/include/hw/core/cpu-slot.h +++ b/include/hw/core/cpu-slot.h @@ -78,6 +78,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(CPUSlot, CPU_SLOT) * when necessary. * @stat: Statistical topology information for topology tree. * @supported_levels: Supported topology levels for topology tree. + * @ms: Machine in which this cpu-slot is plugged. */ struct CPUSlot { /*< private >*/ @@ -87,6 +88,12 @@ struct CPUSlot { QTAILQ_HEAD(, CPUCore) cores; CPUTopoStat stat; DECLARE_BITMAP(supported_levels, USER_AVAIL_LEVEL_NUM); + MachineState *ms; }; =20 +#define MACHINE_CORE_FOREACH(ms, core) \ + QTAILQ_FOREACH((core), &(ms)->topo->cores, node) + +void machine_plug_cpu_slot(MachineState *ms); + #endif /* CPU_SLOT_H */ diff --git a/system/vl.c b/system/vl.c index 65add2fb2460..637f708d2265 100644 --- a/system/vl.c +++ b/system/vl.c @@ -2128,6 +2128,8 @@ static void qemu_create_machine(QDict *qdict) false, &error_abort); qobject_unref(default_opts); } + + machine_plug_cpu_slot(current_machine); } =20 static int global_init_func(void *opaque, QemuOpts *opts, Error **errp) --=20 2.34.1