From nobody Wed Nov 27 04:57:50 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701355162; cv=none; d=zohomail.com; s=zohoarc; b=fZglFXQZsilQN7oNgAO7bx7uN+i1bJzDW6z6WCbb0g+WapjrRswERZ6gt657BxSht40m7Ozg/RwobBV/he1JQd4E9D8mt3798kut770EfUP8t5TwwY8A0WBA6PyS7L8D3KXGm40RkFk1vU9GJy2k3glfHPAA99RRbSDMYD1jvgQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701355162; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OmYa/5gkNTA0z+R1wsqm4BWqfL45cJ4MgBQ2Q5U3oKw=; b=j7WozlRox4S2FrnMxkpfRn8um50mE3FUNImaNkxv43aIrXH9OzfdeAgi+iaGP19sj2fiAjLs6qv8gMYdj6sXXFSI7/Z35DnbEHTQCkWzXE8hx8RuSmbx3Yh/cHZd+b3Ic0XIAsMxGl1Wh69PMHFi28LzsDOfFNKXfCPQrDI2K1g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1701355162694648.5871460038877; Thu, 30 Nov 2023 06:39:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r8i9C-0001ov-Ti; Thu, 30 Nov 2023 09:36:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i8P-000160-5z; Thu, 30 Nov 2023 09:35:21 -0500 Received: from mgamail.intel.com ([192.55.52.43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i8N-0001qi-0i; Thu, 30 Nov 2023 09:35:20 -0500 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 06:35:15 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga005.jf.intel.com with ESMTP; 30 Nov 2023 06:35:05 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701354919; x=1732890919; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HnOAO3NMx1dRMWQIeSpDRtg/0be+6N1pOpK/5nWbTXE=; b=DU//5S62izPMvrZxFxAZ+lXRnPSNs+WPPZo3blL01HjQnSB+k0fbnken SPWJSMf6BdFDdQVGIkQ/Nkf2AM8r474YR8K3mti69JfmDfMomfR2DL1iE eZ1NYFdDxgipBwVhx6s12tyUvhRoj5W07EEFmHToWCjEiv+xCpUETKPCc JUJyMUQigyrZ5UXyFR+zuMe1z9xxWtV9xNPHz18YKczbHY6FmqCimC+AE tvczfUfokmf0/ACnITmMTIHHebLoB7FF/d90TA7mjrnwXyM45GRirpTn5 uxz1x3amwbukUmGBQBCeohOb+ZdkqfSCyvIfWacvMPaedJ2zucc7F3RHW A==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="479532380" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="479532380" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="942730225" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="942730225" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Richard Henderson , "Michael S . Tsirkin" , Jason Wang , Nicholas Piggin , Daniel Henrique Barboza , Igor Mammedov , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , David Gibson , Harsh Prateek Bora , Stefano Stabellini , Anthony Perard , Paul Durrant , Gerd Hoffmann , Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, xen-devel@lists.xenproject.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: Nina Schoetterl-Glausch , Thomas Huth , Zhiyuan Lv , Zhenyu Wang , Yongwei Ma , Zhao Liu Subject: [RFC 30/41] hw/core/slot: Check topology child to be added under CPU slot Date: Thu, 30 Nov 2023 22:41:52 +0800 Message-Id: <20231130144203.2307629-31-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> References: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.43; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1701355163831000003 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Implement CPUTopoClass.check_topo_child() in cpu-slot to be compatible with the limitations of the current smp topology. Signed-off-by: Zhao Liu --- hw/core/cpu-slot.c | 37 +++++++++++++++++++++++++++++++++++++ hw/core/cpu-topo.c | 2 +- include/hw/core/cpu-slot.h | 2 ++ include/hw/core/cpu-topo.h | 1 + 4 files changed, 41 insertions(+), 1 deletion(-) diff --git a/hw/core/cpu-slot.c b/hw/core/cpu-slot.c index e8e6f4d25532..2a796ad5b6e7 100644 --- a/hw/core/cpu-slot.c +++ b/hw/core/cpu-slot.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" =20 #include "hw/core/cpu-slot.h" +#include "qapi/error.h" =20 static inline CPUTopoStatEntry *get_topo_stat_entry(CPUTopoStat *stat, @@ -94,6 +95,37 @@ static void cpu_slot_update_topo_info(CPUTopoState *root= , CPUTopoState *child, } } =20 +static void cpu_slot_check_topo_support(CPUTopoState *root, CPUTopoState *= child, + Error **errp) +{ + CPUSlot *slot =3D CPU_SLOT(root); + CPUTopoLevel child_level =3D CPU_TOPO_LEVEL(child); + + if (!test_bit(child_level, slot->supported_levels)) { + error_setg(errp, "cpu topo: the level %s is not supported", + cpu_topo_level_to_string(child_level)); + return; + } + + /* + * Currently we doesn't support hybrid topology. For SMP topology, + * each child under the same parent are same type. + */ + if (child->parent->num_children) { + CPUTopoState *sibling =3D QTAILQ_FIRST(&child->parent->children); + const char *sibling_type =3D object_get_typename(OBJECT(sibling)); + const char *child_type =3D object_get_typename(OBJECT(child)); + + if (strcmp(sibling_type, child_type)) { + error_setg(errp, "Invalid smp topology: different CPU " + "topology types (%s child vs %s sibling) " + "under the same parent (%s).", + child_type, sibling_type, + object_get_typename(OBJECT(child->parent))); + } + } +} + static void cpu_slot_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -104,6 +136,7 @@ static void cpu_slot_class_init(ObjectClass *oc, void *= data) =20 tc->level =3D CPU_TOPO_ROOT; tc->update_topo_info =3D cpu_slot_update_topo_info; + tc->check_topo_child =3D cpu_slot_check_topo_support; } =20 static void cpu_slot_instance_init(Object *obj) @@ -112,6 +145,10 @@ static void cpu_slot_instance_init(Object *obj) =20 QTAILQ_INIT(&slot->cores); set_bit(CPU_TOPO_ROOT, slot->stat.curr_levels); + + /* Set all levels by default. */ + bitmap_fill(slot->supported_levels, USER_AVAIL_LEVEL_NUM); + clear_bit(CPU_TOPO_UNKNOWN, slot->supported_levels); } =20 static const TypeInfo cpu_slot_type_info =3D { diff --git a/hw/core/cpu-topo.c b/hw/core/cpu-topo.c index 687a4cc566ec..351112ca7a73 100644 --- a/hw/core/cpu-topo.c +++ b/hw/core/cpu-topo.c @@ -24,7 +24,7 @@ #include "hw/qdev-properties.h" #include "qapi/error.h" =20 -static const char *cpu_topo_level_to_string(CPUTopoLevel level) +const char *cpu_topo_level_to_string(CPUTopoLevel level) { switch (level) { case CPU_TOPO_UNKNOWN: diff --git a/include/hw/core/cpu-slot.h b/include/hw/core/cpu-slot.h index fa2bd4af247d..7bf51988afb3 100644 --- a/include/hw/core/cpu-slot.h +++ b/include/hw/core/cpu-slot.h @@ -77,6 +77,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(CPUSlot, CPU_SLOT) * queues for other topology levels to facilitate traversal * when necessary. * @stat: Statistical topology information for topology tree. + * @supported_levels: Supported topology levels for topology tree. */ struct CPUSlot { /*< private >*/ @@ -85,6 +86,7 @@ struct CPUSlot { /*< public >*/ QTAILQ_HEAD(, CPUCore) cores; CPUTopoStat stat; + DECLARE_BITMAP(supported_levels, USER_AVAIL_LEVEL_NUM); }; =20 #endif /* CPU_SLOT_H */ diff --git a/include/hw/core/cpu-topo.h b/include/hw/core/cpu-topo.h index 453bacbb558b..d27da0335c42 100644 --- a/include/hw/core/cpu-topo.h +++ b/include/hw/core/cpu-topo.h @@ -102,5 +102,6 @@ int cpu_topo_child_foreach(CPUTopoState *topo, unsigned= long *levels, int cpu_topo_child_foreach_recursive(CPUTopoState *topo, unsigned long *levels, topo_fn fn, void *opaque); +const char *cpu_topo_level_to_string(CPUTopoLevel level); =20 #endif /* CPU_TOPO_H */ --=20 2.34.1