From nobody Wed Nov 27 04:38:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701354987; cv=none; d=zohomail.com; s=zohoarc; b=HIFYWMjfPK7iYAmmOnTZx2xY8WbSe3GLw4DWthLj7Y886INSLRsm/jbWRyD3J+07N6xuc5Y9jlH1CmOLnjRAUKBUxvSwwNNufkBg6RoLyGdscD0xDadlq+NI6Qo2wISHWYChTs4JncPksK9I3h8ETlUBNcqGJJ2Zgj5aebQpUwE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701354987; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hX8MTd+RhIF3J7qaJiG28gdCnUnyZmf+y1qQCDMVFpQ=; b=CdJN6fClyuAZto4xIjcxrYaLDlnunhlIDLgorLkWCaO1FV/KS5N8ifu9SnPc3mTP5eeqbVStDe+F66bz7GcGvsDR7e89+oBZmAEl6oWrWIzjmGlwfjWywiDPLIqxRA6Ga2l3WaEqfz3TkDVFjnD62sc1vhunnKK6HFERnbSmB6Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1701354987073715.048788140689; Thu, 30 Nov 2023 06:36:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r8i87-0000EN-VS; Thu, 30 Nov 2023 09:35:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i85-0008Tr-2S; Thu, 30 Nov 2023 09:35:01 -0500 Received: from mgamail.intel.com ([192.55.52.43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i7u-0001Un-SP; Thu, 30 Nov 2023 09:35:00 -0500 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 06:34:47 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga005.jf.intel.com with ESMTP; 30 Nov 2023 06:34:37 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701354890; x=1732890890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dK+ilj3Q1LqgiJ2/EiJWYjQp1qXfjG6+/g3hE8BTtcM=; b=CBoT00iUZavpZrRiU+b75R3pv+ggnBmPYkA3OVVGpHXlZXP8BkmReFDL nzeSWUyj86Om8LG3Oo1r9VMeI65OwpvuxWrFhU3VZceg2WWm7mprZPB8H /hEHgeFxedIEmnF1fz7PgisTHufE7jUa1IA57P/voCJv+8Q+JGgXzb5m7 oPFy5gQUszeQtZMhjsq/A23VTZsykpJePbeOkHGAR2T1e2diCfKkTTvDt 9gzJVjwnfi5vDparYIc7r+I74W4s8n8iRHof2pRhee2Img3sjbO/0g7wu uxg7XTPHEF1d5qGpP/m4t+cAiuWyGXXTtrnryn0gauXUGocEcnvUfdY2M g==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="479532284" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="479532284" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="942730118" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="942730118" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Richard Henderson , "Michael S . Tsirkin" , Jason Wang , Nicholas Piggin , Daniel Henrique Barboza , Igor Mammedov , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , David Gibson , Harsh Prateek Bora , Stefano Stabellini , Anthony Perard , Paul Durrant , Gerd Hoffmann , Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, xen-devel@lists.xenproject.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: Nina Schoetterl-Glausch , Thomas Huth , Zhiyuan Lv , Zhenyu Wang , Yongwei Ma , Zhao Liu Subject: [RFC 27/41] hw/core/slot: Introduce CPU slot as the root of CPU topology Date: Thu, 30 Nov 2023 22:41:49 +0800 Message-Id: <20231130144203.2307629-28-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> References: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.43; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1701354987217000004 From: Zhao Liu Abstract the root of topology tree as a special topology device "cpu-slot". Signed-off-by: Zhao Liu --- MAINTAINERS | 2 ++ hw/core/cpu-slot.c | 48 ++++++++++++++++++++++++++++++++++++++ hw/core/meson.build | 1 + include/hw/core/cpu-slot.h | 38 ++++++++++++++++++++++++++++++ 4 files changed, 89 insertions(+) create mode 100644 hw/core/cpu-slot.c create mode 100644 include/hw/core/cpu-slot.h diff --git a/MAINTAINERS b/MAINTAINERS index 4b373ff46ce3..ac08b5a8c4e0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1856,6 +1856,7 @@ R: Philippe Mathieu-Daud=C3=A9 R: Yanan Wang S: Supported F: hw/core/cpu.c +F: hw/core/cpu-slot.c F: hw/core/cpu-topo.c F: hw/core/machine-qmp-cmds.c F: hw/core/machine.c @@ -1872,6 +1873,7 @@ F: qapi/machine-common.json F: qapi/machine-target.json F: include/hw/boards.h F: include/hw/core/cpu.h +F: include/hw/core/cpu-slot.h F: include/hw/core/cpu-topo.h F: include/hw/cpu/book.h F: include/hw/cpu/cluster.h diff --git a/hw/core/cpu-slot.c b/hw/core/cpu-slot.c new file mode 100644 index 000000000000..5aef5b0189c2 --- /dev/null +++ b/hw/core/cpu-slot.c @@ -0,0 +1,48 @@ +/* + * CPU slot device abstraction + * + * Copyright (c) 2023 Intel Corporation + * Author: Zhao Liu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" + +#include "hw/core/cpu-slot.h" + +static void cpu_slot_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + CPUTopoClass *tc =3D CPU_TOPO_CLASS(oc); + + set_bit(DEVICE_CATEGORY_CPU_DEF, dc->categories); + dc->user_creatable =3D false; + + tc->level =3D CPU_TOPO_ROOT; +} + +static const TypeInfo cpu_slot_type_info =3D { + .name =3D TYPE_CPU_SLOT, + .parent =3D TYPE_CPU_TOPO, + .class_init =3D cpu_slot_class_init, + .instance_size =3D sizeof(CPUSlot), +}; + +static void cpu_slot_register_types(void) +{ + type_register_static(&cpu_slot_type_info); +} + +type_init(cpu_slot_register_types) diff --git a/hw/core/meson.build b/hw/core/meson.build index 501d2529697e..3347c054e162 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -23,6 +23,7 @@ else endif =20 common_ss.add(files('cpu-common.c')) +common_ss.add(files('cpu-slot.c')) common_ss.add(files('cpu-topo.c')) common_ss.add(files('machine-smp.c')) system_ss.add(when: 'CONFIG_FITLOADER', if_true: files('loader-fit.c')) diff --git a/include/hw/core/cpu-slot.h b/include/hw/core/cpu-slot.h new file mode 100644 index 000000000000..718c8ecaa751 --- /dev/null +++ b/include/hw/core/cpu-slot.h @@ -0,0 +1,38 @@ +/* + * CPU slot device abstraction + * + * Copyright (c) 2023 Intel Corporation + * Author: Zhao Liu + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef CPU_SLOT_H +#define CPU_SLOT_H + +#include "hw/core/cpu-topo.h" +#include "hw/qdev-core.h" + +#define TYPE_CPU_SLOT "cpu-slot" + +OBJECT_DECLARE_SIMPLE_TYPE(CPUSlot, CPU_SLOT) + +struct CPUSlot { + /*< private >*/ + CPUTopoState parent_obj; + + /*< public >*/ +}; + +#endif /* CPU_SLOT_H */ --=20 2.34.1