From nobody Wed Nov 27 04:40:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1701355100; cv=none; d=zohomail.com; s=zohoarc; b=WfpDyMNSBGVG3ATrR4UVSy88NgF6MjVLcIswHxIVFzDlcKxwgZfme/uXZVoxUWF09LaqH2hpwBmh/X2+7BnM8gIBwGFp88OGJoghQZcII3QXkR4EA/OmEOQgfo9D96I514au3YGn7fmJ/vd/5PUP/sw5sUV5yPGFbLL/NRvoiaQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1701355100; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=otuZ4A5xDRsI78OdpqRPKGDlC2fBE+12r54swMx5LHw=; b=jbrohXVk+K7cYrEw+YRxuEPP81kzoXexSVWRMlqQaodPgogHTEk/sGTEzn9UvsjtZjkMkLsXEZaUjk55RQbG/QzcTfveegXvwuCvXUUIXDok6uWoi3xeMOqQbhkHAyPEWhZnduggF5SNcMv4fAl7yMN8QTDtmkYxi+pQbhNv2o4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 170135510001933.83769836996453; Thu, 30 Nov 2023 06:38:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r8i7M-0006Q3-NT; Thu, 30 Nov 2023 09:34:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i6k-0005qt-Iv; Thu, 30 Nov 2023 09:33:40 -0500 Received: from mgamail.intel.com ([192.55.52.43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r8i6i-0001RT-8O; Thu, 30 Nov 2023 09:33:38 -0500 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Nov 2023 06:33:32 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.36]) by orsmga005.jf.intel.com with ESMTP; 30 Nov 2023 06:33:22 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701354816; x=1732890816; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ewTMs2u73zZUV2zJblGAkkri1EYaJm+RSs7ZWl9w7g8=; b=ObtDTnZKhzx71/fy1sMds76oOx6R/DHFRvy3OH1z+Sp2VD4MufcayHji a4Zj4jiMJAHMnI45dfJ/b55phnK2IvSYIf/oDnr+qxKlkAzKJq9Tj1sy6 zj1YDYDEVxna9DyTxZi5r0C+bT5o2fjD47rVixkcR6Tm5fxOamoJKT7Hy IpimkBZk1OSXww1cVtblCRnvKIvkTPsrMYKYX3NuvNw34wBl+cyLRY7cE /McbdqOTHw2l3aZhLqJSlgI4VTE0h/4vrs1+ceSR10Jsv0d8GxtY7c+zB kI0/5BIrUJcFq7+4vyVUwuLIxBw1TiA1laMWmjKZYdP5NkDkfdJX/a/Mk A==; X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="479531981" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="479531981" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10910"; a="942730032" X-IronPort-AV: E=Sophos;i="6.04,239,1695711600"; d="scan'208";a="942730032" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang , Richard Henderson , "Michael S . Tsirkin" , Jason Wang , Nicholas Piggin , Daniel Henrique Barboza , Igor Mammedov , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , =?UTF-8?q?Fr=C3=A9d=C3=A9ric=20Barrat?= , David Gibson , Harsh Prateek Bora , Stefano Stabellini , Anthony Perard , Paul Durrant , Gerd Hoffmann , Peter Maydell , Alistair Francis , "Edgar E . Iglesias" , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Bin Meng , Palmer Dabbelt , Weiwei Li , Liu Zhiwei , qemu-devel@nongnu.org, kvm@vger.kernel.org, qemu-ppc@nongnu.org, xen-devel@lists.xenproject.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Cc: Nina Schoetterl-Glausch , Thomas Huth , Zhiyuan Lv , Zhenyu Wang , Yongwei Ma , Zhao Liu Subject: [RFC 19/41] hw/cpu/cluster: Wrap TCG related ops and props into CONFIG_TCG Date: Thu, 30 Nov 2023 22:41:41 +0800 Message-Id: <20231130144203.2307629-20-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> References: <20231130144203.2307629-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.43; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -42 X-Spam_score: -4.3 X-Spam_bar: ---- X-Spam_report: (-4.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1701355101637000007 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Currenltly cpu-cluster is used in TCG case to organize CPUs with the same type. Wrap 2 things into TCG specific areas: 1. cluster-id: The cluster-id in TCG case is global, since no higher topology container above cluster. To simplify the logic of cluster topology in virtualization, move the cluster-id into CONFIG_TCG, then it won't be exposed in cli. 2. CPU collection in realize(): In TCG case, the CPUs are added into cluster directly via child<> property. But in virtualization case, the CPU topology will be built via topology tree. Thus, wrap CPU collection as the TCG operation. Signed-off-by: Zhao Liu --- hw/cpu/cluster.c | 30 +++++++++++++++++++++++++----- include/hw/cpu/cluster.h | 22 ++++++++++++++++++++-- 2 files changed, 45 insertions(+), 7 deletions(-) diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index fd978a543e40..340cfad9f8f1 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -26,7 +26,9 @@ #include "qapi/error.h" =20 static Property cpu_cluster_properties[] =3D { +#ifdef CONFIG_TCG DEFINE_PROP_UINT32("cluster-id", CPUCluster, cluster_id, 0), +#endif DEFINE_PROP_END_OF_LIST() }; =20 @@ -47,18 +49,17 @@ static int add_cpu_to_cluster(Object *obj, void *opaque) return 0; } =20 -static void cpu_cluster_realize(DeviceState *dev, Error **errp) +static void cpu_cluster_common_collect_cpus(CPUCluster *cluster, Error **e= rrp) { /* Iterate through all our CPU children and set their cluster_index */ - CPUCluster *cluster =3D CPU_CLUSTER(dev); - Object *cluster_obj =3D OBJECT(dev); + Object *cluster_obj =3D OBJECT(cluster); CallbackData cbdata =3D { .cluster =3D cluster, .cpu_count =3D 0, }; =20 - if (cluster->cluster_id >=3D MAX_CLUSTERS) { - error_setg(errp, "cluster-id must be less than %d", MAX_CLUSTERS); + if (cluster->cluster_id >=3D MAX_TCG_CLUSTERS) { + error_setg(errp, "cluster-id must be less than %d", MAX_TCG_CLUSTE= RS); return; } =20 @@ -73,15 +74,34 @@ static void cpu_cluster_realize(DeviceState *dev, Error= **errp) assert(cbdata.cpu_count > 0); } =20 +static const struct TCGClusterOps common_cluster_tcg_ops =3D { + .collect_cpus =3D cpu_cluster_common_collect_cpus, +}; + +static void cpu_cluster_realize(DeviceState *dev, Error **errp) +{ + CPUCluster *cluster =3D CPU_CLUSTER(dev); + CPUClusterClass *cc =3D CPU_CLUSTER_GET_CLASS(dev); + + if (cc->tcg_clu_ops->collect_cpus) { + cc->tcg_clu_ops->collect_cpus(cluster, errp); + } +} + static void cpu_cluster_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + CPUClusterClass *cc =3D CPU_CLUSTER_CLASS(klass); =20 device_class_set_props(dc, cpu_cluster_properties); dc->realize =3D cpu_cluster_realize; =20 /* This is not directly for users, CPU children must be attached by co= de */ dc->user_creatable =3D false; + +#ifdef CONFIG_TCG + cc->tcg_clu_ops =3D &common_cluster_tcg_ops; +#endif } =20 static const TypeInfo cpu_cluster_type_info =3D { diff --git a/include/hw/cpu/cluster.h b/include/hw/cpu/cluster.h index 644b87350268..c038f05ddc9f 100644 --- a/include/hw/cpu/cluster.h +++ b/include/hw/cpu/cluster.h @@ -55,13 +55,31 @@ */ =20 #define TYPE_CPU_CLUSTER "cpu-cluster" -OBJECT_DECLARE_SIMPLE_TYPE(CPUCluster, CPU_CLUSTER) +OBJECT_DECLARE_TYPE(CPUCluster, CPUClusterClass, CPU_CLUSTER) =20 /* * This limit is imposed by TCG, which puts the cluster ID into an * 8 bit field (and uses all-1s for the default "not in any cluster"). */ -#define MAX_CLUSTERS 255 +#define MAX_TCG_CLUSTERS 255 + +struct TCGClusterOps { + /** + * @collect_cpus: Iterate children CPUs and set cluser_index. + * + * Called when the cluster is realized. + */ + void (*collect_cpus)(CPUCluster *cluster, Error **errp); +}; + +struct CPUClusterClass { + /*< private >*/ + DeviceClass parent_class; + + /*< public >*/ + /* when TCG is not available, this pointer is NULL */ + const struct TCGClusterOps *tcg_clu_ops; +}; =20 /** * CPUCluster: --=20 2.34.1